JPH01183911A - Phase delaying circuit - Google Patents

Abstract

PURPOSE:To easily and suitably set a delaying value by detecting the phase delaying quantity of a delaying clock for a reference clock with a phase delaying detecting circuit and adjusting the charging discharging quantity with a control signal in accordance with the detecting result. CONSTITUTION:In first and second elements 11 and 14, a charging quantity adjusting element 12 and a discharging quantity adjusting element 13, the source of PMOS 41 is connected to a supply voltage Vdd, the source of PMOS 42 is connected to the drain and the drain of the PMOS 42 is connected through a connecting point N to the drain of NMOS 43. Respective gates of the PMOS 41 and an NMOS 44 are commonly connected to a reference clock S and the gate of the PMOS 42 and the NMOS 44 is connected to connecting points N1 and N2 respectively. At the phase delaying circuit, the inverter composed of a PMOS 50 and an NMOS 51 is connected to the connecting point N of the PMOS 42 and the NMOS 43 and a delaying clock R is outputted through the inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase delay circuit that delays a reference clock by a predetermined phase amount.

(Prior Art) Conventionally, there have been delay circuits of this type, such as those shown in FIGS. 2 and 3, for example. The configuration will be explained below.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional delay circuit, and FIG. 3 is an input/output waveform diagram thereof.

This delay circuit consists of a plurality (N) of inverters 1-1 to 1-N connected in cascade with a certain delay 1t (ns>), and a reference clock φi is inserted into the first stage inverter 1-1. Then, the delayed clock φ with the desired delay amount T of t×N (ns>) is input to the subsequent inverter 1-
It was to be output from N.

(Problems to be Solved by the Invention) However, the delay circuit having the above configuration has the following problems.

(a) For example, inverters 1-1 to 1 for obtaining a constant delay it when the period of the reference clock φi is very long.
If the delay value -N is short, in order to obtain the desired amount of delay T, a considerable number of inverters must be inserted, and the area occupied by them will also reach a considerable amount. Furthermore, as the number of inverters increases, the layout (arrangement) thereof becomes difficult, and the wiring loads for each of the inverters 1-1 to 1-H are different, making it difficult to obtain a planned delay value.

(b) The amount of delay is not used as a phase with respect to the clock period, but as an absolute value. In other words, the amount of delay is determined based on the clock period, so if the clock frequency is different, you will have to redesign it. There must be. Further, when the delayed clock is distributed from the delay circuit shown in FIG. 2, there is a disadvantage that the design must be made according to the load to which the delayed clock is distributed.

The present invention solves the problems of the prior art described above, such as an increase in the occupied area due to an increase in the number of delay elements, difficulty in layout and accompanying variation in wiring load, and disadvantages and inconveniences in design. The present invention provides a phase delay circuit that solves the problem.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a phase delay circuit that delays a reference clock by a predetermined phase amount. a phase delay detection circuit that detects an amount of phase delay and outputs a control signal corresponding to the amount of phase delay; a first element that controls charging of electric charge; and a charge amount that adjusts the amount of charge by the first element based on the control signal. an adjusting means, a second element for controlling charge discharge, and a second element for controlling charge discharge based on the control signal.
and a discharge amount adjusting means for adjusting the amount of discharge by the element.

(Function) According to the present invention, since the phase delay circuit is configured as described above, the phase delay detection circuit detects the amount of phase delay of the output delayed clock with respect to the input reference clock, and outputs a control signal in accordance with the delay amount. . Based on this control signal, the first and second
The element adjusts the amount of charge and discharge, makes the amount of charge equal to the amount of discharge, and outputs a delayed clock with a desired amount of phase delay.

As a result, the occupied area can be reduced by reducing the number of delay elements, and the layout can be made more capacitive, and the delay amount can be easily and accurately set without being affected by the load amount or the like. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a phase delay circuit showing an embodiment of the present invention.

This phase delay circuit includes a phase delay detection circuit 10 that detects the amount of phase delay of the output delayed clock R with respect to the input reference clock S and outputs control signals a and b in accordance with the amount of phase delay. Furthermore, a first element 11, a charge amount adjustment element 12, a discharge amount adjustment element 13, and a second element 14 are connected between the power supply potential Vdd and the ground potential Vss, and the charge amount adjustment element 12 and the discharge amount adjustment element 12 are connected to each other. The delay clock R is configured to be output from the connection point N of the amount adjusting element 13. Here, the first element 11 is an element for controlling charge charging, the charge amount adjustment element 12 is an element for adjusting the charge amount by the first element 11 based on the control signal a, and the second element 14 is an element for controlling the charge amount. The element for controlling the discharge of the second element 14 and the discharge amount adjusting element 13 are elements for adjusting the amount of discharge by the second element 14 based on the control signal.

In the above configuration, the phase delay detection circuit 10 detects the amount of phase delay of the output delayed clock R with respect to the input reference clock S, and sends corresponding control signals a and b to the charge amount adjustment element 12 and the discharge amount adjustment element. 13. Thereby, the charge amount is controlled by the charge amount adjustment element 12 and the discharge amount is controlled by the discharge amount adjustment element 13, and a delayed clock R having a desired phase delay amount is obtained from the connection point N.

FIG. 4 is a circuit diagram showing an example of the configuration of the phase delay circuit shown in FIG. 1.

This phase delay circuit consists of complementary MOS transistors (hereinafter referred to as
The phase delay circuit 10 is composed of a P-channel MOS transistor (hereinafter referred to as PM
It is composed of an N-channel MOS transistor (hereinafter referred to as NIVIO8) 20.22, an N-channel MOS transistor (hereinafter referred to as NIVIO8), and inverters 24 to 31, the first element 11 is a PMO 811, the charge amount adjustment cable 12 is a PMO 842, The discharge amount adjustment element 13 is NMO843, and the second cable 1
4 are each composed of NMO844.

In the phase delay detection circuit 10, PMO820 and NM
O321 is connected in series between the power supply potential ■dd and the ground potential ■ss, and the control signal a is output from the connection point N1 between the PMO 820 and NMO 821. Similarly, PMO82
2 and NMO823 are connected to the power supply potential Vdd and the ground potential Vss.
The PMO322 and NMO82 are connected in series between
The control signal S is output from the connection point N2 of No. 3. A signal S-R is generated using the reference clock S, a delayed clock R1 and an inverter 24.26, which is connected to the gate of the PMO 320, and a signal 10.R is generated using an inverter 24.27.30. is connected to the gate of NMO821, feeds the inverter 25.28 and generates the signal S・■,
Connect this to the gate of PMO822, and use inverter 29.31 to generate signal S-R, which is converted to NM
Connected to the gate of O823. In addition, the connection point Nl,
Capacitors Ca and Cb are connected to N2, respectively.

1st. In the second element 11.14, the charge amount adjustment cable 12, and the discharge amount adjustment element 13, PM is applied to the power supply potential ■dd.
The source of O841 is connected, and the drain of PMO8
The source of 42 is connected, and the train of PMO 842 is connected to the drain of NMO 843 via connection point N. Furthermore, NMO843(7)'/-X is NMO8
The source of the NMO 844 is connected to the ground potentials (1) and (S). The gates of the PMO 841 and NIVIO 344 are commonly connected to the reference clock S, and the gates of the PMO 342 and NMO 844 are connected to connection points Nl and N2, respectively.

In the phase delay circuit shown in FIG. 4, PMO342 and NMO
At connection point N of 843, PIVIO850 and NMO85
1 is connected, and a delayed clock R is output through the inverter. This inverter has the function of inverting the signal at the connection point N and shaping the waveform. That is, this inverter is
Assuming that the reference clock S is S and the set phase delay is α, it has the function of subtracting π from the phase of the signal potential generated at the connection point N, leaving only α as the phase delay, and normally its waveform Since it becomes n2m, that is, it becomes rounded, so it has a waveform shaping function of raising the value of m.

5 (1), (2>, and 3) are signal waveform diagrams of FIG. 4, and the operation of FIG. 4 will be explained with reference to these figures. In addition, α in FIG. β is the set delay amount at the time of falling, and β is the set delay amount at the time of falling.

FIG. 5(1) shows a state where the phase is larger than the set delay amount. In such a case, the PMO 822 is turned on by the signal S-R output from the inverter 28, the control signal S on the connection point N2 is charged up at the power supply potential ■dd, and the signal S-R output from the inverter 31 is charged up. -R turns on the NMO 323 and discharges it.

As a result, the control signal, which was initially at a low voltage, is raised to a certain value, changing the NMO843 from high resistance to low resistance.
Increase the speed at which connection point N is charged up.

FIG. 5(2) shows a state where the set delay amount and phase are equal. If the amount of delay is equal to the set delay amount, the amount of charge of the control signal on the connection point N2 is equal to the amount of discharge, so the potential does not change. In other words, N
The resistance value of MO843 has converged to provide the set delay amount.

FIG. 5(3) shows a state where the phase is smaller than the set delay amount. When the delay amount is small, the control signal on the connection point N2 changes from high potential to low potential, and NM
Make O843 high resistance.

In this case, the control signal a on the connection point N1 is controlled by the charge amount adjustment element 12 that determines the amount of delay at the time of falling.
Therefore, the direction of change in potential with respect to speed and slowness is reversed.

Therefore, the point at which the charge amount and the discharge amount of the control signals a and b become equal is the convergence point, and the phase delay amount is determined by the convergence point. In the case of rising, the conductance gm22 of PMO822 and NMO82
3 conductance gm23, in the case of falling, P
MO820 conductance gI1120 and NIV10
It is shown that the ratio of S21 to conductance gII121 determines the phase delay. However, in this case, the following relationship holds: ≧Rising width of reference tarokk S, and I) MO842 and NMO84
The convergence condition is that the disease No. 3 is within a range that can follow the potentials of the control signals a and b.

The phase delay circuits shown in FIGS. 1 and 4 have the following advantages.

(a) When the period of the reference clock is long, the desired amount of delay can be obtained without using a large number of delay elements.

Therefore, the circuit formation area can be reduced.

(b) Since the PMO 342 and NMO 843 are feedback-controlled to adjust the charge/discharge amount, a highly accurate delay amount can be obtained and a certain degree of manufacturing variation can be absorbed.

(c) Since the amount of delay is controlled not by time but by phase, flexibility with respect to the frequency of the reference clock S is high, and furthermore, the amount of delay can be set regardless of the load connected to the subsequent stage of this phase delay circuit. Therefore, the amount of delay can be designed easily and accurately.

(d) Phase delay amount rising (α) and falling (β)
Since the delay clock R can be set freely, the duty ratio of the delayed clock R can also be set.

The phase delay circuit of this embodiment can be applied to, for example, the following fields.

(i) By using N phase delay circuits shown in FIG. 1, a frequency multiplier (device for gradually increasing the frequency) with a free duty ratio N times can be constructed.

(:i) When using a high-frequency clock that cannot be tracked by an input buffer inside a large-scale integrated circuit (LSI), etc., install multiple phase delay circuits as shown in Figure 1 inside the LSI, etc. After inputting a clock through the input buffer, the clock may be converted into a high-frequency clock by the plurality of phase delay circuits before being used.

(iii) Figure 6 is an LSI that shows an application example of Figure 1.
FIG. 2 is a circuit diagram of a clock distributor such as the above. This clock distributor drives the clock φ with an inverter 60 and distributes it to a plurality of inverters 61-1 to 61-3, and then supplies each of the distributed clocks to target loads 62-1 to 62-3, respectively. This is the circuit that does this. Normally, at the time of design, the load amount of the target loads 62-1 to 62-3 is limited to a certain allowable range and the amount of delay of the clock φ is determined, but by changing the target loads etc. If the range is exceeded, it is necessary to redesign the delay times of the inverters 60.61-1 to 61-3. Therefore, by replacing each inverter 61-1 to 61-3 with the phase delay circuit shown in FIG. 1, it becomes possible to set the lock delay amount accurately without being affected by the target loads 62-1 to 62-3. . Therefore, there is no need for detailed design for taro clock skew (clock deviation) inside the LSI or the like, or clock skew with external LSIs, etc., making the design easier and eliminating the need for redesign.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

■ The phase delay circuit in FIG. 4 is configured with CMO8'''C, but it may also be configured with PMO8 alone, NMO8 alone, or a combination of PMO8 and NMO8.Furthermore,
It is also possible to configure the structure shown in FIG. 4 using transistors other than MOS transistors.

(2) In the circuit shown in FIG. 4, the input reference clock S and the output delayed clock R are in the same phase, but an inverter may be added to the output side so that they have opposite phases.

(2) Other circuits may be added to the circuit shown in FIG. 1 to improve accuracy and stability of operation.

(Effects of the Invention) As described in detail above, according to the present invention, the phase delay detection circuit detects the amount of phase delay of the delayed clock with respect to the reference clock, and a control signal corresponding to the detection result is used to detect the amount of charge and discharge. By adjusting the delay elements, the occupied area can be reduced by reducing the number of delay elements, and the layout can be simplified.
Furthermore, the delay value can be easily and accurately set regardless of the amount of load.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase delay circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional delay circuit, FIG. 3 is an input/output waveform diagram of FIG. 2, and FIG. FIG. 5 (1) is a circuit diagram showing an example of the configuration shown in the figure. (2) and (3) are signal waveform diagrams in FIG. 4, and FIG. 6 is a circuit diagram of a clock distributor for explaining an application example of FIG. 1. 11.14...1st. Second element, 12...
...Charge and adjustment element, 13...Discharge amount adjustment element, S...Reference clock, R...Delay clock. Applicant's agent: Sei Kakimoto +7. /4: No. 1. 2nd element 12: Charge@Amount adjusting element 13 Discharge amount adjusting element S: Reference clock delay clock Figure 1 Figure 2 Figure 2 input/output waveform diagram L −−−−−+−−−−−−−
−−J Example of configuration in Figure 1 (+) (2) B<j−
------j Figure 4 Signal waveform diagram Figure 5 Figure 6

Claims (1)

[Scope of Claims] A phase delay detection circuit that detects a phase delay amount of an output delayed clock with respect to an input reference clock and outputs a control signal corresponding to the phase delay amount, a first element that controls charge charging, a charge amount adjusting means for adjusting the amount of charge by the first element based on the control signal; a second element for controlling the discharge of charge; and a discharge amount adjusting means for adjusting the amount of discharge by the second element based on the control signal. and a phase delay circuit with adjustment.