JP2012147220A - Radio communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent erroneous operation of a radio communication apparatus accompanied by the failure of a low-speed oscillation circuit.SOLUTION: A radio communication apparatus includes: a low-speed clock generation means 12; a high-speed clock generation means 10; a receiving means for receiving a clock signal output by the low-speed clock generation means 12 and the high-speed clock generation means 10 to supply the clock signal; a control means 4; and a clock measurement means 16 for measuring the clock number of the high-speed clock signals and the low-speed clock signals. When the low-speed clock frequency calculated based on each clock number in the clock measurement is out of the prescribed range, the control means does not allow the radio communication apparatus to switch into a low consumption power operation mode from a normal mode so as to continuously run the radio communication without halt even the low-speed clock signal halts due to a failure.

Description

  The present invention relates to a radio communication apparatus that periodically shifts from a normal operation mode to a low power consumption operation mode in which power consumption is smaller in order to reduce power consumption.

  In wireless communication devices that require low power consumption due to the power source of batteries, etc., it is necessary to operate at high speed during wireless communication, so operate in the normal operation mode in which internal circuits are operated using high-speed clock signals. However, when wireless communication does not occur, it is necessary to operate the internal circuit using the low-speed clock signal to reduce the power consumption, and to operate in the low power consumption operation mode that supplies the low-speed clock signal only to the necessary circuit. .

  According to Patent Document 1, in a wireless communication device such as a portable terminal in a TDMA communication system, a processor uses a high-speed clock signal output from a high-speed oscillation circuit at the time of a call and reception of a standby logic control signal. After receiving the logic control signal during standby, it operates based on the low-speed clock signal output from the low-speed oscillation circuit until the next logic control signal is received. It is comprised so that may be reduced.

JP-A-8-172389

  However, in Patent Document 1, while waiting for a radio telegram (TDMA signal), the processor attempts to operate by shifting to the low power consumption operation mode, but a problem such as a failure of the low-speed oscillation circuit has occurred, so the low-speed clock When the signal is not supplied, the wireless communication device does not operate when shifting from the normal operation mode to the low power consumption operation mode. Even if the supply of the low-speed clock signal is not stopped, if the frequency of the low-speed clock signal is shifted, the reception timing of the next logic control signal is measured using this shifted low-speed clock signal. There was a problem that the logic control signal could not be received.

  The present invention solves the conventional problems, and provides a wireless communication device capable of continuing wireless communication without stopping operation even when a low-speed clock signal is stopped due to a malfunction such as a circuit or component failure. The purpose is to do.

  The wireless communication apparatus of the present invention receives a low-speed clock generation unit that generates a low-speed clock signal, a high-speed clock generation unit that generates a high-speed clock signal, a clock signal output from the low-speed clock generation unit and the high-speed clock generation unit, A receiving means for supplying a clock signal to the means, and a normal operation mode for controlling the receiving means to supply a low-speed clock signal and a high-speed clock signal to each means or a low-power consumption operation mode for stopping the supply of the high-speed clock signal to each means Control means for setting the operation mode, and clock measurement means for measuring the number of clocks of the high-speed clock signal and the low-speed clock signal under the control of the control means.

If the frequency of the low-speed clock calculated from the number of clocks in the clock measurement means is out of the preset range, the control means does not shift from the normal operation mode to the low power consumption operation mode, thereby reducing the speed. Even when the clock signal is stopped due to a malfunction, wireless communication can be continued without stopping the operation.

  By using the wireless communication apparatus of the present invention, when the frequency of the low-speed clock calculated from the number of clocks in the clock measurement means is out of the preset range, the control means is switched from the normal operation mode to the low power consumption operation mode. By not transitioning to, the low-speed clock signal is not supplied because of a failure such as a failure in the components of the low-speed transmission circuit, and the wireless communication device operates by shifting from the normal operation mode to the low power consumption operation mode. It can be prevented from disappearing. Even if the supply of the low-speed clock signal is not stopped, an unexpected frequency shift occurs in the frequency of the low-speed clock signal, and the wireless signal can be received by measuring the next reception timing with this shifted low-speed clock signal. It is possible to realize wireless communication that is resistant to failure of the low-speed clock generation circuit and has high reliability.

1 is a configuration diagram of a wireless communication system using a wireless communication device according to a first embodiment of the present invention. Sequence diagram of synchronization signal transmission / reception in the first embodiment of the present invention The block diagram of the radio | wireless communication apparatus in 1st embodiment of this invention FIG. 3 is a flowchart of the wireless communication apparatus according to the first embodiment of the present invention.

  According to a first aspect of the present invention, a low-speed clock generation unit that generates a low-speed clock signal, a high-speed clock generation unit that generates a high-speed clock signal, a clock signal output from the low-speed clock generation unit and the high-speed clock generation unit, A receiving means for supplying a clock signal, and a normal operation mode for controlling the receiving means to supply a low-speed clock signal and a high-speed clock signal to each means or a low-power consumption operation mode for stopping the supply of the high-speed clock signal to each means. Control means for setting the operation mode, and clock measurement means for measuring the number of clocks of the high-speed clock signal and the low-speed clock signal under the control of the control means.

  The control means shifts from the normal operation mode to the low power consumption operation mode when the frequency of the low-speed clock calculated from the number of clocks measured by the clock measurement means is in a preset range, and the clock measurement If the frequency of the low-speed clock calculated from the number of clocks measured by means is out of the preset range, the low-speed clock signal is Even when the operation is stopped, wireless communication can be continued without stopping the operation.

  According to a second aspect of the invention, particularly in the first aspect of the invention, wireless communication means for performing wireless communication is provided.

  Then, the control means calculates the frequency of the low-speed clock signal using the number of clocks measured by the clock measurement means during the wireless communication using the wireless communication means, so that only the low-speed clock signal is measured in the normal operation mode. Since there is no need to operate, time is not wasted for measurement, and the frequency of the low-speed clock signal can be measured without an increase in power consumption.

  In a third aspect of the invention, particularly in the second aspect of the invention, the control means controls the wireless communication means to set the wireless continuous reception state when the frequency of the low-speed clock is out of the preset range.

And by notifying that the frequency of the low-speed clock is out of the set range using the response message for wireless message reception, the wireless message can be reliably received, and the response message immediately Can be notified. In addition, since it is possible to take measures such as replacement and repair, it is possible to provide a wireless communication device with excellent maintainability.

  In the fourth invention, particularly in the second or third invention, the control means has a frequency of the low-speed clock that is out of a preset range, and the wireless communication using the wireless communication means is unsuccessful. It is assumed that the operation mode shifts to the low power consumption operation mode and does not operate in the normal operation mode. As a result, even if a frequency shift occurs in the high-speed clock signal, the wireless communication device does not stop, and it is possible to notify the user that the wireless communication cannot be performed due to the occurrence of the frequency shift in the high-speed clock signal using a notification means such as an LED. Can be notified. In addition, it is possible to provide a wireless communication apparatus that can take measures such as replacement and repair and has excellent maintainability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
First, as an example of a wireless communication system using the present wireless communication device, a wireless automatic meter reading system including a parent device, a relay device, and a child device will be described.

  FIG. 1 shows an example of a wireless automatic meter reading system according to the present invention. In FIG. 1, 101 is a parent device, 102 to 104 are child devices belonging to the parent device 101, 201 is a relay device belonging to the parent device 101, 202 to 204 are child devices belonging to the relay device 201, and 301 belongs to the relay device 201. Relay machines 302 to 304 are slave machines belonging to the relay machine 301, and 401 is a relay machine belonging to the relay machine 301.

  The base unit 101 and the relay units 201, 301, 401 periodically transmit a synchronization signal, and each slave unit belonging to each of the base unit 101, the relay units 201, 301, 401 receives the synchronization signal, so that each radio unit Can synchronize with the clocks of the master 101 and the relays 201, 301, 401. Each slave unit performs intermittent reception at the timing of transmission by the parent unit 101 and relay units 201, 301, and 401 to which the slave unit belongs, and performs terminal call communication at the timing of reception by the parent unit 101 and relay units 201, 301, and 401 to which it belongs. be able to.

  The operation of the wireless automatic meter reading system of the present invention will be described below with reference to FIGS. FIG. 2A is a diagram illustrating a state of a synchronization signal that is periodically transmitted from the parent device 101. As shown in FIG. 2A, base unit 101 alternately transmits the first synchronization signal and the second synchronization signal every time T1 seconds.

  The first synchronization signal is immediately transmitted at a timing of 2 × T1 seconds. On the other hand, the second synchronization signal is transmitted after waiting for a random time T3 seconds (where T3 seconds <T2 seconds <T1 seconds) based on the timing T1 seconds after the transmission timing of the first synchronization signal. For example, T1 is 4 seconds, T2 is 100 milliseconds, T3 is 10 milliseconds × n, and n is an integer between 0 and 9 and is randomly selected. The transmission time of the first synchronization signal and 2 is set to 10 milliseconds or less.

  The slave units 102 to 104 and the relay unit 201 receive the synchronization signal shown in FIG. Since the first slave units 102 to 104 and the relay unit 201 do not know at which timing the synchronization signal is transmitted, the reception operation is continued for a time of T1 seconds or more. If the reception operation is continued for a time of T1 seconds or longer, the first synchronization signal or the second synchronization signal can be received without fail. Further, if the reception operation is continued for a time of T1 seconds or more, in addition to receiving the synchronization signal from the parent device 101, it may be possible to receive the synchronization signal from the relay devices 201, 301, and 401. When a plurality of synchronization signals are received, the clock is set to the synchronization signal of the radio with the lowest synchronization signal level and the smallest number of relay stages. For example, the number of relay stages decreases in the order of relay device 401-> relay device 301-> relay device 201-> master device 101. The base unit 101 has 0 relay stages and the smallest number of relay stages.

  When the second synchronization signal is received, there is a random delay of T3 seconds. If the slave units 102 to 104 that receive the second synchronization signal and synchronize with the transmission timing of the first synchronization signal of the master unit 101 do not know how many random times T3 are, the first synchronization signal or the second synchronization signal for each T1 I do not know the base point of the transmission timing of the synchronization signal. Therefore, base unit 101 that transmits the second synchronization signal inserts information indicating how many random delay times T3 are in the signal format of the second synchronization signal, and transmits the second synchronization signal. And the subunit | mobile_unit 102-104 which receives a 2nd synchronizing signal correct | amends T3 second using the information of the random delay time T3 contained in the signal format of a 2nd synchronizing signal, and calculates the base point of the timing of T1 second be able to. By the above operation, the slave units 102 to 104 can synchronize with the synchronous transmission timing T1 second of the master unit 101. Then, the intermittent reception operation is performed at the timing when the first synchronization signal is transmitted, and the first synchronization signal is received.

  FIG. 2B shows the operation of the synchronization signal transmitted by the parent device 101 and the timing at which the child devices 102 to 104 receive the synchronization signal. As shown in FIGS. 2B and 2A, base unit 101 alternately transmits the first synchronization signal and the second synchronization signal. The subunit | mobile_units 102-104 and the relay machine 201 are intermittently received with the period of the integral multiple of the timing of a 1st synchronizing signal, as shown to FIG. 2 (B) (2). When the first synchronization signal is detected, the first synchronization signal is detected at the next intermittent reception timing. If the first synchronization signal cannot be detected, it rises at the timing of the next second synchronization signal, receives the second synchronization signal, and synchronizes again.

  Here, consider a case where there are a plurality of systems shown in FIG. Each system is not synchronized, and the synchronization signal transmitted from each system is in an asynchronous state. When the synchronization signal transmission interval T1 is 4 seconds and the synchronization transmission time is 10 milliseconds, the duty ratio of the synchronous transmission is 1/400, and the probability that the synchronization signals transmitted from the respective systems are asynchronous is low. However, since there is a slight clock error in the synchronization transmission interval T1 of each system, the timing of the synchronization signal transmitted from each system gradually shifts with the passage of time, and the timing of the synchronization signal transmission sometimes coincides. Conceivable.

  Once the timing coincides, the first synchronization signal collides for a long time until the timing shifts due to a clock error. However, since the second synchronization signal is transmitted with a random delay time T3, the probability that the second synchronization signal collides is low even if the synchronization transmission timings of the respective systems coincide. Then, the probability that the second synchronization signal continuously collides becomes lower. That is, even if the synchronization transmission timings of the respective systems coincide with each other and the state in which the first synchronization signals collide and cannot be detected continues, the second synchronization signal does not collide, and therefore the slave units 102 belonging to the respective parent units 101 ˜104 and the relay device 201 can detect the second synchronization signal of the parent device 101 and synchronize it with the clock of the parent device 101.

  FIG. 2C is a diagram for explaining the signal format of the synchronization signal and the synchronization signal receiving method. 2C shows the signal format of the synchronization signal, and FIG. 2C shows the method of receiving the synchronization signal. The synchronization signal format of (1) in FIG. 2C is the first synchronization signal and the signal format of 2 transmitted every T1 seconds shown in FIG. The reception method shown in (2) of FIG. 2 (C) is a reception method when the first synchronization signal or the second synchronization signal is received at the timing (1) of FIG. 2 (B).

  The signal format of the synchronization signal is composed of a redundant bit consisting of repetition of “1010...” And the first synchronization signal or the second synchronization signal. Although the signal format of the first synchronization signal or the second synchronization signal is not shown in the figure, a bit synchronization signal formed by repeating “1010...”, A frame synchronization signal for finding the head of data, And a control signal for synchronizing the clock. The redundant bit length is T4 seconds.

  Even if the slave units 102 to 104 and the relay unit 201 detect the first synchronization signal of the master unit 101 and establish clock synchronization, the slave units 102 to 104 and the relay unit 201 are built in the master unit 101 until the next first synchronization signal is received. A slight clock error occurs between the clock and the clocks built in the slave devices 102 to 104 and the relay device 201.

  In general, a crystal oscillation signal generated using a crystal resonator is used as a reference oscillation source of a watch built in a wireless device. The oscillation frequency error oscillated by the crystal resonator is a maximum of ± 100 ppm in consideration of temperature change and the like. Further, assuming that the oscillation frequency error of the radio that transmits the synchronization signal is a maximum of ± 100 ppm and the oscillation frequency error of the radio that receives the synchronization signal is also a maximum of ± 100 ppm, the relative relationship between the synchronization signal transmission side and the synchronization signal reception side The oscillation frequency error is a maximum of ± 200 ppm.

  For example, if T1 = 4 seconds, the first synchronization signal is transmitted every 2 × T1 = 8 seconds, and the slave units 102 to 104 and the relay device 201 receive the first synchronization signal every 8 × T1 = 32 seconds. The maximum clock error between the parent device 101 and the child devices 102 to 104 and the relay device 201 in the second is 32 seconds × ± 200 ppm = ± 6.4 ms. Therefore, even if a maximum clock error of ± 6.4 msec occurs, the slave units 102 to 104 and the relay unit 201 are 6.4 msec earlier than the transmission timing of the first synchronization signal so that the first synchronization signal can be reliably received. The power of the transmission / reception means is turned on and the timeout time T6 is set. Then, the intermittent reception operation is repeated for T6 seconds at intervals of T5 seconds.

  When the maximum clock error is X, X varies depending on the reception cycle in which the slave units 102 to 104 and the repeater 201 receive the first synchronization signal. The reception cycle is 2 × T1 × N (N is an arbitrary integer), and the maximum clock error ± X is calculated as X = 2 × T1 × N × 200 ppm. Therefore, in consideration of the reception cycle for receiving the first synchronization signal, the slave units 102 to 104 and the relay unit 201 turn on the power of the transmission / reception means earlier than the transmission timing of the first synchronization signal by the maximum clock error X calculated by the calculation formula. Set to ON, and set timeout time to T6. Then, the intermittent reception operation is repeated for T6 seconds at intervals of T5 seconds. T5 <T4 is set.

  T6 is set to 2 × X <T6 in consideration of the maximum clock error ± X. The slave units 102 to 104 and the relay unit 201 can always detect the redundant bit having the length T4 and receive the first synchronization signal during T6 seconds. When the slave units 102 to 104 and the relay unit 201 detect the redundant bit of T4, the timeout period T6 is canceled and reception is continued. The first synchronization signal is about 10 milliseconds, and the maximum clock error ± X is generally set smaller than the length of the first synchronization signal 10 milliseconds in consideration of current consumption. Therefore, the timeout time of T6 is at most twice as long as the length of the first synchronization signal of 10 milliseconds.

  Next, consider a case where the first synchronization signal cannot be received and the second synchronization signal is received. The redundant bit of the second synchronization signal is also T4 long. And the subunit | mobile_unit 102-104 and the relay machine 201 absorb the maximum clock error +/- X similarly to the case of 1st synchronizing signal reception, and the subunit | mobile_unit 102-104 and the relay machine 201 are based on the transmission timing of a 1st synchronizing signal. The power of the transmission / reception means is turned on earlier by the maximum clock error X, and the timeout time T7 is set. The intermittent reception operation is repeated for T7 seconds at intervals of T5 seconds. T5 <T4 is set. T7 is set to (2 × X + T2) <T7 in consideration of the maximum clock error ± X + the maximum value T2 of the random delay time. The slave units 102 to 104 and the relay unit 201 can always detect the redundant bit having the length T4 and receive the second synchronization signal during T7 seconds. In this example, T2 is a maximum of 90 milliseconds and X is about 10 milliseconds, so T7 is set to a value slightly larger than 110 milliseconds.

Note that the synchronization signal transmission timing and the synchronization signal reception timing shown in FIG. 2C are relative clocks between the master device 101 on the synchronization signal transmission side and the slave devices 102 to 104 and the relay device 201 on the synchronization signal reception side. When the error is zero and the relative error is not zero, the synchronization signal transmission timing is shifted back and forth between the maximum clock error ± X with respect to the synchronization signal reception timing.

  The relay device 201, the relay device 301 and the relay device 401, the slave devices 102 to 104, the slave devices 202 to 204, and the 302 slave devices to 304 described above are in the normal operation mode while receiving the first synchronization signal and the second synchronization signal. When the synchronization signal reception operation is completed, the low power consumption operation mode is entered until the next timing synchronization signal reception. Then, the operation of canceling the low power consumption operation mode and shifting to the normal operation mode again is repeated (intermittent reception).

  FIG. 3 is an example of a block diagram of the above-described repeater and slave units, that is, the wireless communication apparatus of the present invention. FIG. 4 is a communication sequence diagram between the microcomputer unit and the external clock unit in the wireless communication apparatus. In FIG. 3, reference numeral 1 denotes a wireless communication device corresponding to a repeater or slave, 2 denotes a microcomputer unit, 3 denotes an external clock unit, and the wireless communication device 1 includes a microcomputer unit 2 and an external clock unit 3.

  The microcomputer unit 2 includes a control unit 4, a reception unit 5, a communication unit 6, an operation mode output unit 7, a wireless communication unit 8, an interrupt reception unit 9, and a high-speed clock generation unit 10. . The control means 4 is responsible for switching between two operation modes, a normal operation mode that operates with a low-speed clock signal and a high-speed clock signal, and a low-power consumption operation mode that operates only with a low-speed clock signal, and control of each means. The receiving means 5 receives the low-speed clock signal from the external clock unit 3 and supplies the low-speed clock signal and the high-speed clock signal to each means. The communication unit 6 sets the clock signal supply timing and the clock signal frequency to the external clock unit 3 under the control of the control unit. The operation mode output unit 7 transmits an operation mode signal for notifying the external clock unit 3 of the normal operation mode or the low power consumption operation mode as the operation mode of the control unit 4. The wireless communication means 8 communicates with a repeater or a slave unit. The interrupt receiving means 9 outputs a high speed clock signal to the receiving means 5 for generating a high speed clock signal. The high-speed clock generation means 10 outputs the interrupt signal received from the external clock unit 3 as a signal for releasing the low power consumption operation mode and shifting to the normal operation mode to the control means 4.

  The external clock unit 3 includes a clock control unit 11, a low-speed clock generation unit 12, a clock output unit 13, a clock interrupt output unit 14, and a clock communication unit 15. The clock control means 11 controls each means. The low-speed clock generation means 12 supplies a low-speed clock signal for operating each means. The clock output means 13 outputs the low-speed clock signal supplied from the low-speed clock generation means 12 to the microcomputer unit 2 under the control of the clock control means 11. The clock interrupt output unit 14 outputs an interrupt signal to the microcomputer unit 2 under the control of the clock control unit 11. The clock communication means 15 communicates with the microcomputer unit 2 and receives the time timing output from the clock interrupt output means 14.

  The microcomputer unit 2 includes clock measurement means 16. The clock measuring means 16 counts and stores the number of clocks of the received high-speed clock signal in the same manner as the low-speed clock signal received via the receiving means 5 using a counter under the control of the control means 4. The low-speed clock signal is generally a clock signal in the kHz band such as 32.768 kHz, and the high-speed clock signal is generally a clock signal in the MHz band such as 11.52 MHz.

  Hereinafter, the operation of the wireless communication device 1 of the present invention will be described with reference to FIGS. 3 and 4.

  The external clock unit 3 is composed of, for example, a crystal resonator and an oscillation circuit in the low-speed clock generation means 12 and generates a low-speed clock signal of 32.768 kHz. The generated low-speed clock signal of 32.768 kHz is supplied to each means, so that the external clock unit 3 operates. The clock control means 11 controls the clock output means 13 to turn on / off the output of the low-speed clock signal to the outside. At power-on (STEP 1), a low-speed clock signal is output from the clock output means 13 to the microcomputer unit 2 (STEP 2).

  On the other hand, the microcomputer unit 2 receives the low speed clock signal of 32.768 kHz output from the clock output means 13 via the receiving means 5 when the power is turned on (STEP 3), and the received low speed clock signal and high speed clock generating means. A high-speed clock signal such as 11.52 MHz generated in step 1 is supplied to each means, and the control means 4 starts operation in an operation mode called a normal operation mode (STEP 4) and receives a synchronization signal using the wireless communication means 8 The wireless reception operation for starting is started (STEP 5). At this time, the clock measurement unit 16 starts a low-speed counter that counts the low-speed clock signal under the control of the control unit 4. At the same time, a high-speed counter that counts high-speed clock signals is also started (STEP 6). Then, at the end of wireless reception, the counter value of the previous low-speed clock signal and the counter value of the high-speed clock are stored under the control of the control means 4 (STEP 7). Then, the control means 4 calculates the frequency of the low-speed clock signal from the counter value counted up during the wireless communication (STEP 8). In the calculation method, since the cycle of the low-speed clock signal is 1 / 32.768 kHz, the counter value is incremented every cycle. Since the cycle of the high-speed clock signal is 1 / 11.52 MHz, the counter value is incremented every cycle. Further, as described above, the frequency deviation of the low-speed clock signal generally has a deviation of about ± 200 ppm. However, since the frequency deviation of the high-speed clock signal performs wireless communication using the wireless communication means 8, Is about ± 4 ppm. That is, the frequency deviation of the low-speed clock signal can be calculated based on how many times the high-speed clock counter counts during the low-speed clock count-up. Since the message length of the synchronization signal is about 10 milliseconds as described above, the value of the low-speed counter is considered to be about 10 milliseconds / (1 / 32.768 kHz). Next, if the calculated frequency deviation is within ± 200 ppm, for example, the control means 4 shifts to the low power consumption operation mode as described below. On the other hand, if the control means 4 is out of the range, the control means 4 controls the wireless communication means 8 while maintaining the normal operation mode, and sets the wireless continuous reception mode for waiting for a wireless message continuously (STEP 9). If the first synchronization signal or the second synchronization signal is received and if the reception is successful, the frequency of the low-speed clock signal has changed in the response message after the reception of this synchronization signal for the master unit or the relay unit A response message including is returned (STEP 10).

  However, if the first synchronization signal or the second synchronization signal transmitted by the master unit or the slave unit at the interval of T1 is not received even when waiting in the continuous reception state under the control of the control unit 4, the high-speed clock generated by the high-speed clock generation unit 10 It is determined that the frequency of the clock signal is shifted. Then, the control means 4 shifts from the normal operation mode to the low power consumption operation mode (STEP 11), and controls the display means (not shown) such as LED and the buzzer (not shown) to control the frequency of the high-speed clock signal. It is also possible to notify that there is a possibility that they are shifted. At this time, if the operation mode output means 7 is used to transmit to the external clock unit 3 that the mode has been shifted to the low power consumption operation mode, the low-speed clock signal is not supplied from the external clock unit 3 to the microcomputer unit 2, and an LED or the like is displayed. Since the means (not shown) cannot be controlled, the operation mode output means 7 keeps transmitting the signal in the normal operation mode.

Next, when the reception of the synchronization signal is completed and the frequency deviation of the low-speed clock signal is within the range, the control unit 4 uses the communication unit 6 to perform the normal operation from the low power consumption operation mode. Set to return to mode. That is, the time timing information of the signal output by the clock interrupt output means 14 is transmitted to the external clock unit 3 and set (for example, as described above, the time obtained by subtracting α seconds from 8 × T1 = 32 seconds is set. α seconds is the processing time in the external clock unit 3). When the interrupt receiving means 9 receives an interrupt signal from the clock interrupt output means 14, an interrupt permission setting for permitting the control means 4 to output a signal to that effect is performed, and the high-speed clock generating means 10 The supply of the generated high-speed clock signal to each means is stopped, the receiving means 5 is controlled to stop the supply of the low-speed clock signal of 32.768 kHz to each means other than the control means 4, and the operation mode output means 7 In response to this, a signal instructing transmission of an operation mode signal indicating the transition to the low power consumption operation mode is output, and the transition to the low power consumption operation mode is made (STOP operation mode).

  Next, in the external clock unit 3, the clock control unit 11 receives the previous time timing information (32 seconds−α seconds) via the clock communication unit 15. Further, when the microcomputer unit 2 from the operation mode output means 7 receives the operation mode signal indicating that the microcomputer 2 has shifted to the low power consumption operation mode, it controls the clock output means 13 to stop the output of the low-speed clock signal to the receiving means 5. To do. Then, the internal timer is activated to shift to the low power consumption operation mode, and waits until the time included in the time timing information elapses. When this timer expires, the clock control means 11 controls the clock output means 13 to start outputting a low speed clock signal of 32.768 kHz, and sends an interrupt signal to the microcomputer section 2 to the clock interrupt output means 14. A signal instructing the transmission of is output.

  Next, in the microcomputer unit 2, the receiving unit 5 supplies the low-speed clock signal to the control unit 4. Then, the interrupt receiving means 9 receives the previous interrupt signal and outputs a signal notifying that it has been received to the control means 4. The control means 4 is triggered by the reception of this signal to start the supply of the 32.768 kHz clock signal and the high-speed clock signal to each means in the low power consumption operation mode (SLOW operation mode), and then shifts to the normal operation mode. Then, the wireless communication means 8 is used to receive the synchronization signal.

  The normal operation mode is an operation mode in which a low-speed clock signal and a high-speed clock signal are supplied to the microcomputer unit 2 and operates with the high-speed clock signal, and is sometimes referred to as a normal mode or a high-speed mode.

  The low power consumption operation mode means that the microcomputer unit 2 does not operate with a high-speed clock signal, operates only with a low-speed clock signal of 32.768 kHz, does not operate in an operation mode called SLOW operation mode, or both, and operates in SLOW mode. Two operation modes called a STOP operation mode, which is a further low power consumption operation mode compared to the mode, can be considered and may be called a standby mode. Here, the method of shifting to the STOP in which the supply of the low-speed clock signal is stopped from the external clock unit 3 has been described. However, in order to simplify the configuration and control of the external clock unit 3, the clock control unit 11 outputs the operation mode. It can be considered that the signal from the means 7 is ignored or the clock control means 11 is omitted, and the clock output means 13 always outputs a low-speed clock signal of 32.768 kHz.

  In this embodiment, the clock measuring unit 16 counts the low-speed clock signal and the high-speed clock signal, and the frequency deviation (frequency deviation) is calculated by the control unit 4. However, the clock measuring unit 16 calculates the calculation result. Is also conceivable to output to the control means 4.

  In the present embodiment, the control unit 4 has been described as calculating the frequency of the low-speed clock signal using the number of clocks measured by the clock measurement unit 16 during the wireless communication using the wireless communication unit 8. You don't have to measure the frequency every time. Further, when the frequency cannot be measured during wireless communication from the processing speed of the control means 4 and the number of counters used, it can be similarly performed after the wireless communication.

  In this embodiment, when the frequency shift of the low-speed clock signal occurs, the control means 4 stores these in a non-volatile memory (not shown) such as an EEPROM memory, so that the contents of the malfunction of the wireless communication apparatus 1 are stored. It is also conceivable that the configuration can be easily analyzed.

  The microcomputer unit 2 may be a microcomputer, which is a circuit in which a CPU and a memory are integrated on one LSI chip. As the external clock unit 3, an RTC (Real-time clock) can be considered. An external output of a clock signal of 32.768 kHz, an output of an interrupt signal after a time set by a microcomputer, an output of clock data, calendar data An LSI specialized in low-voltage operation and low power consumption having an output function can be considered.

  The wireless automatic meter reading system using the wireless communication device 1 of the present invention can be used for gas and electric power automatic meter reading systems. A gas meter is connected to the slave units 102 to 104, 202 to 204, and 302 to 304, and gas meter reading data of the gas meter connected to the slave units 102 to 104, 202 to 204, and 302 to 304 by polling communication from the master unit 101 Can be collected in the parent device 101. The collected gas meter reading data can be sent to the center server using a public line connected to the master unit 101. Further, the relay devices 201, 301, 401 also have a function as slave units, and a gas meter may be connected thereto.

  The clock signal supply control to each means is performed by the control means 4 controlling the receiving means 5. However, each means has an input ON / OFF function of the clock signal, and the control means 4 performs each control. It is also conceivable that each means is controlled.

  Note that communication methods of the communication unit 6 in the microcomputer unit 2 and the clock communication unit 15 in the external clock unit 3 are generally used I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), 3-Wire. A serial bus called can be considered. If these communication methods are used, since the microcomputer unit 2 normally has these functions, it is not necessary to add a new function to communicate with the external clock unit 3. Cost reduction can be achieved. Further, since a general RTC can be used as the external clock unit 3, it is easy to change the external clock unit 3 to reduce power consumption.

  In the present embodiment, the wireless communication device 1 has been described as being divided into the microcomputer unit 2 and the external clock unit 3. However, the microcomputer unit 2 may include a means for the external clock unit 3.

  Note that the reason why the low-speed clock signal generated by the low-speed clock generation means 12 is not supplied to the microcomputer unit 2 is that the wiring is broken, the component is open / short-circuited, the component is not mounted correctly, the low-speed clock generation unit 12 There may be a defect in the crystal unit. In particular, since the crystal unit has a structure in which a crystal piece is bonded to a metal or resin case, if a foreign object such as dust enters during the manufacture of the crystal unit, the oscillation frequency may shift, Oscillation may stop. Also, the amount of frequency shift varies depending on the location of dust, etc., and when the dust comes off the crystal piece, the stopped vibrator may start oscillating again.

As described above, when the wireless communication apparatus 1 according to the present invention is used, the control unit 4 is normally used when the frequency of the low-speed clock calculated from the number of clocks measured by the clock measurement unit 16 is out of the preset range. By not shifting from the operation mode to the low power consumption operation mode, a problem such as a failure of the low speed clock generation means 12 occurs, so that the low speed clock signal is not supplied, and the normal operation mode is shifted to the low power consumption operation mode. Thus, it is possible to prevent the wireless communication device 1 from operating. Even if the supply of the low-speed clock signal is not stopped, an unexpected frequency shift occurs in the frequency of the low-speed clock signal, and the synchronization signal can be received by measuring the next reception timing with this shifted low-speed clock signal. It is possible to realize wireless communication that is robust against failures related to the low-speed clock signal and highly reliable.

  As described above, when the frequency of the low-speed clock is out of the preset range, the wireless communication device according to the present invention does not shift from the normal operation mode to the low-power consumption operation mode, so that the low-speed clock signal Even when the wireless communication device is stopped due to a malfunction such as a failure, it is possible to realize a wireless communication device capable of continuous wireless communication without stopping the operation of the wireless communication device itself.

DESCRIPTION OF SYMBOLS 1 Wireless communication apparatus 2 Microcomputer part 3 External clock part 4 Control means 5 Reception means 6 Communication means 7 Operation mode output means 8 Wireless communication means 9 Interrupt reception means 10 High-speed clock generation means 11 Clock control means 12 Low-speed clock generation means 13 Clock output Means 14 Clock interrupt output means 15 Clock communication means 16 Clock measurement means 101 Master unit 102 to 104, 202 to 204, 302 to 304 Slave unit 201, 301, 401 Relay unit

Claims (4)

In a wireless communication device comprising an external clock unit and a microcomputer unit that operates with a clock signal output from the external clock unit,
The external clock unit includes low-speed clock generation means for generating a low-speed clock signal, high-speed clock generation means for generating a high-speed clock signal,
The microcomputer unit includes: a communication unit that performs wireless communication; a low-speed clock generation unit; a reception unit that receives a clock signal output from the high-speed clock generation unit and supplies the clock signal to the communication unit; and a low-speed clock to the communication unit Control means for setting an operation mode of a normal operation mode for supplying a signal and a high-speed clock signal or a low-power consumption operation mode for stopping supply of a high-speed clock signal to the communication means; A clock measuring means for measuring the number of clocks,
The control means shifts from a normal operation mode to a low power consumption operation mode when the frequency of the low-speed clock calculated from the number of clocks measured by the clock measurement means is within a preset range, and the clock measurement means A wireless communication apparatus that does not shift from the normal operation mode to the low power consumption operation mode when the frequency of the low-speed clock calculated from the number of clocks measured in step 1 is out of a preset range. The microcomputer unit includes wireless communication means for performing wireless communication,
2. The wireless communication apparatus according to claim 1, wherein the control means calculates the frequency of the low-speed clock signal using the number of clocks measured by the clock measurement means during wireless communication using the wireless communication means. When the frequency of the low-speed clock signal is out of the preset range, the control means controls the wireless communication means to set the wireless continuous reception state, and uses the response message for wireless message reception to use the low-speed clock signal. The wireless communication apparatus according to claim 2, wherein a notification is made that the frequency is out of the set range. When the frequency of the low-speed clock signal is out of the preset range and the wireless communication using the wireless communication means is unsuccessful, the control means shifts to the low power consumption operation mode and operates in the normal operation mode. The wireless communication apparatus according to claim 2 or 3, wherein the wireless communication apparatus is not used.

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