JP5332775B2 - Electronic component and manufacturing method thereof - Google Patents

Electronic component and manufacturing method thereof Download PDF

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JP5332775B2
JP5332775B2 JP2009066050A JP2009066050A JP5332775B2 JP 5332775 B2 JP5332775 B2 JP 5332775B2 JP 2009066050 A JP2009066050 A JP 2009066050A JP 2009066050 A JP2009066050 A JP 2009066050A JP 5332775 B2 JP5332775 B2 JP 5332775B2
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substrate
semiconductor element
electronic component
carbon nanotubes
protruding
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JP2010219397A (en
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浩三 清水
誠樹 作山
正孝 水越
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Fujitsu Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

本発明は、回路基板上に半導体素子を搭載した電子部品及びその製造方法に関する。   The present invention relates to an electronic component in which a semiconductor element is mounted on a circuit board and a manufacturing method thereof.

電子部品の高密度実装化への要求が年々強くなっている現在、ベアチップ実装方式が注目されている。また、ベアチップ実装における接続方式は、ワイヤボンディング法によるフェイスアップ実装から、半導体素子の電極上に形成した突起状端子を回路基板に直接接続するフェイスダウン実装へと変化してきている。フェイスダウン実装は、ワイヤボンディングに比べて接続端子間の距離を短くできることから、多端子での接続を容易に実現できるとともに、大容量の信号を高速で伝達できるなど電気的な特性に優れた接続方式である。   Currently, the demand for high-density mounting of electronic components is increasing year by year, and the bare chip mounting method is attracting attention. Further, the connection method in the bare chip mounting has been changed from the face-up mounting by the wire bonding method to the face-down mounting in which the protruding terminals formed on the electrodes of the semiconductor element are directly connected to the circuit board. Face-down mounting can shorten the distance between connection terminals compared to wire bonding, so connection with multiple terminals can be easily realized, and connections with excellent electrical characteristics such as high-capacity signals can be transmitted at high speed. It is a method.

フェイスダウン実装では、半導体素子上に形成した突起状端子を用いて回路基板に接続した後、半導体素子と回路基板との間にアンダーフィル接着材を充填し、突起電極に加わる応力を分散させる方法が一般的に採用されている。   In face-down mounting, after connecting to a circuit board using a protruding terminal formed on a semiconductor element, an underfill adhesive is filled between the semiconductor element and the circuit board to disperse the stress applied to the protruding electrode. Is generally adopted.

特開2001−177052号公報JP 2001-177052 A 特開2002−141633号公報JP 2002-141633 A 特開2007−311700号公報JP 2007-311700 A

上述したように、半導体素子は、アンダーフィル接着剤を介して回路基板上に搭載されており、半導体素子と回路基板との間の熱膨張差は、歪み、反りなどを引き起こす原因となる。特に近年では、高機能化、高密度化、低コスト化の流れの中で、回路基板内の銅配線密度が高まっている。銅の熱膨張係数は17ppm/℃と高い故に、回路基板の熱膨張係数も、半導体素子の4ppm/℃に比べて拡大する傾向にある。   As described above, the semiconductor element is mounted on the circuit board via the underfill adhesive, and the thermal expansion difference between the semiconductor element and the circuit board causes distortion, warpage, and the like. Particularly in recent years, the density of copper wiring in circuit boards has increased in the trend of higher functionality, higher density, and lower costs. Since the thermal expansion coefficient of copper is as high as 17 ppm / ° C., the thermal expansion coefficient of the circuit board also tends to be larger than that of the semiconductor element of 4 ppm / ° C.

このような状況は、接点接続の維持が困難になることのみならず、実稼働環境において多大なストレスを引き起こし、半導体素子の割れ、接合部の破壊などの劣化を招く虞があり、信頼性を十分に満足させることが困難であった。   Such a situation not only makes it difficult to maintain the contact connection, but also causes great stress in the actual operating environment, which may lead to deterioration such as cracking of the semiconductor element and destruction of the joint, and reliability is improved. It was difficult to fully satisfy.

本発明の目的は、回路基板と半導体素子との間の接点接続を維持しつつ回路基板から半導体素子へ加わる応力を効果的に緩和することができる電子部品及びその製造方法を提供することにある。   An object of the present invention is to provide an electronic component that can effectively relieve stress applied from a circuit board to a semiconductor element while maintaining contact connection between the circuit board and the semiconductor element, and a method for manufacturing the same. .

実施形態の一観点によれば、第1の基板と、前記第1の基板上に形成され、突起状端子を介して前記第1の基板に電気的に接続された第2の基板とを有し、前記突起状端子は、前記第2の基板に接合され、前記第1の基板側の端部に選択的に形成された導電性の被膜を有する炭素元素の第1の線状構造体の束と、前記第1の基板に接合され、前記第2の基板側の端部に選択的に形成された導電性の被膜を有する炭素元素の第2の線状構造体の束とを含み、前記第1の線状構造体の束と前記第2の線状構造体の束とが互いに噛み合うことにより、前記第1の基板と前記第2の基板とが電気的に接続されている電子部品が提供される。
According to one embodiment of the present invention, there is provided a first substrate and a second substrate formed on the first substrate and electrically connected to the first substrate through a protruding terminal. The protruding terminal is bonded to the second substrate, and the first linear structure body of carbon element having a conductive film selectively formed at an end portion on the first substrate side. A bundle and a bundle of carbon element second linear structures having a conductive film bonded to the first substrate and selectively formed at an end portion on the second substrate side, An electronic component in which the first substrate and the second substrate are electrically connected to each other when the bundle of the first linear structures and the bundle of the second linear structures are engaged with each other. Is provided.

また、実施形態の他の観点によれば、第1の基板上に、炭素元素の線状構造体の束の第1の突起状端子を形成する工程と、前記第1の突起状端子の先端部に、導電性の第1の被膜を選択的に形成する工程と、第2の基板上に、炭素元素の線状構造体の束の第2の突起状端子を形成する工程と、前記第2の突起状端子の先端部に、導電性の第2の被膜を選択的に形成する工程と、前記第2の基板を前記第1の基板上に搭載し、前記第1の突起状端子と前記第2の突起状端子とを噛み合わせることにより、前記第1の基板と前記第2の基板とを電気的に接続する工程とを有する電子部品の製造方法が提供される。
According to another aspect of the embodiment, a step of forming a first protruding terminal of a bundle of linear structures of carbon elements on a first substrate, and a tip of the first protruding terminal A step of selectively forming a conductive first film on a portion, a step of forming a second protruding terminal of a bundle of linear structures of carbon elements on a second substrate, A step of selectively forming a conductive second film on the tip of each of the two protruding terminals, mounting the second substrate on the first substrate, and There is provided an electronic component manufacturing method including a step of electrically connecting the first substrate and the second substrate by meshing with the second protruding terminal.

開示の電子部品及びその製造方法によれば、先端部に被膜が形成された炭素元素の線状構造体の束の突起状端子を突き合わせて接触接合するので、炭素元素の線状構造体の内面及び表面を電流経路として利用することができる。これにより、炭素元素の線状構造体だけの突起状端子の場合と比較して、1桁程度低い低抵抗の接合体を実現することができる。また、線状構造体の束の突起状端子は、低荷重の押し込みによって噛み合わせることができるので、線状構造体が過度に撓むなどによって隣接端子とショートすることを防止することができる。また、突起状端子が噛み合った状態が保持されるため、接触接合後に位置ずれが生じることを防止することができる。   According to the disclosed electronic component and the method of manufacturing the same, the protruding terminals of the bundle of carbon element linear structures having a coating formed on the tip portion are abutted and contact-bonded, so that the inner surface of the carbon element linear structure And the surface can be used as a current path. As a result, it is possible to realize a low-resistance bonded body that is about an order of magnitude lower than that in the case of a protruding terminal having only a carbon element linear structure. Further, since the protruding terminals of the bundle of linear structures can be engaged with each other by pressing with a low load, it is possible to prevent the linear structures from being short-circuited with the adjacent terminals due to excessive bending. Moreover, since the state in which the protruding terminals are engaged with each other is maintained, it is possible to prevent the positional deviation from occurring after the contact bonding.

図1は、一実施形態による電子部品の構造を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing the structure of an electronic component according to an embodiment. 図2は、一実施形態による電子部品における突起状端子の構造の一例を示す概略図である。FIG. 2 is a schematic diagram illustrating an example of a structure of a protruding terminal in an electronic component according to an embodiment. 図3は、一実施形態による電子部品における突起状端子の接続状態の一例を示す概略図である。FIG. 3 is a schematic diagram illustrating an example of a connection state of the protruding terminals in the electronic component according to the embodiment. 図4は、一実施形態による電子部品の製造方法を示す工程断面図(その1)である。FIG. 4 is a process cross-sectional view (part 1) illustrating the method of manufacturing the electronic component according to the embodiment. 図5は、一実施形態による電子部品の製造方法を示す工程断面図(その2)である。FIG. 5 is a process cross-sectional view (part 2) illustrating the method of manufacturing the electronic component according to the embodiment. 図6は、一実施形態による電子部品の製造方法を示す工程断面図(その3)である。FIG. 6 is a process cross-sectional view (part 3) illustrating the method for manufacturing the electronic component according to the embodiment.

一実施形態による電子部品及びその製造方法について図1乃至図6を用いて説明する。   An electronic component and a manufacturing method thereof according to an embodiment will be described with reference to FIGS.

図1は、本実施形態による電子部品の構造を示す概略断面図である。図2は、本実施形態による電子部品における突起状端子の構造の一例を示す概略図である。図3は、本実施形態による電子部品における突起状端子の接続状態の一例を示す概略図である。図4乃至図6は、本実施形態による電子部品の製造方法を示す工程断面図である。   FIG. 1 is a schematic cross-sectional view showing the structure of the electronic component according to the present embodiment. FIG. 2 is a schematic view showing an example of the structure of the protruding terminals in the electronic component according to the present embodiment. FIG. 3 is a schematic diagram illustrating an example of a connection state of the protruding terminals in the electronic component according to the present embodiment. 4 to 6 are process cross-sectional views illustrating the method of manufacturing the electronic component according to the present embodiment.

はじめに、本実施形態による電子部品の構造について図1乃至図3を用いて説明する。   First, the structure of the electronic component according to the present embodiment will be described with reference to FIGS.

回路基板30上には、半導体素子10が搭載されている。回路基板30には、所定の配線パターン(図示せず)と、半導体素子10との間で電気的接続を行うための接続電極32が形成されている。半導体素子10は、多数のトランジスタその他の素子や多層配線層(図示せず)が形成された基板12と、外部接続端子であるパッド電極14とを有している。半導体素子10のパッド電極14は、カーボンナノチューブの束によって形成された突起状端子20,34により、回路基板30の接続電極32に電気的に接続されている。半導体素子10は、枠体38によって支持され、接着剤40によって回路基板30に固定されている。   A semiconductor element 10 is mounted on the circuit board 30. On the circuit board 30, a connection electrode 32 for electrical connection between a predetermined wiring pattern (not shown) and the semiconductor element 10 is formed. The semiconductor element 10 includes a substrate 12 on which a large number of transistors and other elements and a multilayer wiring layer (not shown) are formed, and a pad electrode 14 that is an external connection terminal. The pad electrode 14 of the semiconductor element 10 is electrically connected to the connection electrode 32 of the circuit board 30 by the protruding terminals 20 and 34 formed by a bundle of carbon nanotubes. The semiconductor element 10 is supported by a frame body 38 and fixed to the circuit board 30 by an adhesive 40.

半導体素子10のパッド電極14上に形成された突起状端子20は、例えば図2に示すように、垂直方向に配向したカーボンナノチューブ20aと、カーボンナノチューブ20aの先端部に形成された被膜22を有している。同様に、回路基板30の接続電極32上に形成された突起状端子34は、垂直方向に配向したカーボンナノチューブ34aと、カーボンナノチューブ34aの端部に形成された被膜36を有している。突起状端子20と突起状端子34とは、例えば図3に示すように、カーボンナノチューブ20aとカーボンナノチューブ36aとが被膜22,36が形成された端部において互いに噛み合うように配置されており、これによって電気的接続がなされている。   For example, as shown in FIG. 2, the protruding terminal 20 formed on the pad electrode 14 of the semiconductor element 10 has a carbon nanotube 20a oriented in the vertical direction and a coating 22 formed at the tip of the carbon nanotube 20a. doing. Similarly, the projecting terminal 34 formed on the connection electrode 32 of the circuit board 30 has a carbon nanotube 34a oriented in the vertical direction and a coating 36 formed on the end of the carbon nanotube 34a. For example, as shown in FIG. 3, the protruding terminals 20 and the protruding terminals 34 are arranged so that the carbon nanotubes 20a and the carbon nanotubes 36a mesh with each other at the end portions where the coatings 22 and 36 are formed. The electrical connection is made.

このように、本実施形態による電子部品は、回路基板30と半導体素子10とを接続する突起状端子20,34が、先端部に被膜22,36を有するカーボンナノチューブ20a,34aの束により形成されている。そして、突起状端子20の端部と突起状端子34の端部とが互いに噛み合うことにより、パッド電極14と接続電極32との間が電気的に接続されている。   As described above, in the electronic component according to the present embodiment, the protruding terminals 20 and 34 that connect the circuit board 30 and the semiconductor element 10 are formed by a bundle of carbon nanotubes 20a and 34a having the coatings 22 and 36 at the tip portions. ing. Then, the end portion of the protruding terminal 20 and the end portion of the protruding terminal 34 are engaged with each other, whereby the pad electrode 14 and the connection electrode 32 are electrically connected.

突起状端子20,34を形成するカーボンナノチューブは、低抵抗であるが故に、大電流を流すことが可能である。また、カーボンナノチューブは高い弾力性(バネ性)を有するため、コネクタのような接点接続で接続を維持することが可能である。更に、この接点接続は、回路基板30と半導体素子10との間の熱膨張係数差に起因した応力を、カーボンナノチューブが変形することにより吸収できるという効果も奏する。   Since the carbon nanotubes forming the protruding terminals 20 and 34 have a low resistance, a large current can flow. Further, since the carbon nanotube has high elasticity (spring property), the connection can be maintained by contact connection such as a connector. Furthermore, this contact connection also has an effect that the stress caused by the difference in thermal expansion coefficient between the circuit board 30 and the semiconductor element 10 can be absorbed by the deformation of the carbon nanotubes.

一般的なフェイスダウン実装では、回路基板と半導体素子とを突起状端子で接続した後、アンダーフィルと呼ばれる封止剤を回路基板と半導体素子の間の隙間に充填し、突起状端子に加わる応力を分散している。しかしながら、突起状端子としてカーボンナノチューブ束を用いた場合にも同様の手法を用いると、アンダーフィル封止剤によってカーボンナノチューブによる効果が阻害される虞がある。   In general face-down mounting, the circuit board and the semiconductor element are connected to each other with a protruding terminal, and then a sealant called underfill is filled in the gap between the circuit board and the semiconductor element to apply stress to the protruding terminal. Is distributed. However, when a similar method is used even when a carbon nanotube bundle is used as the protruding terminal, the effect of the carbon nanotubes may be hindered by the underfill sealant.

すなわち、突起状端子としてカーボンナノチューブの束を用いた場合、アンダーフィルを充填/硬化すると、カーボンナノチューブがアンダーフィル封止剤に濡れ、更に硬化によって固定されるため、カーボンナノチューブに期待されるバネ性が損なわれてしまう。また、カーボンナノチューブ間の間隔が大きいと、アンダーフィルがカーボンナノチューブ間に入り込み、一層バネ性が低下してしまう。   In other words, when a bundle of carbon nanotubes is used as the projecting terminal, if the underfill is filled / cured, the carbon nanotubes get wet with the underfill sealant and are fixed by curing, so that the spring property expected for the carbon nanotubes Will be damaged. Moreover, when the space | interval between carbon nanotubes is large, an underfill will penetrate | invade between carbon nanotubes, and spring property will fall further.

カーボンナノチューブを用いた他の実装方法としては、半導体素子を回路基板に載置した後、半導体素子の周囲を構造体で固定する方法も考えられる。しかしながら、位置合わせ載置後に位置ずれすることなく固定するのは非常に困難である。また、接点接触であるが故に、固定するためのプロセスでの位置ずれや加圧不足によって十分な接触面積が確保できない、接点接続であり金属結合と比較すると電気抵抗は一桁以上大きい、などの理由により電気抵抗が高くなる虞がある。荷重をかけた押し込みによって接続抵抗の低抵抗化を達成することが可能であるが、100μm程度の狭ピッチの接合においては、カーボンナノチューブの過剰な撓み性によって隣接端子とショートする虞もある。   As another mounting method using carbon nanotubes, a method of fixing the periphery of the semiconductor element with a structure after mounting the semiconductor element on a circuit board is also conceivable. However, it is very difficult to fix without positioning after positioning. In addition, because of contact contact, a sufficient contact area cannot be secured due to misalignment or insufficient pressurization in the fixing process, contact resistance is greater than an electrical resistance compared to metal bonding, etc. There is a possibility that the electric resistance becomes high for the reason. Although it is possible to reduce the connection resistance by pressing under load, in joining with a narrow pitch of about 100 μm, there is a risk of shorting with an adjacent terminal due to excessive flexibility of the carbon nanotubes.

この点、本実施形態による電子部品では、回路基板30と半導体素子10とが、カーボンナノチューブの束によって形成された突起状端子20,34により電気的に接続されている。そして、回路基板30と半導体素子10との間には、アンダーフィル接着剤は充填されていない。したがって、突起状端子20,34としてカーボンナノチューブの束を用いた場合にも、カーボンナノチューブのバネ性が損なわれることはない。突起状端子20の端部と突起状端子34の端部とは互いに噛み合っており、回路基板30上に半導体素子10を載置した後に位置ずれが生じるのを防止することができる。   In this regard, in the electronic component according to the present embodiment, the circuit board 30 and the semiconductor element 10 are electrically connected by the protruding terminals 20 and 34 formed by a bundle of carbon nanotubes. The underfill adhesive is not filled between the circuit board 30 and the semiconductor element 10. Therefore, even when a bundle of carbon nanotubes is used as the protruding terminals 20 and 34, the spring properties of the carbon nanotubes are not impaired. The end portions of the protruding terminals 20 and the end portions of the protruding terminals 34 are engaged with each other, so that it is possible to prevent the positional deviation from occurring after the semiconductor element 10 is placed on the circuit board 30.

また、突起状端子20の端部と突起状端子34の端部とが噛み合うことにより、カーボンナノチューブ20aは、直接或いは被膜22を介して間接的に、カーボンナノチューブ34a及び/又は被膜36に接続することができる。同様に、カーボンナノチューブ34aは、直接或いは被膜26を介して間接的に、カーボンナノチューブ20a及び又は被膜22に接続することができる。したがって、カーボンナノチューブの端部に被膜を形成しない場合と比較して、突起状端子20と突起状端子34との間の接触面積を増加することができる。カーボンナノチューブはチューブの内面に電流経路が存在するといわれているが、被膜を形成することによりカーボンナノチューブの外面にも電流経路を形成することができる。これにより、接触面積増加の効果と相俟って、突起状端子20と突起状端子34との間の接続抵抗を低減することができる。   Further, the end of the protruding terminal 20 and the end of the protruding terminal 34 are engaged with each other, whereby the carbon nanotube 20 a is connected to the carbon nanotube 34 a and / or the coating 36 directly or indirectly through the coating 22. be able to. Similarly, the carbon nanotubes 34 a can be connected to the carbon nanotubes 20 a and / or the coating 22 directly or indirectly through the coating 26. Therefore, the contact area between the projecting terminal 20 and the projecting terminal 34 can be increased as compared with the case where a film is not formed at the end of the carbon nanotube. Carbon nanotubes are said to have a current path on the inner surface of the tube, but a current path can also be formed on the outer surface of the carbon nanotube by forming a coating. Thereby, combined with the effect of increasing the contact area, the connection resistance between the protruding terminal 20 and the protruding terminal 34 can be reduced.

また、半導体素子10と回路基板30との間に過剰な荷重を加えることなく接続抵抗を低減できるため、カーボンナノチューブが過剰に撓むことを防止することができ、狭ピッチ接合における隣接端子間ショートを防止することが可能となる。   Further, since the connection resistance can be reduced without applying an excessive load between the semiconductor element 10 and the circuit board 30, it is possible to prevent the carbon nanotubes from being excessively bent and to short between adjacent terminals in a narrow pitch junction. Can be prevented.

したがって、このような電子部品を形成することにより、半導体素子10と回路基板30との間に加わる機械的ストレスや熱的ストレスを、バネ性が維持されたカーボンナノチューブ束の突起状端子22により効果的に吸収することができる。また、突起状端子20の端部と突起状端子34の端部とが噛み合うことにより、突起状端子20と突起状端子34との間の位置ずれを防止できるとともに、接続抵抗を低減することができる。これにより、半導体素子10と回路基板30との間の良好な接点接続を維持することができ、半導体素子10の長期にわたる動作保証が可能となる。   Therefore, by forming such an electronic component, mechanical stress and thermal stress applied between the semiconductor element 10 and the circuit board 30 are more effective by the protruding terminals 22 of the carbon nanotube bundle in which the spring property is maintained. Can be absorbed. Further, since the end of the protruding terminal 20 and the end of the protruding terminal 34 are engaged with each other, positional displacement between the protruding terminal 20 and the protruding terminal 34 can be prevented and connection resistance can be reduced. it can. Thereby, a good contact connection between the semiconductor element 10 and the circuit board 30 can be maintained, and the operation of the semiconductor element 10 can be ensured for a long period of time.

次に、本実施形態による電子部品の製造方法について図4乃至図6を用いて説明する。   Next, the method for manufacturing the electronic component according to the present embodiment will be described with reference to FIGS.

半導体素子10は、特に限定されるものではないが、例えば図4(a)に示すように、基板12と、その最上層に形成されたパッド電極14と、基板12及びパッド電極14の上に形成されたパッシベーション膜16とを有している。基板12には、多数のトランジスタその他の素子や多層配線層(図示せず)が形成されている。パッシベーション膜16には、パッド電極14を露出する開口部が形成されている。   The semiconductor element 10 is not particularly limited. For example, as shown in FIG. 4A, the semiconductor element 10 is formed on a substrate 12, a pad electrode 14 formed on the uppermost layer, and the substrate 12 and the pad electrode 14. And the formed passivation film 16. A large number of transistors and other elements and a multilayer wiring layer (not shown) are formed on the substrate 12. In the passivation film 16, an opening for exposing the pad electrode 14 is formed.

この半導体素子10のパッド電極14上に、はんだ或いは導電性微粒子を含む接着剤の接続層18を形成する(図4(b))。   A connection layer 18 of an adhesive containing solder or conductive fine particles is formed on the pad electrode 14 of the semiconductor element 10 (FIG. 4B).

次いで、半導体素子10とは別の基板、例えばシリコン基板(図示せず)上に、例えばスパッタ法により、例えば膜厚5nmのAl(アルミニウム)膜と、例えば膜厚2nmのFe(鉄)膜とを形成し、触媒金属膜を形成する。触媒金属としては、Fe以外の他の材料を用いてもよい。例えば、Ni(ニッケル)、Co(コバルト)等の遷移金属を含んだ触媒を用いてもよい。また、これらの触媒は、薄膜状にしてもよいし、微粒子状にしてもよい。また、ゼオライト等の担持材料中に触媒を含ませてもよいし、触媒となる金属元素を含んだフェリチン等のタンパク質の自己組織的配列を活用してもよい。   Next, an Al (aluminum) film having a thickness of, for example, 5 nm and an Fe (iron) film having a thickness of, for example, 2 nm are formed on a substrate different from the semiconductor element 10, for example, a silicon substrate (not shown) by, for example, sputtering. To form a catalytic metal film. As the catalyst metal, other materials than Fe may be used. For example, a catalyst containing a transition metal such as Ni (nickel) or Co (cobalt) may be used. These catalysts may be in the form of a thin film or fine particles. Further, a catalyst may be contained in a support material such as zeolite, or a self-organized arrangement of proteins such as ferritin containing a metal element serving as a catalyst may be utilized.

次いで、この触媒金属膜を触媒として、例えばCVD法により、カーボンナノチューブを成長する。カーボンナノチューブの成長は、例えば、原料ガスとしてアセチレン、メタン等の炭化水素系ガス、エタノール、メタノール等のアルコール系原料を、キャリアガスとしてアルゴンガスや水素ガスを用い、例えば100Paの圧力において、300〜700℃、例えば600℃の成長温度で成長することができる。カーボンナノチューブの長さは、成長時間によって任意に制御することができる。   Next, using this catalytic metal film as a catalyst, carbon nanotubes are grown by, for example, CVD. The growth of the carbon nanotubes is performed using, for example, a hydrocarbon gas such as acetylene or methane as a source gas, an alcohol source material such as ethanol or methanol, and an argon gas or hydrogen gas as a carrier gas. It can be grown at a growth temperature of 700 ° C., for example 600 ° C. The length of the carbon nanotube can be arbitrarily controlled by the growth time.

次いで、シリコン基板上に成長したカーボンナノチューブを、接続層18を形成した半導体素子10のパッド電極14上に押し当て、前記はんだ或いは接着剤によってパッド電極14上に固定する。   Next, the carbon nanotubes grown on the silicon substrate are pressed onto the pad electrode 14 of the semiconductor element 10 on which the connection layer 18 is formed, and fixed on the pad electrode 14 with the solder or the adhesive.

次いで、シリコン基板を取り外すことにより、パッド電極14上に、カーボンナノチューブの束を選択的に転写することができる。   Next, the bundle of carbon nanotubes can be selectively transferred onto the pad electrode 14 by removing the silicon substrate.

こうして、半導体素子10のパッド電極14上に、カーボンナノチューブの束の突起状端子20を形成する(図4(c))。   Thus, the protruding terminals 20 of the bundle of carbon nanotubes are formed on the pad electrode 14 of the semiconductor element 10 (FIG. 4C).

突起状端子20を形成するカーボンナノチューブの直径、平面密度、長さは、シリコン基板上に成長するカーボンナノチューブの成長条件によって制御することができる。ここでは、突起状端子20として、直径5nm〜10nm、平面密度1×1011本/cm、長さ100〜120μmのカーボンナノチューブの束を形成するものとする。ただし、突起状端子20を形成するカーボンナノチューブの束は、これに限定されるものではない。 The diameter, planar density, and length of the carbon nanotubes forming the protruding terminals 20 can be controlled by the growth conditions of the carbon nanotubes grown on the silicon substrate. Here, a bundle of carbon nanotubes having a diameter of 5 nm to 10 nm, a planar density of 1 × 10 11 pieces / cm 2 , and a length of 100 to 120 μm is formed as the protruding terminals 20. However, the bundle of carbon nanotubes forming the protruding terminals 20 is not limited to this.

次いで、このように形成した突起状端子20上に、例えばリフトオフ法により、例えば膜厚50〜100nm程度のAu(金)の被膜22を形成する(図4(d))。被膜22は、カーボンナノチューブの間隙が被膜によって完全に埋め込まれない膜厚とする。かかる観点から、被膜の膜厚は、突起状端子20を形成するカーボンナノチューブの間隔の半分程度以下の膜厚にすることが望ましい。   Next, an Au (gold) film 22 having a film thickness of, for example, about 50 to 100 nm is formed on the protruding terminals 20 thus formed by, for example, a lift-off method (FIG. 4D). The coating film 22 has a thickness such that the gap between the carbon nanotubes is not completely filled with the coating film. From this point of view, it is desirable that the film thickness is about half or less of the interval between the carbon nanotubes forming the protruding terminals 20.

例えば、1×1011本/cm程度の平面密度でカーボンナノチューブを成長した場合、カーボンナノチューブの間隔はおよそ30nm程度となる。この場合にカーボンナノチューブの間隙が被膜によって完全に埋め込まれないようにするためには、被膜の膜厚を15nm程度以下にすることが望ましい。 For example, when carbon nanotubes are grown at a plane density of about 1 × 10 11 pieces / cm 2 , the interval between the carbon nanotubes is about 30 nm. In this case, in order to prevent the gap between the carbon nanotubes from being completely filled with the coating, it is desirable that the thickness of the coating is about 15 nm or less.

なお、5×1010本/cm程度の平面密度でカーボンナノチューブを成長した場合、カーボンナノチューブの間隔はおよそ50nm程度となる。また、1×1010本/cm程度の平面密度でカーボンナノチューブを成長した場合、カーボンナノチューブの間隔はおよそ100nm程度となる。 When carbon nanotubes are grown at a plane density of about 5 × 10 10 pieces / cm 2 , the interval between the carbon nanotubes is about 50 nm. When carbon nanotubes are grown at a plane density of about 1 × 10 10 pieces / cm 2 , the interval between the carbon nanotubes is about 100 nm.

突起状端子20上に形成した被膜22は、例えば図2に示すように、カーボンナノチューブ20aの上端部分を覆うように形成される。図2では、それぞれのカーボンナノチューブ20aの端部を覆うように被膜22が形成されている場合を示しているが、複数本のカーボンナノチューブ20aの端部を束ねるように被膜22が形成されていてもよい。   For example, as shown in FIG. 2, the coating 22 formed on the protruding terminals 20 is formed so as to cover the upper end portion of the carbon nanotube 20 a. FIG. 2 shows the case where the coating 22 is formed so as to cover the ends of the respective carbon nanotubes 20a. However, the coating 22 is formed so as to bundle the ends of the plurality of carbon nanotubes 20a. Also good.

被膜22は、導電性を有する材料であれば特に限定されるものではないが、例えば、金属や合金等を適用することができる。被膜22の構成材料としては、例えば、金(Au)、銅(Cu)、ニッケル(Ni)、銀(Ag)等を用いることができる。また、被膜22は、単層構造である必要はなく、例えばチタン(Ti)と金(Au)との積層構造など、2層或いは3層以上の積層構造であってもよい。   The coating 22 is not particularly limited as long as it is a conductive material, and for example, a metal, an alloy, or the like can be applied. As a constituent material of the film 22, for example, gold (Au), copper (Cu), nickel (Ni), silver (Ag), or the like can be used. Further, the coating film 22 does not have to have a single layer structure, and may have a laminated structure of two layers or three or more layers such as a laminated structure of titanium (Ti) and gold (Au).

一方、半導体素子10を搭載する回路基板30には、半導体素子10の突起状端子22を接続するための接続電極32が形成されている(図5(a))。   On the other hand, on the circuit board 30 on which the semiconductor element 10 is mounted, connection electrodes 32 for connecting the protruding terminals 22 of the semiconductor element 10 are formed (FIG. 5A).

この回路基板30の接続端子32上に、突起状端子20の形成方法と同様にして、カーボンナノチューブの束の突起状端子34を形成する(図5(b))。ここでは、突起状端子34として、直径5nm〜10nm、平面密度5×1010本/cm、長さ50〜70μmのカーボンナノチューブの束を形成するものとする。ただし、突起状端子34を形成するカーボンナノチューブの束は、これに限定されるものではない。 On the connection terminal 32 of the circuit board 30, a protruding terminal 34 of a bundle of carbon nanotubes is formed in the same manner as the method of forming the protruding terminal 20 (FIG. 5B). Here, a bundle of carbon nanotubes having a diameter of 5 nm to 10 nm, a plane density of 5 × 10 10 pieces / cm 2 , and a length of 50 to 70 μm is formed as the protruding terminals 34. However, the bundle of carbon nanotubes forming the protruding terminals 34 is not limited to this.

次いで、突起状端子34上に、被膜22の形成方法と同様にして、例えば膜厚50〜100nm程度のAu(金)の被膜36を形成する(図5(c))。被膜36は、カーボンナノチューブの間隙が被膜によって完全に埋め込まれない膜厚とする。かかる観点から、被膜36の膜厚は、突起状端子34を形成するカーボンナノチューブの間隔の半分程度以下の膜厚にすることが望ましい。   Next, an Au (gold) film 36 having a film thickness of, for example, about 50 to 100 nm is formed on the protruding terminals 34 in the same manner as the method for forming the film 22 (FIG. 5C). The coating 36 has a thickness that does not completely fill the gap between the carbon nanotubes with the coating. From this point of view, it is desirable that the film 36 has a film thickness that is about half or less of the interval between the carbon nanotubes that form the protruding terminals 34.

なお、半導体素子10と回路基板30との間の接続抵抗は、カーボンナノチューブ20aの径、平面密度、被膜22の膜厚と、カーボンナノチューブ34aの径、平面密度、被膜36の膜厚との関係によって変化する(後述の実施例を参照)。カーボンナノチューブ20aの径、平面密度及び被膜22の膜厚、並びに、カーボンナノチューブ34aの径、平面密度及び被膜36の膜厚は、半導体素子10と回路基板30との間の接続に必要とされる接続抵抗に応じて適宜設定することが望ましい。   The connection resistance between the semiconductor element 10 and the circuit board 30 is the relationship between the diameter and planar density of the carbon nanotubes 20a and the film thickness of the coating film 22 and the diameter and planar density of the carbon nanotubes 34a and the film thickness of the coating film 36. (Refer to the examples described later). The diameter, planar density, and film thickness of the coating 22 of the carbon nanotubes 20a, and the diameter, planar density, and coating film 36 of the carbon nanotubes 34a are required for the connection between the semiconductor element 10 and the circuit board 30. It is desirable to set appropriately according to the connection resistance.

次いで、回路基板30上に、半導体素子10を実装する際に回路基板30に固定するための枠体38を形成する(図5(d))。   Next, a frame 38 for fixing the semiconductor element 10 to the circuit board 30 when mounting the semiconductor element 10 is formed on the circuit board 30 (FIG. 5D).

次いで、回路基板30上に、突起状端子20を形成した半導体素子10を、半導体素子10の突起状端子20と回路基板30の突起状端子34とが向き合うように位置合わせし、例えば0.6MPaの圧力で半導体素子10を回路基板30に押し付ける(図6(a)〜図6(b))。   Next, the semiconductor element 10 on which the protruding terminals 20 are formed on the circuit board 30 is aligned so that the protruding terminals 20 of the semiconductor element 10 and the protruding terminals 34 of the circuit board 30 face each other, for example, 0.6 MPa. The semiconductor element 10 is pressed against the circuit board 30 with the pressure (FIG. 6A to FIG. 6B).

これにより、突起状端子20のカーボンナノチューブ20aと突起状端子34のカーボンナノチューブ34aとが互いに噛み合い、突起状端子20と突起状端子34とが電気的に接続される。   As a result, the carbon nanotubes 20a of the protruding terminals 20 and the carbon nanotubes 34a of the protruding terminals 34 mesh with each other, and the protruding terminals 20 and the protruding terminals 34 are electrically connected.

この際、突起状端子20のカーボンナノチューブ20aの端部には被膜22が、突起状端子34のカーボンナノチューブ34aの端部には被膜36が形成されているため、突起状端子20と突起状端子34との間の接触面積を増加することができる(図3参照)。これにより、被膜22,36を形成しない場合と比較して、突起状端子20と突起状端子34との間の接触抵抗を低減することができる。   At this time, since the coating 22 is formed on the end of the carbon nanotube 20a of the protruding terminal 20 and the coating 36 is formed on the end of the carbon nanotube 34a of the protruding terminal 34, the protruding terminal 20 and the protruding terminal are formed. It is possible to increase the area of contact with 34 (see FIG. 3). Thereby, compared with the case where the coating films 22 and 36 are not formed, the contact resistance between the protruding terminal 20 and the protruding terminal 34 can be reduced.

また、カーボンナノチューブは、弾力性を有する素材のため、半導体素子10を回路基板30に押し付ける際や、半導体素子10と回路基板30との間に熱応力が加わった際に、これらの間に加わる応力を緩和して接点接続を維持する効果を有している。また、突起状端子20のカーボンナノチューブ20aと突起状端子34のカーボンナノチューブ34aとが噛み合うことには、半導体素子10を搭載した後の位置ずれを防止する効果もある。   Further, since the carbon nanotube is a material having elasticity, it is added between the semiconductor element 10 and the circuit board 30 when the semiconductor element 10 is pressed against the circuit board 30 or when thermal stress is applied between the semiconductor element 10 and the circuit board 30. It has the effect of relieving stress and maintaining contact connection. Further, the engagement of the carbon nanotubes 20a of the projecting terminals 20 and the carbon nanotubes 34a of the projecting terminals 34 has an effect of preventing a positional shift after the semiconductor element 10 is mounted.

次いで、半導体素子10を回路基板30に押し付けて突起状端子20,34のカーボンナノチューブ20a,34aに付勢力を与えた状態で、半導体素子10の外周部に例えばエポキシ系樹脂やシアネートエステル系樹脂などの接着剤40を塗布し、枠体38に接着する。これにより、半導体素子10を、回路基板30上に固定する(図6(c))。   Next, in a state where the semiconductor element 10 is pressed against the circuit board 30 to apply a biasing force to the carbon nanotubes 20a and 34a of the protruding terminals 20 and 34, for example, an epoxy resin or a cyanate ester resin is provided on the outer peripheral portion of the semiconductor element 10. The adhesive 40 is applied and adhered to the frame 38. Thereby, the semiconductor element 10 is fixed on the circuit board 30 (FIG. 6C).

こうして、本実施形態による電子部品を完成する。   Thus, the electronic component according to the present embodiment is completed.

このように、本実施形態によれば、先端部に被膜が形成されたカーボンナノチューブの束の突起状端子を突き合わせて接触接合するので、カーボンナノチューブの内面及び表面を電流経路として利用することができる。これにより、カーボンナノチューブだけの突起状端子の場合と比較して、1桁程度低い低抵抗の接合体を実現することができる。また、カーボンナノチューブの束の突起状端子は、低荷重の押し込みによって噛み合わせることができるので、カーボンナノチューブが過度に撓んで隣接端子とショートすることを防止することができる。また、突起状端子が噛み合った状態が保持されるため、接触接合後に位置ずれが生じることを防止することができる。   As described above, according to the present embodiment, the protruding terminals of the bundle of carbon nanotubes having a coating formed at the tip are abutted and contact-bonded, so that the inner surface and the surface of the carbon nanotube can be used as a current path. . As a result, it is possible to realize a low-resistance bonded body that is about an order of magnitude lower than that in the case of a protruding terminal made of only carbon nanotubes. Further, since the protruding terminals of the bundle of carbon nanotubes can be engaged with each other by pressing with a low load, it is possible to prevent the carbon nanotubes from being excessively bent and short-circuited with the adjacent terminals. Moreover, since the state in which the protruding terminals are engaged with each other is maintained, it is possible to prevent the positional deviation from occurring after the contact bonding.

[変形実施形態]
上記実施形態に限らず種々の変形が可能である。
[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

例えば、上記実施形態では、突起状端子20と突起状端子34とが噛み合わされた状態として、被膜22と被膜36とが直に接している場合を示しているが(図3参照)、被膜22と被膜36とは必ずしも接している必要はない。例えば、突起状端子20と突起状端子34とがより深く噛み合い、被膜22と被膜36とが直接接触していないような場合にも、接続抵抗を低減する効果がある。   For example, in the above-described embodiment, the case where the coating 22 and the coating 36 are in direct contact with each other is shown in a state where the protruding terminals 20 and the protruding terminals 34 are engaged with each other (see FIG. 3). And the coating 36 are not necessarily in contact with each other. For example, even when the protruding terminals 20 and the protruding terminals 34 are deeply engaged with each other and the coating 22 and the coating 36 are not in direct contact with each other, there is an effect of reducing the connection resistance.

また、上記実施形態では、半導体素子10を回路基板30上に固定する構造体として接着剤40を用いたが、半導体素子10は必ずしも接着剤40のようなサイドフィルによって固定する必要はない。例えば、半導体素子10の裏面側にヒートスプレッダその他の封止構造体を設け、この封止構造体によって回路基板30上に固定するようにしてもよい。   In the above embodiment, the adhesive 40 is used as a structure for fixing the semiconductor element 10 on the circuit board 30. However, the semiconductor element 10 is not necessarily fixed by a side fill such as the adhesive 40. For example, a heat spreader or other sealing structure may be provided on the back side of the semiconductor element 10 and fixed on the circuit board 30 by this sealing structure.

また、上記実施形態では、突起状端子20,34をカーボンナノチューブにより形成したが、突起状端子20,34は、これに限定されるものではない。カーボンナノチューブと同様の弾力性を有する導電性部材としては、例えば、カーボンナノチューブ以外の他の炭素元素の線状構造体が挙げられる。炭素元素の線状構造体としては、カーボンナノチューブのほか、カーボンナノワイヤ、カーボンロッド、カーボンファイバが挙げられる。これら線状構造体は、サイズが異なるほかは、カーボンナノチューブと同様である。   Moreover, in the said embodiment, although the protruding terminals 20 and 34 were formed with the carbon nanotube, the protruding terminals 20 and 34 are not limited to this. Examples of the conductive member having elasticity similar to that of carbon nanotubes include linear structures of carbon elements other than carbon nanotubes. Examples of the carbon element linear structure include carbon nanowires, carbon rods, and carbon fibers in addition to carbon nanotubes. These linear structures are the same as the carbon nanotubes except that their sizes are different.

また、上記実施形態では、半導体素子と回路基板との間の電気的接続への適用例を示したが、半導体素子と回路基板との接続のみならず、2つの基板を電気的に接続する際に広く適用することができる。   Moreover, in the said embodiment, although the application example to the electrical connection between a semiconductor element and a circuit board was shown, when connecting not only the connection of a semiconductor element and a circuit board but two boards | substrates Can be widely applied to.

上記一実施形態による電子部品の製造方法を用い、以下の条件により電子部品を製造した。   Using the electronic component manufacturing method according to the above-described embodiment, an electronic component was manufactured under the following conditions.

[実施例1]
半導体素子10のパッド電極14上に、直径80μm、平面密度1×1010本/cm、長さ120μmのカーボンナノチューブの束の突起状端子20を形成した。また、この突起状端子20上には、膜厚70nmのAuの被膜22を形成した。
[Example 1]
On the pad electrode 14 of the semiconductor element 10, a protruding terminal 20 of a bundle of carbon nanotubes having a diameter of 80 μm, a planar density of 1 × 10 10 pieces / cm 2 , and a length of 120 μm was formed. Further, an Au coating 22 having a film thickness of 70 nm was formed on the protruding terminals 20.

回路基板30の接続電極32上には、直径120μm、平面密度1×1011本/cm、長さ50μmのカーボンナノチューブの束の突起状端子34を形成した。また、この突起状端子34上には、膜厚70nmのAuの被膜36を形成した。 On the connection electrode 32 of the circuit board 30, a protruding terminal 34 of a bundle of carbon nanotubes having a diameter of 120 μm, a planar density of 1 × 10 11 pieces / cm 2 , and a length of 50 μm was formed. An Au coating 36 having a film thickness of 70 nm was formed on the protruding terminals 34.

次いで、半導体素子10を、回路基板30上に位置合わせし、0.6MPaの荷重により突き当て接合を行った。   Next, the semiconductor element 10 was aligned on the circuit board 30 and butt-joined with a load of 0.6 MPa.

次いで、半導体素子10および回路基板30を固定するようにエポキシ樹脂のサイドフィル材を塗布し、150℃、30分間の加熱処理を行い、半導体素子10を回路基板30上に固定した。   Next, a side fill material of epoxy resin was applied so as to fix the semiconductor element 10 and the circuit board 30, and heat treatment was performed at 150 ° C. for 30 minutes to fix the semiconductor element 10 on the circuit board 30.

[実施例2]
半導体素子10上に形成する突起状端子20のカーボンナノチューブの平面密度を5×1010本/cmとしたほかは、実施例1と同様の条件で電子部品を製造した。
[Example 2]
An electronic component was manufactured under the same conditions as in Example 1 except that the planar density of the carbon nanotubes of the protruding terminals 20 formed on the semiconductor element 10 was 5 × 10 10 pieces / cm 2 .

[実施例3]
半導体素子10上に形成する突起状端子20のカーボンナノチューブの平面密度を1×1011本/cmとしたほかは、実施例1と同様の条件で電子部品を製造した。
[Example 3]
An electronic component was manufactured under the same conditions as in Example 1 except that the planar density of the carbon nanotubes of the protruding terminals 20 formed on the semiconductor element 10 was 1 × 10 11 pieces / cm 2 .

[比較例]
比較のため、回路基板30上に突起状端子34を形成せずに半導体素子10を搭載した電子部品も作製した。半導体素子10上に形成する突起状端子20のカーボンナノチューブの平面密度を5×1010本/cmとしたこと、突起状端子34を形成しないことのほかは、実施例1と同様の条件で電子部品を製造した。
[Comparative example]
For comparison, an electronic component on which the semiconductor element 10 was mounted without forming the protruding terminals 34 on the circuit board 30 was also produced. The planar density of the carbon nanotubes of the protruding terminals 20 formed on the semiconductor element 10 was set to 5 × 10 10 pieces / cm 2 and the protruding terminals 34 were not formed under the same conditions as in Example 1. Electronic components were manufactured.

このようにして作製した4種類の電子部品について、半導体素子と回路基板との間の電気的接続が問題ないことを確認した。半導体素子と回路基板との間の抵抗値は、比較例の電子部品が10.5Ωであるのに対し、実施例1〜3の電子部品は、それぞれ0.75Ω、0.5Ω、8.5Ωであった。実施例3の電子部品で接続抵抗が高めではあるが、何れも比較例の電子部品よりも低抵抗であった。実施例3の電子部品で接続抵抗が高かった理由は明らかではないが、突起状端子20,34のいずれのカーボンナノチューブも高密度のため、噛み合わせが十分でなかったことが考えられる。   It was confirmed that there was no problem in the electrical connection between the semiconductor element and the circuit board for the four types of electronic components thus produced. The resistance value between the semiconductor element and the circuit board is 10.5Ω for the electronic component of the comparative example, whereas the electronic components of Examples 1 to 3 are 0.75Ω, 0.5Ω, and 8.5Ω, respectively. Met. Although the connection resistance was higher in the electronic component of Example 3, all of them were lower in resistance than the electronic component of the comparative example. The reason why the connection resistance is high in the electronic component of Example 3 is not clear, but it is considered that the carbon nanotubes of the protruding terminals 20 and 34 were not dense enough to be engaged because of high density.

実施例1〜3の電子部品について、−25〜125℃の繰り返し温度サイクル試験を500サイクル行った結果、抵抗上昇は10%以下と良好であった。また、121℃/85%の環境下に1000時間放置後においても、サイクル試験と同様に抵抗上昇は10%以下と良好であった。   As a result of performing 500 cycles of the repeated temperature cycle test at −25 to 125 ° C. for the electronic components of Examples 1 to 3, the resistance increase was as good as 10% or less. Further, even after being left in an environment of 121 ° C./85% for 1000 hours, the resistance increase was as good as 10% or less as in the cycle test.

10…半導体素子
12…基板
14…パッド電極
16…パッシベーション膜
18…接続層
20,34…突起状端子
20a,34a…カーボンナノチューブ
22,36…被膜
30…回路基板
32…接続電極
38…枠体
40…接着剤
DESCRIPTION OF SYMBOLS 10 ... Semiconductor element 12 ... Board | substrate 14 ... Pad electrode 16 ... Passivation film 18 ... Connection layer 20, 34 ... Projection terminal 20a, 34a ... Carbon nanotube 22, 36 ... Film 30 ... Circuit board 32 ... Connection electrode 38 ... Frame 40 …adhesive

Claims (5)

第1の基板と、
前記第1の基板上に形成され、突起状端子を介して前記第1の基板に電気的に接続された第2の基板とを有し、
前記突起状端子は、前記第2の基板に接合され、前記第1の基板側の端部に選択的に形成された導電性の被膜を有する炭素元素の第1の線状構造体の束と、前記第1の基板に接合され、前記第2の基板側の端部に選択的に形成された導電性の被膜を有する炭素元素の第2の線状構造体の束とを含み、
前記第1の線状構造体の束と前記第2の線状構造体の束とが互いに噛み合うことにより、前記第1の基板と前記第2の基板とが電気的に接続されている
ことを特徴とする電子部品。
A first substrate;
A second substrate formed on the first substrate and electrically connected to the first substrate via a protruding terminal;
The protruding terminal is bonded to the second substrate, and a bundle of first linear structures of carbon elements having a conductive film selectively formed at an end portion on the first substrate side, and A bundle of carbon element second linear structures having a conductive coating bonded to the first substrate and selectively formed at an end portion on the second substrate side,
The first substrate and the second substrate are electrically connected to each other when the bundle of the first linear structures and the bundle of the second linear structures are engaged with each other. Features electronic components.
請求項1記載の電子部品において、
前記第2の基板を前記第1の基板に固定する構造体を更に有する
ことを特徴とする電子部品。
The electronic component according to claim 1 Symbol placement,
The electronic component further comprising: a structure for fixing the second substrate to the first substrate.
請求項1又は2記載の電子部品において、
前記第1の基板は、回路基板であり、
前記第2の基板は、半導体素子である
ことを特徴とする電子部品。
The electronic component according to claim 1 or 2 ,
The first substrate is a circuit board;
The electronic component, wherein the second substrate is a semiconductor element.
第1の基板上に、炭素元素の線状構造体の束の第1の突起状端子を形成する工程と、
前記第1の突起状端子の先端部に、導電性の第1の被膜を選択的に形成する工程と、
第2の基板上に、炭素元素の線状構造体の束の第2の突起状端子を形成する工程と、
前記第2の突起状端子の先端部に、導電性の第2の被膜を選択的に形成する工程と、
前記第2の基板を前記第1の基板上に搭載し、前記第1の突起状端子と前記第2の突起状端子とを噛み合わせることにより、前記第1の基板と前記第2の基板とを電気的に接続する工程と
を有することを特徴とする電子部品の製造方法。
Forming a first protruding terminal of a bundle of linear structures of carbon elements on a first substrate;
Selectively forming a conductive first film on the tip of the first protruding terminal;
Forming a second protruding terminal of a bundle of carbon element linear structures on a second substrate;
Selectively forming a conductive second coating on the tip of the second protruding terminal;
By mounting the second substrate on the first substrate and engaging the first protruding terminal and the second protruding terminal, the first substrate and the second substrate And a step of electrically connecting the electronic component and the electronic component manufacturing method.
請求項記載の電子部品の製造方法において、
前記第1の基板と前記第2の基板とを電気的に接続する工程の後、前記第2の基板を前記第1の基板に固定する工程を更に有する
ことを特徴とする電子部品の製造方法。
In the manufacturing method of the electronic component of Claim 4 ,
The method of manufacturing an electronic component, further comprising a step of fixing the second substrate to the first substrate after the step of electrically connecting the first substrate and the second substrate. .
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