JP2000114434A - Structure for mounting semiconductor chip or semiconductor device on substrate - Google Patents

Structure for mounting semiconductor chip or semiconductor device on substrate

Info

Publication number
JP2000114434A
JP2000114434A JP10275734A JP27573498A JP2000114434A JP 2000114434 A JP2000114434 A JP 2000114434A JP 10275734 A JP10275734 A JP 10275734A JP 27573498 A JP27573498 A JP 27573498A JP 2000114434 A JP2000114434 A JP 2000114434A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
mounting
pillars
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10275734A
Other languages
Japanese (ja)
Inventor
Fumio Miyagawa
文雄 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP10275734A priority Critical patent/JP2000114434A/en
Publication of JP2000114434A publication Critical patent/JP2000114434A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Connecting Device With Holders (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

PROBLEM TO BE SOLVED: To dismount a semiconductor chip from a substrate easily. SOLUTION: In a structure for mounting a semiconductor chip 10 or a semiconductor device on a substrate 16 in which a plurality of electrode pads 12 formed on the surface of the semiconductor chip 10 and a plurality of lands 18 formed on the surface of the substrate 16 are electrically connected together to mount, a plurality of conductive columnar bodies 20 and 22 are erected at a right angle at intervals on each surface of the electrode pads 12 and the lands 18, respectively. The semiconductor chip 10 is mounted so that a plurality of columnar bodies 20 formed on the electrode pads 12 are inserted among a plurality of columnar bodies 22 formed on the lands 18 in a position corresponding to the electrode pad 12, and further that both of columnar bodies 20 and 22 are fitted with each other under the condition where outer peripheral surfaces of the columnar bodies are brought into contact with each other.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップ若し
くは半導体装置の実装基板への実装構造に関する。
The present invention relates to a structure for mounting a semiconductor chip or a semiconductor device on a mounting board.

【0002】[0002]

【従来の技術】従来の半導体チップ若しくは半導体装置
の実装基板への実装構造の概要について図7を用いて説
明する。まず、半導体チップ若しくは半導体装置(以
下、被実装体とも言う)10の表面に2次元エリア状に
形成された複数の電極パッド12へはんだボール等を装
着してバンプ14を形成する。そして、被実装体10の
各バンプ14が、実装基板16の表面に同じく2次元エ
リア状に同じ位置になるように形成された複数のランド
18の各々と接触するように被実装体10を位置決めし
ながら実装基板16上に載せる。最後に全体に加熱して
バンプ14を溶かす。これによって、被実装体10の各
電極パッド12と実装基板16の各ランド18とがはん
だ等のバンプ形成素材によって電気的に接続された状態
で、被実装体10が実装基板16に実装される。
2. Description of the Related Art An outline of a conventional mounting structure of a semiconductor chip or a semiconductor device on a mounting substrate will be described with reference to FIG. First, a bump 14 is formed by mounting a solder ball or the like on a plurality of electrode pads 12 formed in a two-dimensional area on the surface of a semiconductor chip or a semiconductor device (hereinafter also referred to as a mounted body) 10. Then, the mounted body 10 is positioned so that each bump 14 of the mounted body 10 comes into contact with each of a plurality of lands 18 formed on the surface of the mounting board 16 in the same position in the same two-dimensional area. While mounting on the mounting board 16. Finally, the entire structure is heated to melt the bumps 14. As a result, the mounted body 10 is mounted on the mounting board 16 in a state where the electrode pads 12 of the mounted body 10 and the lands 18 of the mounting board 16 are electrically connected by the bump forming material such as solder. .

【0003】[0003]

【発明が解決しようとする課題】半導体チップや半導体
装置の電気的試験はこれら単独でも行われ、良品と判断
されたものが、実装基板へ実装されるのであるが、さら
に実装基板へ実装された状態においても、さらに詳細な
機能についての電気的試験が行われ、最終的にOKと判
断されたものが良品として出荷される。そして、半導体
チップや半導体装置は単品で良品と判断された後も、実
装基板へ実装されて始めて試験される項目に関して不良
と判断される場合があったり、また上述したように電極
パッドやランドは2次元エリア状に配置されているか
ら、全電極パッドとランドとの相互の接続状態は目視で
は判断が困難であり、実装後の試験において接続不良が
始めて判明することもある。
An electrical test of a semiconductor chip or a semiconductor device is also performed alone, and a product judged to be non-defective is mounted on a mounting board. Even in this state, a more detailed electrical test is performed on the functions, and those finally determined to be OK are shipped as non-defective products. And, even after a semiconductor chip or a semiconductor device is determined to be a single good product, it may be determined that the item to be tested only after being mounted on a mounting board is defective. Since they are arranged in a two-dimensional area, the mutual connection state between all the electrode pads and the lands is difficult to determine visually, and a connection failure may become apparent for the first time in a test after mounting.

【0004】このような場合には、一旦実装した半導体
チップや半導体装置を実装基板から取り外して、良品の
半導体チップや半導体装置と交換等して再度実装基板へ
取り付ける作業を行わなければならない。しかしなが
ら、従来のバンプを用いた半導体チップ若しくは半導体
装置の実装基板への実装構造では、2次元エリア状に広
がる全電極パッドと全ランドを接続しているバンプ形成
素材(はんだ等)を同時に溶かさなければ、実装基板か
ら半導体チップ若しくは半導体装置を取り外すことがで
きず、取り外し作業が非常に大変であるという課題があ
る。
In such a case, it is necessary to remove the semiconductor chip or the semiconductor device once mounted from the mounting board, replace the semiconductor chip or the semiconductor device with a good semiconductor chip or the like, and mount it again on the mounting board. However, in a conventional mounting structure of a semiconductor chip or a semiconductor device on a mounting substrate using bumps, a bump forming material (solder or the like) connecting all the electrode pads and all the lands spread in a two-dimensional area must be melted at the same time. For example, there is a problem that the semiconductor chip or the semiconductor device cannot be removed from the mounting substrate, and the removal operation is very difficult.

【0005】従って、本発明は上記課題を解決すべくな
され、その目的とするところは、実装基板からの半導体
チップ若しくは半導体装置の取り外しが簡単に行える半
導体チップ若しくは半導体装置の実装基板への実装構造
を提供することにある。
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to solve the above-mentioned problems, and an object of the present invention is to provide a structure for mounting a semiconductor chip or a semiconductor device on a mounting substrate in which the semiconductor chip or the semiconductor device can be easily removed from the mounting substrate. Is to provide.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するた
め、本発明のうち請求項1記載の発明は、半導体チップ
若しくは半導体装置の表面に形成された複数の電極パッ
ドと実装基板の表面に形成された複数のランドとを電気
的に接続して実装する、半導体チップ若しくは半導体装
置の実装基板への実装構造において、前記電極パッドお
よび前記ランドの各表面には、導電性の柱状体が間隔を
あけて複数本直角に立設され、前記半導体チップ若しく
は前記半導体装置は、前記電極パッドに形成された複数
の柱状体が、該電極パッドに対応する位置の前記ランド
に形成された複数の柱状体間に差し込まれると共に、双
方の柱状体の外周面同士が相互に接触した状態で嵌まり
込んで実装されていることを特徴とする。
In order to solve the above-mentioned problems, according to the present invention, a plurality of electrode pads formed on a surface of a semiconductor chip or a semiconductor device and a plurality of electrode pads formed on a surface of a mounting substrate are provided. In a mounting structure of a semiconductor chip or a semiconductor device mounted on a mounting board, a conductive columnar body is provided on each surface of the electrode pads and the lands at intervals. The semiconductor chip or the semiconductor device is provided with a plurality of pillars formed on the land at positions corresponding to the electrode pads. It is characterized in that it is inserted in between, and fitted and mounted in a state where the outer peripheral surfaces of both columnar bodies are in contact with each other.

【0007】これによれば、半導体チップ若しくは半導
体装置と実装基板とは、電極パッドおよびランドの各表
面に形成された柱状体同士が嵌まり合って、相互の外周
面間の摩擦力だけで接続されている。よって、半導体チ
ップ若しくは半導体装置を実装基板から取り外す場合に
は実装基板から半導体チップ若しくは半導体装置を引き
離すだけでよく、従来のように加熱処理は不要となり、
取り外しが簡単に行える。また、半導体チップ若しくは
半導体装置を実装基板へ装着する場合にも従来のように
バンプを溶かす必要がなく、工程が簡略化できる。
According to this, the semiconductor chip or the semiconductor device and the mounting board are connected only by the frictional force between the outer peripheral surfaces of the electrode pads and the columns formed on the respective surfaces of the lands. Have been. Therefore, when the semiconductor chip or the semiconductor device is detached from the mounting substrate, it is only necessary to separate the semiconductor chip or the semiconductor device from the mounting substrate, and the heat treatment as in the related art is unnecessary,
Easy removal. Also, even when a semiconductor chip or a semiconductor device is mounted on a mounting substrate, it is not necessary to melt the bumps as in the related art, and the process can be simplified.

【0008】また、本発明のうち請求項2記載の発明
は、半導体チップ若しくは半導体装置の表面に形成され
た複数の電極パッドと実装基板の表面に形成された複数
のランドとを電気的に接続して実装する、半導体チップ
若しくは半導体装置の実装基板への実装構造において、
前記電極パッドの各表面には、導電性の柱状体が間隔を
あけて複数本直角に立設され、前記実装基板の複数のラ
ンドの形成領域上には、厚み方向に沿って厚さと同じ長
さの無数の導電性の柱状体が両端を露出させ、外周面同
士が相互に接触しない状態で非導電性ゴム材中に埋設さ
れて成る異方性導電シートが固着され、前記半導体チッ
プ若しくは前記半導体装置は、前記異方性導電シートを
介して前記実装基板へ押しつけられて、前記電極パッド
に形成された複数の柱状体が前記異方性導電シートに突
き刺されると共に、該電極パッドに対応する位置の前記
ランドの領域にある異方性導電シート中の複数の柱状体
間に双方の柱状体の外周面同士が相互に接触した状態で
嵌まり込んで実装されていることを特徴とする。
According to a second aspect of the present invention, a plurality of electrode pads formed on a surface of a semiconductor chip or a semiconductor device are electrically connected to a plurality of lands formed on a surface of a mounting substrate. In the mounting structure of the semiconductor chip or semiconductor device on the mounting board,
On each surface of the electrode pad, a plurality of conductive pillars are erected at right angles with an interval therebetween, and on a formation region of a plurality of lands of the mounting substrate, the same length as the thickness along the thickness direction. The anisotropic conductive sheet embedded in a non-conductive rubber material in a state where the myriad of conductive pillars expose both ends and the outer peripheral surfaces do not contact each other is fixed, and the semiconductor chip or the The semiconductor device is pressed against the mounting substrate via the anisotropic conductive sheet, and the plurality of columnar bodies formed on the electrode pad are pierced into the anisotropic conductive sheet and correspond to the electrode pad. It is characterized in that the outer peripheral surfaces of the two pillars are fitted and mounted between the plurality of pillars in the anisotropic conductive sheet in the land area at the position in a state where they are in contact with each other.

【0009】これによれば、半導体チップ若しくは半導
体装置と実装基板とは、半導体チップ若しくは半導体装
置が異方性導電シートを介して実装基板へ押しつけら
れ、電極パッドの表面に形成された柱状体が異方性導電
シートに突き刺されることによって、電極パッドとラン
ドとが電気的に接続される。よって、半導体チップ若し
くは半導体装置を実装基板から取り外す場合には半導体
チップ若しくは半導体装置の実装基板への押しつけを解
除して、半導体チップ若しくは半導体装置の電極パッド
に形成された柱状体を異方性導電シートから引き抜くだ
けでよい。従って、従来のように加熱処理は不要である
から、取り外しが簡単になる。また、半導体チップ若し
くは半導体装置を実装基板へ装着する場合にも従来のよ
うにバンプを溶かす必要がなく、工程が簡略化できる。
According to this, the semiconductor chip or the semiconductor device and the mounting substrate are formed by pressing the semiconductor chip or the semiconductor device against the mounting substrate via the anisotropic conductive sheet and forming the columnar body formed on the surface of the electrode pad. By piercing the anisotropic conductive sheet, the electrode pad and the land are electrically connected. Therefore, when removing the semiconductor chip or the semiconductor device from the mounting substrate, the pressing of the semiconductor chip or the semiconductor device against the mounting substrate is released, and the columnar body formed on the electrode pad of the semiconductor chip or the semiconductor device is anisotropically conductive. Just pull it out of the sheet. Therefore, the heat treatment is not required as in the related art, and the removal is simplified. Also, even when a semiconductor chip or a semiconductor device is mounted on a mounting substrate, it is not necessary to melt the bumps as in the related art, and the process can be simplified.

【0010】[0010]

【発明の実施の形態】以下、本発明に係る半導体チップ
若しくは半導体装置の実装基板への実装構造の好適な実
施の形態について添付図面と共に詳述する。なお、従来
例と同じ構成については同じ符号を付し、詳細な説明は
省略する。 (第1の実施の形態)最初に、本実施の形態の基本的な
考え方について図1〜図3を用いて説明する。その考え
方は、半導体チップ若しくは半導体装置(被実装体1
0)を実装基板16へ、被実装体10の表面に形成され
た複数の電極パッド12と実装基板16の表面に形成さ
れた複数のランド18とを電気的に接続して実装する場
合に、まず、図1に示すように電極パッド12およびラ
ンド18の各表面に、導電性の柱状体20、22を間隔
をあけて複数本直角に立設する。そして、各電極パッド
12に形成された複数の柱状体20が、電極パッド12
に対応する位置の各ランド18に形成された複数の柱状
体22間に差し込まれ、双方の柱状体20、22の外周
面同士が相互に接触した状態で嵌まり込むように図2の
ごとく実装することにある。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the mounting structure of a semiconductor chip or a semiconductor device on a mounting board according to the present invention will be described below in detail with reference to the accompanying drawings. The same components as those of the conventional example are denoted by the same reference numerals, and detailed description thereof will be omitted. (First Embodiment) First, the basic concept of the present embodiment will be described with reference to FIGS. The idea is that a semiconductor chip or a semiconductor device (mount 1
0) is mounted on the mounting board 16 by electrically connecting the plurality of electrode pads 12 formed on the surface of the mounted body 10 and the plurality of lands 18 formed on the surface of the mounting board 16 with: First, as shown in FIG. 1, a plurality of conductive pillars 20 and 22 are erected at right angles on each surface of the electrode pad 12 and the land 18 at intervals. Then, the plurality of pillars 20 formed on each electrode pad 12 are
2 is mounted between the plurality of columnar bodies 22 formed on the lands 18 at positions corresponding to the positions of FIG. 2 so that the outer peripheral surfaces of the two columnar bodies 20 and 22 are fitted in a state of being in contact with each other. Is to do.

【0011】そして、この構造で実装された被実装体1
0は、被実装体10の柱状体20と実装基板16の柱状
体22の接触する外周面間に生ずる摩擦力により、実装
基板16に振動が加わったりしても実装基板16から簡
単には抜けない。一方、従来のようにバンプ形成素材
(はんだ等)を溶かすことによって電極パッド12およ
びランド18が接続されたものではないため、接触する
全ての柱状体20と全ての柱状体22間に作用する全摩
擦力以上の力で被実装体10を実装基板16から引き離
せば、再加熱することなく被実装体10を実装基板16
から取り外すことができる。また一旦取り外した被実装
体10を同じようにして実装基板16に再度実装するこ
とも可能となるのである。
Then, the mounted body 1 mounted with this structure
No. 0 is easily detached from the mounting substrate 16 even when vibration is applied to the mounting substrate 16 due to a frictional force generated between the outer peripheral surface of the columnar body 20 of the mounted body 10 and the columnar body 22 of the mounting substrate 16 in contact with each other. Absent. On the other hand, since the electrode pads 12 and the lands 18 are not connected by melting the bump forming material (solder or the like) as in the related art, all the contacting columnar members 20 and all the columnar members 22 act between them. If the body 10 is separated from the mounting board 16 by a force higher than the frictional force, the body 10 can be mounted on the mounting board 16 without reheating.
Can be removed from. Further, the mounted body 10 once removed can be mounted on the mounting board 16 again in the same manner.

【0012】(電極パッド、ランド、各柱状体の構造)
次に、各構成要素の詳細な構成について説明する。実装
基板16に設けられる各ランド18の2次元的配置は、
各ランド18と電気的に接続される被実装体10に設け
られた各電極パッド12の2次元的配置と同じに設定さ
れている。つまり、実装基板16に対して被実装体10
を位置決めし、被実装体10を実装基板16のランド1
8が形成された領域内の所定位置に載せた場合には、相
互に重なるように配置されている。
(Structures of electrode pads, lands, and pillars)
Next, a detailed configuration of each component will be described. The two-dimensional arrangement of each land 18 provided on the mounting board 16 is as follows.
The two-dimensional arrangement of each electrode pad 12 provided on the mounted body 10 electrically connected to each land 18 is set. That is, the mounted body 10 is
And the mounted body 10 is mounted on the land 1 of the mounting board 16.
When they are placed at a predetermined position in the region where 8 is formed, they are arranged so as to overlap each other.

【0013】そして、電極パッド12およびランド18
には一例として図3に示すように、同一ピッチPで4行
×4列のマトリクス状に柱状体20、22が同じ本数だ
け垂直に突設されている。なお、マトリクスの形態は4
行×4列に限定されず、n行×m列(n、mともに2以
上の自然数)であれば良く、nやmの数値は電極パッド
12やランド18の面積や形状を考慮して設定する。ま
た、各柱状体20、22のピッチは、一方の柱状体の隙
間に、他方の柱状体が嵌まり込むことができれば良いの
であるから、必ずしも同一ピッチとする必要はなく、他
方の柱状体のピッチが一方の柱状体のピッチの整数倍と
なっていれば良い。
The electrode pad 12 and the land 18
As an example, as shown in FIG. 3, the same number of pillars 20, 22 are vertically projected in a matrix of 4 rows × 4 columns at the same pitch P. The form of the matrix is 4
The number of rows is not limited to 4 × columns, and may be n rows × m columns (both n and m are natural numbers of 2 or more). I do. Further, the pitch between the columnar bodies 20 and 22 is not necessarily required to be the same pitch because it is only necessary that the other columnar body can fit into the gap between one columnar body. It is sufficient that the pitch is an integral multiple of the pitch of one of the columnar bodies.

【0014】また、各柱状体20、22の太さも同様
に、一方の柱状体の隙間に、他方の柱状体が嵌まり込ん
で双方の外周面同士が接触できれば良いのであるから、
図3に示すごとく本実施の形態のように略同じ太さに形
成しても良いし、太さを異にしていても良い。他方の柱
状体の太さは一方の柱状体の隙間を考慮して決定すれば
良い。また、柱状体20、22の配置は図3に示すよう
なマトリクス状以外にも、千鳥状に配置するこも可能で
ある。
Similarly, the thickness of each of the pillars 20 and 22 may be the same as long as the other pillar is fitted into the gap between one pillar and the outer peripheral surfaces of both pillars can contact each other.
As shown in FIG. 3, they may be formed to have substantially the same thickness as in the present embodiment, or may have different thicknesses. The thickness of the other column may be determined in consideration of the gap between the columns. Further, the arrangement of the columnar bodies 20 and 22 can be arranged in a staggered manner in addition to the matrix as shown in FIG.

【0015】(柱状体の形成工程)この柱状体20、2
2の形成は、次の図4で示す工程で行われる。なお、被
実装体10の電極パッド12への柱状体20の形成を一
例として取り上げて説明するが、実装基板16のランド
18に柱状体22を形成する場合も同様である。第1工
程は、被実装体10の電極パッド12や他の導体パター
ン(不図示)の形成面上に、Ti/Cu 、Cr/Cu 、Cr/Ni な
どの給電層と呼ばれる金属層(不図示)をスパッタリン
グや無電解めっき等により全面に形成する。第2工程
は、図4(a)に示すようにその金属層上に液状のフォ
トレジストを数回塗布して所定の厚さのレジスト膜24
を形成する。その後このレジスト膜24をフォトリソグ
ラフィーにより処理して微細ホール26を各電極パッド
12の領域内に複数(本例では4×4=16個)形成
し、柱状体20を形成すべき金属層の部位を露出させ
る。ここで微細ホール26の孔径は、その後芯材28の
表面にNiめっき等からなる被覆層を形成して最終的な柱
状体20とすることから、被覆層の厚み分だけ柱状体2
0よりも小径にしておく。
(Step of forming columnar body)
The formation of 2 is performed in the next step shown in FIG. The formation of the pillars 20 on the electrode pads 12 of the mounted body 10 will be described as an example, but the same applies to the case where the pillars 22 are formed on the lands 18 of the mounting board 16. In the first step, a metal layer (not shown) such as a power supply layer such as Ti / Cu, Cr / Cu, or Cr / Ni is formed on the surface of the body 10 on which the electrode pads 12 and other conductive patterns (not shown) are formed. ) Is formed on the entire surface by sputtering or electroless plating. In the second step, as shown in FIG. 4A, a liquid photoresist is applied on the metal layer several times to form a resist film 24 having a predetermined thickness.
To form Thereafter, the resist film 24 is processed by photolithography to form a plurality of (in this example, 4 × 4 = 16) fine holes 26 in the region of each electrode pad 12, and a portion of the metal layer on which the columnar body 20 is to be formed. To expose. Here, the diameter of the fine holes 26 is determined by forming a coating layer made of Ni plating or the like on the surface of the core material 28 to form the final columnar body 20.
Keep the diameter smaller than 0.

【0016】そして第3工程は、電気めっき法により、
図4(b)のように金属層上にCuメッキを施して、柱状
体20の芯材28を形成する。この際、芯材28の先端
がレジスト膜24の表面から突出しないようにする。突
出した場合には芯材28の先端がレジスト膜24の表面
上で傘状に広がって外径が大きくなり、隣接する芯材2
8の先端同士が接触したり、また接触しないまでも芯材
28間の間隔が狭くなってしまうからである。ここで、
本実施の形態では最終的な柱状体20、22の長さは約
50μm〜100μm程度に形成するため、芯材28の
長さも同程度か、その後芯材28の表面にNiめっき等か
らなる被覆層を形成することを考慮して若干短めに形成
する必要がある。
In the third step, an electroplating method is used.
As shown in FIG. 4B, Cu plating is performed on the metal layer to form the core material 28 of the columnar body 20. At this time, the tip of the core 28 is prevented from protruding from the surface of the resist film 24. In the case where the core material 28 protrudes, the tip of the core material 28 expands in an umbrella shape on the surface of the resist film 24 to increase the outer diameter.
This is because the gaps between the core materials 28 become narrow even if the tips of the tips 8 contact each other or even if they do not contact each other. here,
In the present embodiment, since the final length of the columnar bodies 20 and 22 is formed to be about 50 μm to about 100 μm, the length of the core material 28 is also approximately the same, and then the surface of the core material 28 is coated with Ni plating, etc. It is necessary to form the layer slightly shorter in consideration of forming the layer.

【0017】なお、一回の第2工程と第3工程により、
芯材28の長さを約50μm〜100μm程度に形成で
きない場合には、上述した第2工程と第3工程を必要な
回数だけ繰り返し、芯材28の長さを目標とする長さに
する。図4は、第2工程と第3工程を2回繰り返す場合
を示しており、最初の第3工程の後に、再度の第2工程
として、図4(c)に示すように、芯材28が微細ホー
ル26内に形成されたレジスト膜24上に、液状フォト
レジストを数回塗布して所定の厚さの第2レジスト膜3
0を積層する。この第2レジスト膜30をフォトリソグ
ラフィーにより処理して微細ホール26上に、微細ホー
ル26と連通する微細ホール26と同径の第2微細ホー
ル32を形成し、芯材28の上部を露出させる。次に、
再度の第3工程として、図4(d)に示すように電気め
っき法により、露出している芯材28の上部に、さらに
Cuメッキを施して、芯材28の全長を長くする。
Note that the second and third steps are performed once.
When the length of the core material 28 cannot be formed to about 50 μm to 100 μm, the above-described second and third steps are repeated as many times as necessary to make the length of the core material 28 a target length. FIG. 4 shows a case where the second step and the third step are repeated twice, and after the first third step, as a second step again, as shown in FIG. A liquid photoresist is applied several times on the resist film 24 formed in the fine holes 26 to form a second resist film 3 having a predetermined thickness.
0 is laminated. The second resist film 30 is processed by photolithography to form a second fine hole 32 having the same diameter as the fine hole 26 communicating with the fine hole 26 on the fine hole 26, thereby exposing the upper portion of the core 28. next,
As a third step again, as shown in FIG. 4D, the upper portion of the exposed core material 28 is further plated by electroplating.
The whole length of the core material 28 is lengthened by performing Cu plating.

【0018】この1回若しくは数回の第2工程と第3工
程によって、芯材28が所望の長さに形成できたら、次
に第4工程として図4(e)に示すように、レジスト膜
24(および1又は2以上の第2レジスト膜30)を除
去する。これにより、各電極パッド12上に所定のピッ
チでマトリクス状に配置された所定の太さの芯材28が
形成される。次に、上記のように電極パッド12とラン
ド18に形成された柱状体20、22同士は、相互に相
手の柱状体22、20間に形成される隙間に嵌まり合
い、着脱自在に連結されるから、連結の際には若干傾き
(曲がり)、連結が解除された場合には元の直線形状に
戻らなければならない。また、場合によっては連結の際
に互いの先端同士が当接し合うこともあり、簡単に曲が
ってしまうものでは困る。よって、柱状体20、22に
は一定の剛性と弾性力を持たせる必要がある。このた
め、柱状体20、22の表面全体に、被覆層( Ni,Auめ
っき)を形成する。
After the core material 28 can be formed to a desired length by one or several times of the second and third steps, the resist film is formed as a fourth step as shown in FIG. 24 (and one or more second resist films 30) are removed. As a result, core members 28 having a predetermined thickness are formed on each of the electrode pads 12 in a matrix at a predetermined pitch. Next, the columnar bodies 20, 22 formed on the electrode pad 12 and the land 18 as described above are fitted into the gap formed between the opposing columnar bodies 22, 20, and are removably connected. Therefore, the connection must be slightly inclined (bent) at the time of connection, and must return to the original linear shape when the connection is released. Further, in some cases, the tips of the two may abut each other at the time of connection, so that it is not easy to bend easily. Therefore, the columnar bodies 20 and 22 need to have a certain rigidity and elasticity. For this reason, a coating layer (Ni, Au plating) is formed on the entire surfaces of the columnar bodies 20 and 22.

【0019】第5工程として、図4(f)に示すよう
に、被実装体10の電極パッド12や他の導体パターン
(不図示)の形成面(詳細にはこの形成面上に形成され
た給電層)上に、液状のフォトレジストを数回塗布して
所定の厚さのレジスト膜44を形成する。次に、第6工
程として、形成したレジスト膜44をフォトリソグラフ
ィーにより処理して各電極パッド12領域を露出させる
(図4(g))。この処理により各電極パッド12上に
形成された芯材28も露出する。
As a fifth step, as shown in FIG. 4 (f), the surface on which the electrode pads 12 and other conductor patterns (not shown) of the mounted body 10 are formed (specifically, formed on this surface). A liquid photoresist is applied several times on the power supply layer) to form a resist film 44 having a predetermined thickness. Next, as a sixth step, the formed resist film 44 is processed by photolithography to expose each electrode pad 12 region (FIG. 4G). By this process, the core material 28 formed on each electrode pad 12 is also exposed.

【0020】次に、第7工程として、給電層から給電し
てレジスト膜44から露出する金属部位に、Niめっきと
Auめっきを順次施す。これにより、NiめっきとAuめっき
とからなる被覆層34が、露出している電極パッド12
と芯材28の表面に形成される(図4(h))。芯材2
8は表面に被覆層34が形成されることによって柱状体
20となる。その後、第8工程としてレジスト膜44を
除去し、さらに給電層をエッチングで除去する(図4
(i))。また、実装基板16の各ランド18上にも同
様の工程によって、柱状体22を形成することができ
る。
Next, as a seventh step, Ni plating is applied to a metal portion exposed from the resist film 44 by supplying power from the power supply layer.
Apply Au plating sequentially. As a result, the coating layer 34 made of Ni plating and Au plating is exposed to the exposed electrode pad 12.
And on the surface of the core material 28 (FIG. 4 (h)). Core material 2
8 becomes the columnar body 20 by forming the coating layer 34 on the surface. Thereafter, the resist film 44 is removed as an eighth step, and the power supply layer is further removed by etching (FIG. 4).
(I)). Further, the columnar body 22 can be formed on each land 18 of the mounting board 16 by the same process.

【0021】なお、上述した工程では、芯材28の形成
は電解Cuメッキで行っていたが、給電層を電極パッド1
2の形成面に形成せず、上述した第2工程と第3工程に
おいて、レジスト膜24に形成された微細ホール26内
の電極パッド12上に無電解Cuメッキで芯材28を直接
形成する方法も可能である。なお、この場合にも一回の
無電解Cuメッキで形成できる芯材28の長さは短いと考
えられるから、上述したように第2工程と第3工程を必
要な回数だけ繰り返し、芯材28を所望の長さとする。
また、図示はしないが、芯材28はワイヤーボンディン
グによっても形成することができる。
In the above-described process, the core material 28 is formed by electrolytic Cu plating.
A method of directly forming the core material 28 by electroless Cu plating on the electrode pads 12 in the fine holes 26 formed in the resist film 24 in the second step and the third step described above without forming the core material 28 on the formation surface of the resist film 24 Is also possible. In this case, the length of the core material 28 that can be formed by one electroless Cu plating is considered to be short. Therefore, as described above, the second step and the third step are repeated as many times as necessary, and the core material 28 is formed. To the desired length.
Although not shown, the core member 28 can also be formed by wire bonding.

【0022】また、図4(f)〜(i)の工程に代え
て、他の第5工程として、図4(f)に示すように、給
電層をエッチングで選択的に除去した後に、芯材28の
表面(電極パッド12の表面も同様)に無電解Niめっき
(若しくは下地無電解Niめっきと無電解Auめっき)を施
し、被覆層34を形成するようにしても良い。この方法
は実装基板16の各ランド18上に柱状体22を形成す
る場合にも適用できる。なお、この場合、給電層を銅で
形成しても、給電層の厚さは同じく銅で構成される芯材
28の太さに比較して非常に薄いので、芯材28の表面
が多少浸食されるだけで、給電層をエッチングで完全に
除去することもできる。
Further, instead of the steps of FIGS. 4F to 4I, as a fifth step, as shown in FIG. 4F, after the power supply layer is selectively removed by etching, the core is removed. The coating layer 34 may be formed by applying electroless Ni plating (or the underlying electroless Ni plating and electroless Au plating) to the surface of the material 28 (the surface of the electrode pad 12 is also the same). This method can be applied to the case where the columnar body 22 is formed on each land 18 of the mounting board 16. In this case, even if the power supply layer is formed of copper, the thickness of the power supply layer is very thin compared to the thickness of the core material 28 also made of copper, so that the surface of the core material 28 is slightly eroded. However, the power supply layer can be completely removed by etching.

【0023】また、さらに実装基板16の各ランド18
上に柱状体22を形成する場合において、芯材28の表
面に被覆層34を形成する工程では、特願昭63−96
579号に開示された技術を用いることも可能である。
すなわち、予め実装基板16内層において各ランド18
個々に接続される配線パターンを実装基板16の周縁部
分に導き、各配線パターンの周縁側の端部同士を実装基
板16の周縁に沿って延びる導通パターン部で電気的に
接続しておく。そして、図4(h)に示す第7工程にお
いては、給電層に代えてこの導通パターン部から給電し
てレジスト膜44から露出する金属部位に、Niめっきと
Auめっきを順次施す。そして、最後に図4に示す第8工
程として、レジスト膜44を除去すると共に、給電層の
除去作業に代えて、実装基板16の周縁部分を研削する
(導通パターン部が露出している場合にはエッチングす
る)ことによって導通パターン部を除去し、各ランド1
8同士の電気的導通を断つ。
Further, each land 18 of the mounting board 16
In the case of forming the columnar body 22 thereon, in the step of forming the coating layer 34 on the surface of the core material 28, Japanese Patent Application No. 63-96
It is also possible to use the technique disclosed in US Pat.
That is, each land 18 is previously formed in the inner layer of the mounting
The individually connected wiring patterns are led to the peripheral portion of the mounting substrate 16, and the ends on the peripheral side of each wiring pattern are electrically connected to each other by a conductive pattern portion extending along the peripheral edge of the mounting substrate 16. Then, in a seventh step shown in FIG. 4H, Ni plating is applied to the metal portion exposed from the resist film 44 by supplying power from the conductive pattern portion instead of the power supply layer.
Apply Au plating sequentially. Finally, as an eighth step shown in FIG. 4, the resist film 44 is removed, and the periphery of the mounting substrate 16 is ground in place of the operation of removing the power supply layer (when the conductive pattern portion is exposed). Is etched) to remove the conductive pattern portion.
The electrical continuity between the 8 is cut off.

【0024】また、柱状体22を形成する被覆層34と
して、はんだめっきを施し、半導体チップ等の被実装体
10を実装基板16へ一旦搭載し、電気的試験を終えた
後に、試験の結果、合格となったものに関しては、その
後加熱処理を行い、被覆層34を形成していたはんだを
溶かし、被実装体10と実装基板16の双方の柱状体2
0、22同士をはんだ接合することも可能である。これ
により、合格品に関してより強固な接続状態として出荷
することができるようになる。なお、この場合には被実
装体10のはんだ付け後の取り外しは困難になるが、不
合格になったものに関しては実装基板16から被実装体
10を取り外し、再度別の被実装体10を取り付けて実
装基板16を再利用できるので、有効である。
Further, as a coating layer 34 forming the columnar body 22, solder plating is applied, the mounted body 10 such as a semiconductor chip is once mounted on the mounting board 16, and after the electrical test is completed, the test results are as follows. Those that passed the test were then subjected to a heat treatment to melt the solder that had formed the coating layer 34, and the columnar members 2 of both the mounted body 10 and the mounting board 16 were heated.
It is also possible to solder-join 0 and 22 together. As a result, it is possible to ship the accepted product in a stronger connection state. In this case, it is difficult to remove the mounted body 10 after soldering. However, in the case of a failed board, the mounted body 10 is removed from the mounting board 16 and another mounted body 10 is attached again. This is effective because the mounting substrate 16 can be reused.

【0025】(第2の実施の形態)最初に、本実施の形
態の基本的な考え方について図5と図6を用いて説明す
る。なお、第1の実施の形態と同じ構成については同じ
符号を付し、詳細な説明は省略する。その考え方は、半
導体チップ若しくは半導体装置(被実装体10)を実装
基板16へ、被実装体10の表面に形成された複数の電
極パッド12と実装基板16の表面に形成された複数の
ランド18とを電気的に接続して実装する場合に、ま
ず、第1の実施の形態と同様に、図5に示すように電極
パッド12の各表面に、導電性の柱状体20を間隔をあ
けて複数本直角に立設する。
(Second Embodiment) First, the basic concept of the present embodiment will be described with reference to FIGS. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The idea is that a semiconductor chip or a semiconductor device (mounted body 10) is mounted on a mounting board 16, a plurality of electrode pads 12 formed on the surface of the mounted body 10 and a plurality of lands 18 formed on the surface of the mounting board 16. When electrically connecting and mounting, first, similarly to the first embodiment, as shown in FIG. 5, a conductive columnar body 20 is provided on each surface of the electrode pad 12 at intervals. Erect multiple at right angles.

【0026】次に、図5に示すように実装基板16の複
数のランド18の形成領域A上に、厚み方向に沿って厚
さBと同じ長さの無数の導電性の柱状体36が両端を露
出させ、外周面同士が相互に接触しない状態で非導電性
ゴム材38中に略平行に埋設されて成る公知の異方性導
電シート40を固着する。実際には、接着等の手段によ
って実装基板16上に固定する。そして、被実装体10
は図6に示すように、異方性導電シート40を介して実
装基板16へ押しつけられ、電極パッド12に形成され
た複数の柱状体20が異方性導電シート40に突き刺さ
さる。そして突き刺さった柱状体20が、電極パッド1
2に対応する位置のランド18の領域にある異方性導電
シート40中の複数の柱状体36間に双方の外周面同士
が接触した状態で嵌まり込んで実装される。
Next, as shown in FIG. 5, an infinite number of conductive pillars 36 having the same length as the thickness B along the thickness direction are formed on the regions A where the plurality of lands 18 of the mounting board 16 are formed. Is exposed, and a known anisotropic conductive sheet 40 buried substantially in parallel with the non-conductive rubber material 38 in a state where the outer peripheral surfaces are not in contact with each other is fixed. Actually, it is fixed on the mounting substrate 16 by means such as adhesion. Then, the mounted body 10
As shown in FIG. 6, is pressed against the mounting substrate 16 via the anisotropic conductive sheet 40, and the plurality of columnar bodies 20 formed on the electrode pads 12 pierce the anisotropic conductive sheet 40. The pierced columnar body 20 is the electrode pad 1
2 are fitted and mounted between the plurality of columnar bodies 36 in the anisotropic conductive sheet 40 in the region of the land 18 at the position corresponding to 2 in a state where both outer peripheral surfaces are in contact with each other.

【0027】これにより、被実装体10の各電極パッド
12に形成された柱状体20と、この電極パッド12に
対応する実装基板16のランド18の領域に配置された
異方性導電シート40中の柱状体36とは外周面同士が
接触する。そして、異方性導電シート40は被実装体1
0により実装基板16へ押しつけられているため、ラン
ド18の領域内にある異方性導電シート40中の柱状体
36の下端はランド18と接触する。よって、被実装体
10の電極パッド12と実装基板16のランド18とは
各々の柱状体20、36を介して電気的に接続されるこ
とになる。また、被実装体10の柱状体20は異方性導
電シート40の非導電性ゴム材40中に差し込まれてい
るだけであるから、被実装体10の実装基板16への押
しつけを解除し、さらに被実装体10に実装基板16か
ら離反する方向の所定の大きさの外力を加えることによ
って、被実装体10の柱状体20を非導電性ゴム材38
から抜けば、第1の実施の形態と同様に被実装体10を
実装基板16から比較的簡単に取り外すことも可能であ
る。また、再度、装着することも可能である。
Thus, the columnar body 20 formed on each electrode pad 12 of the mounted body 10 and the anisotropic conductive sheet 40 arranged in the region of the land 18 of the mounting board 16 corresponding to the electrode pad 12 The outer peripheral surfaces of the columnar body 36 are in contact with each other. Then, the anisotropic conductive sheet 40 is
The lower end of the columnar body 36 in the anisotropic conductive sheet 40 in the area of the land 18 comes into contact with the land 18 because it is pressed against the mounting board 16 by the zero. Therefore, the electrode pads 12 of the mounted body 10 and the lands 18 of the mounting board 16 are electrically connected through the respective pillars 20 and 36. Further, since the columnar body 20 of the mounted body 10 is only inserted into the non-conductive rubber material 40 of the anisotropic conductive sheet 40, the pressing of the mounted body 10 against the mounting board 16 is released, Further, by applying an external force having a predetermined magnitude in a direction away from the mounting substrate 16 to the mounted body 10, the columnar body 20 of the mounted body 10
If it comes out, the mounted object 10 can be relatively easily removed from the mounting board 16 as in the first embodiment. It is also possible to mount it again.

【0028】本実施の形態では、被実装体10の電極パ
ッド12側に柱状体20を形成し、異方性導電シート4
0は実装基板16側に配置したが、その逆、つまり実装
基板16側に第1の実施の形態のように柱状体22を形
成して電極パッド12側には柱状体20を形成せずに異
方性導電シート40を取り付ける構成でも良い。本実施
の形態のように、実装基板16側の柱状体36が非導電
性ゴム材38中に埋設された構成の場合には、柱状体3
6は非導電性ゴム材38によって保護されているから、
折れにくく、かつ曲がりにくいという特徴がある。従っ
て、第1の実施の形態の場合においても、被実装体10
の電極パッド12の形成領域、若しくは実装基板16の
ランド18の形成領域のいずれか一方を、電極パッド1
2若しくはランド18に突設された柱状体20、22の
長さと略同じ厚さの弾性を有する樹脂材で覆うことによ
って、第2の実施の形態の異方性導電シート40の場合
と同様に樹脂材で覆われた柱状体20、22が折れた
り、曲がったりすることを抑制することも可能となる。
一例として被実装体10の電極パッド12の形成領域C
に適用する場合には、図1の点線で示すごとく樹脂材4
2で柱状体20を覆えば良い。
In this embodiment, the columnar body 20 is formed on the side of the electrode pad 12 of the mounted body 10 and the anisotropic conductive sheet 4 is formed.
0 is disposed on the mounting board 16 side, but the reverse, that is, the columnar body 22 is formed on the mounting board 16 side and the columnar body 20 is not formed on the electrode pad 12 side as in the first embodiment. A configuration in which the anisotropic conductive sheet 40 is attached may be used. In the case where the column 36 on the mounting board 16 side is embedded in the non-conductive rubber material 38 as in the present embodiment, the column 3
6 is protected by the non-conductive rubber material 38,
There is a feature that it is hard to break and hard to bend. Therefore, also in the case of the first embodiment, the mounted body 10
Either the electrode pad 12 formation region or the land 18 formation region of the mounting substrate 16 is
By covering with an elastic resin material having substantially the same thickness as the length of the columnar bodies 20 and 22 protruding from the land 2 or the land 18, similarly to the case of the anisotropic conductive sheet 40 of the second embodiment, It is also possible to prevent the columnar bodies 20 and 22 covered with the resin material from being bent or bent.
As an example, the formation region C of the electrode pad 12 of the mounted body 10
When applied to the resin material 4 as shown by the dotted line in FIG.
The column 20 may be covered with 2.

【0029】上述した第1の実施の形態や第2の実施の
形態のように、電極パッド12および/またはランド1
8上に柱状体20、22を立設して、被実装体10を実
装基板16に対して着脱自在に実装する実装構造は、確
かに決まった面積の電極パッド12やランド18上に複
数の柱状体20、22を立設しなければならないため、
電極パッド12やランド18の面積が小さい場合や、電
極パッド12やランド18の間隔が狭く、また数が多い
場合には柱状体20、22の形成に手間がかかる。しか
しながら、システムLSIのように入出力用の電極が比
較的少なくなるものについては有効であると考えられ
る。
As in the above-described first and second embodiments, the electrode pad 12 and / or the land 1
The mounting structure in which the columnar bodies 20 and 22 are erected on the mounting board 8 and the mounted body 10 is detachably mounted on the mounting board 16 has a plurality of electrode pads 12 and lands 18 having a fixed area. Since the pillars 20, 22 must be erected,
When the area of the electrode pads 12 and the lands 18 is small, or when the distance between the electrode pads 12 and the lands 18 is small and the number is large, it takes time to form the columnar bodies 20 and 22. However, it is considered effective for a system LSI having a relatively small number of input / output electrodes, such as a system LSI.

【0030】以上、本発明の好適な実施例について種々
述べてきたが、本発明は上述の実施例に限定されるので
はなく、発明の精神を逸脱しない範囲で多くの改変を施
し得るのはもちろんである。
Although the preferred embodiments of the present invention have been described in various ways, the present invention is not limited to the above-described embodiments, and it is noted that many modifications can be made without departing from the spirit of the invention. Of course.

【0031】[0031]

【発明の効果】本発明に係る半導体チップ若しくは半導
体装置の実装基板への実装構造によれば、従来のように
実装時や取り外し時に加熱してバンプ形成素材(はんだ
等)を溶かす必要がなくなり、半導体チップ若しくは半
導体装置の実装基板への実装や実装基板からの取り外し
が比較的簡単に行える。また、取り外した被実装体の再
実装も簡単に行えるという効果を奏する。
According to the structure for mounting a semiconductor chip or a semiconductor device on a mounting substrate according to the present invention, it is not necessary to heat the material for forming bumps (solder or the like) by heating at the time of mounting or removing as in the prior art. A semiconductor chip or a semiconductor device can be mounted on a mounting substrate or removed from the mounting substrate relatively easily. Further, there is an effect that the detached mounted body can be easily remounted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体チップ若しくは半導体装置
の実装基板への実装構造の第1の実施の形態を説明する
ための説明図である(実装前の状態図)。
FIG. 1 is an explanatory diagram for explaining a first embodiment of a mounting structure of a semiconductor chip or a semiconductor device on a mounting substrate according to the present invention (state diagram before mounting).

【図2】図1の半導体チップ若しくは半導体装置を実装
基板への実装した状態を示す説明図である。
FIG. 2 is an explanatory diagram showing a state in which the semiconductor chip or the semiconductor device of FIG. 1 is mounted on a mounting board.

【図3】図1の電極パッドに形成された柱状体の構造
と、この柱状体間に嵌まり込む実装基板側の柱状体との
関係を示す平面図である。
FIG. 3 is a plan view showing the relationship between the structure of a columnar body formed on the electrode pad of FIG. 1 and a columnar body on the mounting board side fitted between the columnar bodies.

【図4】図1の半導体チップ若しくは半導体装置、また
実装基板に形成される柱状体の形成工程を示す説明図で
ある。
FIG. 4 is an explanatory view showing a step of forming a columnar body formed on the semiconductor chip or the semiconductor device of FIG. 1 and a mounting substrate.

【図5】本発明に係る半導体チップ若しくは半導体装置
の実装基板への実装構造の第2の実施の形態を説明する
ための説明図である(実装前の状態図)。
FIG. 5 is an explanatory diagram for explaining a second embodiment of the mounting structure of the semiconductor chip or the semiconductor device on the mounting substrate according to the present invention (state diagram before mounting).

【図6】図5の半導体チップ若しくは半導体装置を実装
基板への実装した状態を示す説明図である。
6 is an explanatory diagram showing a state where the semiconductor chip or the semiconductor device of FIG. 5 is mounted on a mounting board.

【図7】従来の半導体チップ若しくは半導体装置の実装
基板へのバンプを用いた実装構造を説明するための説明
図である(実装前の状態図)。
FIG. 7 is an explanatory diagram for explaining a conventional mounting structure of a semiconductor chip or a semiconductor device on a mounting substrate using bumps (state diagram before mounting).

【符号の説明】[Explanation of symbols]

10 被実装体(半導体チップ若しくは半導体装置) 12 電極パッド 16 実装基板 18 ランド 20 柱状体(電極パッド側) 22 柱状体(ランド側) REFERENCE SIGNS LIST 10 mounted object (semiconductor chip or semiconductor device) 12 electrode pad 16 mounting substrate 18 land 20 columnar body (electrode pad side) 22 columnar body (land side)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ若しくは半導体装置の表面
に形成された複数の電極パッドと実装基板の表面に形成
された複数のランドとを電気的に接続して実装する、半
導体チップ若しくは半導体装置の実装基板への実装構造
において、 前記電極パッドおよび前記ランドの各表面には、導電性
の柱状体が間隔をあけて複数本直角に立設され、 前記半導体チップ若しくは前記半導体装置は、前記電極
パッドに形成された複数の柱状体が、該電極パッドに対
応する位置の前記ランドに形成された複数の柱状体間に
差し込まれると共に、双方の柱状体の外周面同士が相互
に接触した状態で嵌まり込んで実装されていることを特
徴とする、半導体チップ若しくは半導体装置の実装基板
への実装構造。
1. A semiconductor chip or semiconductor device mounting method in which a plurality of electrode pads formed on a surface of a semiconductor chip or a semiconductor device and a plurality of lands formed on a surface of a mounting substrate are electrically connected and mounted. In the mounting structure on the substrate, a plurality of conductive pillars are provided at right angles at intervals on each surface of the electrode pad and the land, and the semiconductor chip or the semiconductor device is provided on the electrode pad. The formed plurality of pillars are inserted between the plurality of pillars formed on the lands at positions corresponding to the electrode pads, and fitted in a state where the outer peripheral surfaces of both pillars are in contact with each other. A mounting structure of a semiconductor chip or a semiconductor device on a mounting substrate, wherein the mounting structure is mounted on the mounting substrate.
【請求項2】 半導体チップ若しくは半導体装置の表面
に形成された複数の電極パッドと実装基板の表面に形成
された複数のランドとを電気的に接続して実装する、半
導体チップ若しくは半導体装置の実装基板への実装構造
において、 前記電極パッドの各表面には、導電性の柱状体が間隔を
あけて複数本直角に立設され、 前記実装基板の複数のランドの形成領域上には、厚み方
向に沿って厚さと同じ長さの無数の導電性の柱状体が両
端を露出させ、外周面同士が相互に接触しない状態で非
導電性ゴム材中に埋設されて成る異方性導電シートが固
着され、 前記半導体チップ若しくは前記半導体装置は、前記異方
性導電シートを介して前記実装基板へ押しつけられて、
前記電極パッドに形成された複数の柱状体が前記異方性
導電シートに突き刺されると共に、該電極パッドに対応
する位置の前記ランドの領域にある異方性導電シート中
の複数の柱状体間に双方の柱状体の外周面同士が相互に
接触した状態で嵌まり込んで実装されていることを特徴
とする、半導体チップ若しくは半導体装置の実装基板へ
の実装構造。
2. A semiconductor chip or semiconductor device mounting method, wherein a plurality of electrode pads formed on a surface of a semiconductor chip or a semiconductor device and a plurality of lands formed on a surface of a mounting substrate are electrically connected and mounted. In the mounting structure on the substrate, a plurality of conductive pillars are erected at right angles with an interval on each surface of the electrode pad, and a thickness direction is formed on a region where a plurality of lands of the mounting substrate are formed. Anisotropic conductive sheets embedded in a non-conductive rubber material with both ends exposed by countless conductive pillars of the same length as The semiconductor chip or the semiconductor device is pressed against the mounting substrate via the anisotropic conductive sheet,
The plurality of pillars formed on the electrode pad are pierced into the anisotropic conductive sheet, and between the plurality of pillars in the anisotropic conductive sheet in a region of the land corresponding to the electrode pad. A mounting structure of a semiconductor chip or a semiconductor device on a mounting board, wherein the outer peripheral surfaces of both columnar bodies are fitted and mounted in a state of being in contact with each other.
JP10275734A 1998-09-29 1998-09-29 Structure for mounting semiconductor chip or semiconductor device on substrate Pending JP2000114434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10275734A JP2000114434A (en) 1998-09-29 1998-09-29 Structure for mounting semiconductor chip or semiconductor device on substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10275734A JP2000114434A (en) 1998-09-29 1998-09-29 Structure for mounting semiconductor chip or semiconductor device on substrate

Publications (1)

Publication Number Publication Date
JP2000114434A true JP2000114434A (en) 2000-04-21

Family

ID=17559652

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000114434A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007414A (en) * 2001-06-20 2003-01-10 Yamaichi Electronics Co Ltd Ic socket
WO2007086516A1 (en) * 2006-01-26 2007-08-02 Matsushita Electric Works, Ltd. Board-to-board connector
JP2009259980A (en) * 2008-04-15 2009-11-05 Toshiba Corp Electrode, semiconductor package, and substrate
JP2010219397A (en) * 2009-03-18 2010-09-30 Fujitsu Ltd Electronic component and method of manufacturing the same
JP2011054326A (en) * 2009-08-31 2011-03-17 Smk Corp Fine connector
JP2011192895A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor chip
JP2011192894A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor device
JP2012109086A (en) * 2010-11-16 2012-06-07 Japan Aviation Electronics Industry Ltd Brush connector unit
DE102019128900A1 (en) * 2019-10-25 2021-04-29 Endress+Hauser SE+Co. KG Method for producing an SMD-solderable component, SMD-solderable component, electronic unit and field device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007414A (en) * 2001-06-20 2003-01-10 Yamaichi Electronics Co Ltd Ic socket
WO2007086516A1 (en) * 2006-01-26 2007-08-02 Matsushita Electric Works, Ltd. Board-to-board connector
EP1978601A1 (en) * 2006-01-26 2008-10-08 Matsushita Electric Works, Ltd Board-to-board connector
US7674114B2 (en) 2006-01-26 2010-03-09 Panasonic Electric Works Co., Ltd. Board-to-board connector
EP1978601A4 (en) * 2006-01-26 2011-04-06 Panasonic Elec Works Co Ltd Board-to-board connector
JP2009259980A (en) * 2008-04-15 2009-11-05 Toshiba Corp Electrode, semiconductor package, and substrate
JP2010219397A (en) * 2009-03-18 2010-09-30 Fujitsu Ltd Electronic component and method of manufacturing the same
JP2011054326A (en) * 2009-08-31 2011-03-17 Smk Corp Fine connector
JP2011192895A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor chip
JP2011192894A (en) * 2010-03-16 2011-09-29 Zycube:Kk Method for mounting semiconductor device
JP2012109086A (en) * 2010-11-16 2012-06-07 Japan Aviation Electronics Industry Ltd Brush connector unit
DE102019128900A1 (en) * 2019-10-25 2021-04-29 Endress+Hauser SE+Co. KG Method for producing an SMD-solderable component, SMD-solderable component, electronic unit and field device

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