JP2011192894A - Method for mounting semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means capable of having a low profile in a structure in which semiconductor devices are stacked. <P>SOLUTION: A plurality of minute metal balls 13 are formed on a conductor 12 of the semiconductor device 10, and a plurality of minute metal balls 18 are formed on a conductor 17 of a semiconductor interposer 15 having a Young's modulus larger than that of a resin, and the metal balls are flip-chip bonded. As a result, the conductors are connected to each other via the minute metal balls to obtain a low profile. Also, shapes, sizes and arrangements of the metal balls are optimized so that a stacking process can be facilitated. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for mounting a semiconductor device with a reduced size and height.

  2. Description of the Related Art In recent years, technological advances in semiconductor devices have been great, and they have been used over a wide range such as industrial equipment and consumer equipment. As a result, it has greatly contributed to the downsizing, weight reduction, price reduction, and higher functionality of equipment and systems equipped with semiconductor devices. Typical examples are portable devices such as mobile phones and digital cameras. In these devices, the number of pixels and the size of the mounted image sensor are increasing, and the moving image playback function, the television reception function, and the like are also advanced. In addition, in order to overcome the limitation of the frequency band that can be used, a future technology such as a multi-frequency communication function, for example, cognitive communication, has attracted attention. In order to expand these functions, it is indispensable to mount many semiconductor devices in a limited space in the equipment. Semiconductor devices themselves are also becoming increasingly miniaturized and highly integrated, contributing to downsizing of devices and low power consumption. However, a method of mounting a semiconductor device in a narrow space is also important, and high expectations are placed on high-density mounting technology such as a three-dimensional stacked structure.

  When mounting semiconductor devices at high density, reduction of occupied area and reduction in height (reduction of occupied volume) are key. In particular, the low profile can contribute to the thinning of the device, and can meet the needs of “light thin and short” required for portable devices. For this reason, development of a technique for mounting a semiconductor device with a low profile has been strongly desired.

  In order to solve such a problem, the following cited non-patent document 1 shows a structure in which packaged semiconductor devices are stacked one above the other. According to this configuration, it is possible to reduce the height and size of the semiconductor device.

  FIG. 19 is a view showing a laminated structure shown in FIG. 1 of the following cited non-patent document 1. This figure shows a case where two surface-mounted semiconductor devices in which terminals for electrical connection are arranged in a matrix are stacked. In such a semiconductor device, a semiconductor chip is often electrically connected by a bonding wire on a resin interposer in which the terminals are arranged in a matrix. FIG. 2A shows a case where both the upper and lower semiconductor devices are formed by wire bonding technology. On the other hand, FIG. 5B shows a case where the upper semiconductor device is formed by wire bonding technology and the lower semiconductor device is manufactured by flip chip technology. In the flip-chip technology, a semiconductor device on which a circuit is formed is electrically connected to a resin interposer via a conductive ball with the surface thereof turned down (turned over). Such a configuration eliminates the need for a bonding wire, which helps to reduce the height. In the configuration shown in FIG. 19, as the upper semiconductor device, a commercially available surface-mount type semiconductor device can be used as it is unless a matrix-like terminal is arranged at the center of the lower surface of the semiconductor device. There is a big advantage.

  The size of each part in the configuration shown in FIG. 19 will be described. 19 in FIG. 19 is a resin-made interposer, the standard value of which is 130 micrometers, and the minimum value is about 100 micrometers. Further, regarding the interposer 2 of the semiconductor device disposed on the lower side, the minimum value of the thickness is as large as about 260 micrometers. Reference numeral 3 in FIG. 19 denotes conductive balls arranged in a matrix, the standard value of which is about 300 micrometers and the minimum value is about 270 micrometers. However, these values are values when the arrangement pitch of the conductive balls is 650 micrometers and when the structure shown in FIG. 19 is completed. Reference numeral 4 in FIG. 19 denotes an interval between the interposers. When the semiconductor chip has one stage and two stages, the minimum values are 270 micrometers and 320 micrometers, respectively. As shown in FIG. 19B, when the lower semiconductor device is manufactured by the flip chip technique, the minimum value of this value can be suppressed to about 230 micrometers.

Conference presentation paper Zwenger, et. al, “Next Generation Package-on-Package (PoP) Platform with Through Mold Mold”, IMAPS Device Packaging Conference, 12 March

  However, when pursuing a further reduction in height, the structure illustrated in FIG. 19 has a limit. This limiting factor is described in detail below.

Typical dimension values in the configuration example of FIG. 19 are as described above. Three typical factors that inhibit low profile are described below.
(1) Resin interposer thickness:
As described above, the minimum thickness is determined by the fact that the mechanical strength cannot be maintained if the interposer is made of resin and is extremely thin. In addition, regarding the interposer of the semiconductor device arranged on the lower side, the minimum thickness is increased in order to increase the mechanical strength so as not to be affected by warping or cracking of the interposer.
(2) Size of conductive balls connecting upper and lower semiconductor devices:
The size of the conductive balls is limited by the fact that the use of extremely small conductive balls results in the occurrence of terminals that cannot be connected because the variation in the size of individual conductive balls (corresponding to coplanarity) is limited.
(3) Height space for wire bonding:
As long as the wire bonding technology is adopted, it is important to secure a space for the wire. It is necessary to eliminate the space in the height direction by adopting another electrical connection technology such as flip chip technology.

  Due to the factors that hinder the above-described reduction in height, mounting problems include reducing the thickness of the interposer, reducing the size of the conductive ball, and reducing the space for electrical connection of the semiconductor chip. In other words, in order to realize a further reduction in height, (1) adoption of a material that can reduce the thickness of the interposer and development of the structure of the interposer, and (2) connection failure even if the size of the conductive ball is reduced. Development of a construction method that does not occur, and (3) development of a construction method that eliminates the need for wire bonding technology and reduces the space for electrical connection of semiconductor chips have become problems.

  Surface mount type first semiconductor device in which terminals for electrical connection are arranged in a matrix, surface mount type second semiconductor device in which terminals for electrical connection are arranged in a matrix or a wiring board A mounting method to be mounted on (1) from at least two for electrically connecting the semiconductor device to the second semiconductor device or the wiring board on the first main surface of the first semiconductor device. (2) each of the first conductors is provided with at least two first metal blocks, and (3) a second of the second semiconductor device or wiring board. A main conductor is provided with at least two second conductors for electrically connecting the semiconductor device or the wiring board to the first semiconductor device, and (4) each of the second conductors. And (5) the first semiconductor device and the second semiconductor device or the wiring board are connected to the first metal block and the second metal block. Electrical connection is made by joining metal blocks.

In this paragraph, the shapes of the first semiconductor device and the second semiconductor device described above will be described. There are many types of semiconductor device packages such as integrated circuit elements. There are various types of these classifications, and an example is described below.
(1) Classification by package material:
The mainstream is a shape in which a semiconductor chip is covered with a hard material such as plastic or ceramic. There is also TCP (or TAB) in which a semiconductor chip is mounted on a tape-shaped plastic film. Recently, a so-called chip size package has been put into practical use in which a semiconductor chip (interposer) is disposed on a semiconductor chip and terminals are disposed on the back side of the semiconductor chip in order to reduce the size of the semiconductor device. .
(2) Classification by implementation method:
An insertion mounting type in which the terminals for electrical connection are rod-shaped and the terminals are inserted into holes in a printed circuit board and fixed with solder; There is.
(3) Classification by terminal shape and direction:
A shape in which rod-like or plate-like leads are arranged in one or two directions of the package (DIP is a representative example), a shape in which plate-like leads are arranged in four directions of a package (QFP is a representative example), There are shapes in which ball-shaped terminals are arranged in a matrix (lattice) on the back surface of the package (BGA is a typical example).

  Note that the “semiconductor device” in this specification is a “surface mount type in which terminals for electrical connection are arranged in a matrix” as described above. That is, the packaging material described in the previous paragraph is not limited. Further, the electrical connection terminal does not include a rod-like or plate-like shape. Further, the present invention is not limited to the mounting form and connection technology of the semiconductor chip in the “semiconductor device”. For example, the “semiconductor device” includes (1) a form in which a semiconductor chip is mounted on an interposer, (2) a form in which the semiconductor chip and the interposer are electrically connected by flip chip technology, and (3) a semiconductor chip and the interposer. And (4) a form in which ball-shaped terminals are arranged in a matrix on the back surface of the interposer.

  In the present invention, it is assumed that the first semiconductor device is mounted on the above-described “second semiconductor device or wiring board”.

  In addition, “joining” of “electrically connecting by joining the first metal block and the second metal block” described in the above paragraph is simply electrical contact, mechanically the two metal blocks. And a form in which the two metal masses are melted and re-solidified by high-temperature treatment.

  In the present invention, the first semiconductor device and the second semiconductor device or the wiring board are electrically connected to a plurality of minute metal blocks arranged at individual terminal portions of the first semiconductor device. (This is a ball-shaped terminal and corresponds to the conductive ball in the conventional example described above). By miniaturizing the metal block, the limitation of low profile due to “(2) size of conductive ball connecting upper and lower semiconductor devices” in the conventional example is overcome. Further, by arranging a plurality of metal lumps, the yield of electrical connection due to coplanarity is improved, the reliability is improved, and the maximum value of flowing current is increased.

  The first semiconductor device includes a stacked structure of a semiconductor chip and a semiconductor interposer, and the first conductor and the first conductor are disposed on a main surface of the semiconductor interposer opposite to a main surface on which the semiconductor chip is disposed. Place a metal lump.

  The main surface of the semiconductor interposer on which the first conductor and the first metal block described in the previous paragraph are arranged is the above-described first main surface of the first semiconductor device. It corresponds.

  In the present invention, a semiconductor (for example, silicon) is used as the material for the interposer. A semiconductor chip is mounted on the front side of the interposer, and terminals (metal blocks) for electrical connection of the semiconductor device are arranged on the back side of the interposer. As described above, the thickness of the semiconductor interposer is about 200 micrometers or less without reducing its mechanical strength as compared with the case where the interposer is made of a conventional resin material. The advantage that the thickness can be reduced to a certain extent occurs.

  When the semiconductor chip constituting the first semiconductor device and the semiconductor interposer are stacked, (1) the first conductor or the first conductor is disposed on a surface of the semiconductor chip facing the semiconductor interposer. (2) arranging the second conductor or the second metal mass on a surface where the semiconductor interposer faces the semiconductor chip, and (2) the semiconductor chip and the semiconductor interposer, A mounting method in which the first metal block and the second metal block are electrically connected by joining is also possible. That is, in order to realize the first semiconductor device, it is to use the joining of the first metal block and the second metal block.

  The first metal block and the second metal block each have a circular shape in contact with the first conductor and the second conductor, and the diameter of the circle and the first metal The ratio of the arrangement pitch of the lump and the second metal lump is set to a value exceeding 0.58.

  In addition, in this paragraph, it describes about the shape of the said 1st metal lump and the said 2nd metal lump, a magnitude | size, and arrangement pitch. It is preferable that the first metal block and the second metal block have the same shape, size, and arrangement pitch, but this is not necessarily the case. If they are equal to each other and the shape is hemispherical, it is preferable that the ratio between the diameter and the arrangement pitch of the first metal block and the second metal block is set to be larger than 0.58. In such a setting, when the first semiconductor device and the second semiconductor device or the wiring board are stacked to face each other, the mutual positional relationship between the first metal block and the second metal block. Regardless, there is an advantage that these metal blocks can be joined. As for the arrangement form of the first metal lump and the second metal lump, (1) a form in which these metal lumps are arranged at the intersections of the mesh of the “baked net”, (2) “ There is a form such as “staggered arrangement” in which each line is shifted by a half pitch.

  Each of the first metal block and the second metal block has a polygonal shape in contact with the first conductor and the second conductor, and a diameter of a circle inscribed in the polygon. The ratio of the arrangement pitch of the first metal block and the second metal block is set to a value exceeding 0.58.

  In addition, in this paragraph, it describes about the shape and arrangement | sequence of said 1st metal lump and said 2nd metal lump. The first metal block and the second metal block are not hemispheres, and the shape of the first metal block and the second metal block in contact with the first conductor and the second conductor is a polygon including a quadrangle (this specification) In this case, both of the metal blocks can be regarded as “a pyramid shape with a rounded top and ridge line”. In such a case, the ratio between the “diameter of the polygonal inscribed circle” of the first metal block and the second metal block and the arrangement pitch thereof is set to be larger than 0.58. Regardless of the positional relationship between one metal lump and the second metal lump, these metal lumps can be joined.

  The first metal block and the second metal block each have a shape in contact with the first conductor and the second conductor as an ellipse or an ellipse, and constitute the first metal block The major axis of the ellipse or the ellipse that intersects the major axis of the ellipse or the ellipse that constitutes the second metal block.

  In addition, in this paragraph, it describes about the arrangement | positioning form of the metal lump described in the previous paragraph. The major axis of the ellipse (or oval) of the first metal block and the major axis of the ellipse (or ellipse) of the second metal block intersect. The angle of the intersection is preferably 90 degrees, but is not limited thereto. Since these major axes intersect each other, when the first metal mass and the second metal mass are joined, the first metal is independent of the mutual positional relationship between the metal masses. Joining of the mass with the second metal mass is achieved.

  The first metal block and the second metal block are striped in contact with the first conductor and the second conductor, respectively, and constitute the first metal block The stripe and the stripe constituting the second metal block are crossed with each other.

  In addition, in this paragraph, it describes about the arrangement | positioning form of the metal lump described in the previous paragraph. The shape of the first metal block and the second metal block is a stripe (elongated line), and a plurality of stripes are arranged in parallel. The stripes forming the first metal block and the stripes forming the second metal block are in a positional relationship so as to intersect each other. The angle of the intersection is preferably 90 degrees, but is not limited thereto. Since these stripes cross each other, when the first metal mass and the second metal mass are joined, the first metal is independent of the positional relationship between the metal masses. Joining of the mass with the second metal mass is achieved.

  The thickness of the semiconductor interposer in a specified region within the region where the semiconductor chip is mounted, and the thickness of the semiconductor interposer in the region where the first conductor and the first metal block are disposed. Do not exceed.

  The thickness of the semiconductor interposer is not a specified constant value, and a configuration in which the thickness of the specified region of the semiconductor interposer is smaller than the thickness of other regions is also included in the present invention. For example, the thickness of the region occupying the central portion of the semiconductor interposer is made smaller than the thickness of the peripheral region of the semiconductor interposer. The “designated region” is a region where the semiconductor chip is mounted, and is generally a region having an area smaller than the area of the semiconductor chip. Further, when partially reducing the thickness of the semiconductor interposer, the semiconductor interposer may be dug from the surface side of the semiconductor interposer by a known method such as etching, or may be dug from the back side of the semiconductor interposer. Furthermore, the thickness may be partially reduced by digging from both sides of the front and back surfaces of the semiconductor interposer.

  In the present invention, a “two-stage configuration” (the wiring board is also one stage) is shown in which the first semiconductor device is mounted on the “second semiconductor device or wiring board” described above. However, the present invention is not limited to this, and a multi-stage configuration of three or more stages may be used. In the case of such a multistage configuration, the overall height of the multistage configuration is reduced by a configuration in which the thickness of the specified region of the semiconductor interposer is partially reduced as described in the previous paragraph. The advantage that it can be lowered (lower profile) occurs.

  An opening shape is provided at the center of the semiconductor interposer, and a semiconductor chip is mounted on top of the opening shape.

  Note that an opening may be provided in the semiconductor interposer, and the peripheral region of the semiconductor chip may be supported by the semiconductor interposer. In this configuration, the ends of the four sides of the semiconductor chip may be supported by the opening shape of the semiconductor interposer, and further, the ends of the two opposite sides of the semiconductor chip are supported by the opening shape of the semiconductor interposer. You may do it.

  In the present invention, a “two-stage configuration” (the wiring board is also one stage) is shown in which the first semiconductor device is mounted on the “second semiconductor device or wiring board” described above. However, the present invention is not limited to this, and a multi-stage configuration of three or more stages may be used. In the case of such a multi-stage configuration, there is an advantage that the overall height of the multi-stage configuration can be reduced (low profile) by the configuration having an opening at the center of the semiconductor interposer as described in the previous paragraph. appear.

  Note that, when the first metal block and the second metal block are bonded, in order to increase the bonding strength, the periphery of the bonding region or the first semiconductor device and the above-mentioned “first” An underfill formed of a resin or the like may be provided between the “second semiconductor device or the wiring board”. There are many types of resins used for the underfill, and examples include thermoplastic resins, thermosetting resins, and conductive resins containing conductors. Also, there are many grades with different viscosities and melting points for specific resins. However, the present invention is not limited to the type or grade of resin used for underfill. For example, a functional resin called a pre-applied resin (solder particles are mixed in a thermosetting resin) is used, and the resin has “melted solder particles gather and re-solidify in the region where the conductor exists. In other words, it is possible to use the property that only the resin remains and solidifies in a region where no conductor exists.

  According to the present invention, there has been provided a mounting method that achieves a further reduction in height as compared with the conventional example.

  An electrical connection between the first semiconductor device and the second semiconductor device or the wiring board is made up of a plurality of minute metal blocks (ball-shaped terminals and terminals) arranged at individual terminal portions of the first semiconductor device. The problem of the size of the conductive ball, which has conventionally been a limiting factor for reducing the height, can be overcome. Furthermore, by arranging a plurality of the metal masses, it was possible to improve the yield of electrical connection, improve the reliability, and increase the maximum value of flowing current due to coplanarity.

  The shape of the first metal block and the second metal block is a hemisphere, and its radius is r. Under such conditions, in a state where the first semiconductor device is opposed to the second semiconductor device or the wiring substrate and the two metal blocks are in contact with each other, the first main surface of the first semiconductor device and the first semiconductor device The distance from the second main surface of the second semiconductor device or the wiring board is 2r. Further, since the sum of the volumes of the two metal blocks is the volume of a sphere having a radius r, the value is (4π / 3) × r ^ 3. Here, the notation “r ^ 3” represents “r to the third power”. Next, it is assumed that the temperature of the two metal lumps is raised and both melt and become a cylinder. In such a state, the bottom area of the cylinder is considered to be πr ^ 2, so the height of the cylinder is 4r / 3. As a result, the distance between the two main surfaces is reduced to 4r / 3. In the molten state, the distance between the main surfaces is smaller than 4r / 3 because the center portion is not a perfect cylinder but close to a “via barrel” shape in which the central portion is swollen. That is, in the process of contacting and melting the two metal lumps, the distance between the main surfaces is proportional to the size of the metal lumps. For example, in the case of r = 280 micrometers (standard value of the conductive ball in the conventional example), the distance between the main surfaces is 370 micrometers (this value is less than this value in the via barrel shape). On the other hand, in the case of r = 5 micrometers (the numerical value exemplified as an example when the present invention is implemented), the distance between the main surfaces is 7 micrometers (this value is less than this value in the via barrel shape). That is, by reducing the size of the metal lump (conductive ball), the limit of low profile caused by the above-mentioned “(2) Size of conductive ball connecting upper and lower semiconductor devices” is overcome. Is possible. Further, by miniaturizing the metal lump, the size of each metal lump varies (coplanarity is deteriorated), and it becomes difficult to achieve contact and melting between two opposed metal lumps. However, by disposing at least two metal blocks, the number of metal blocks that can be contacted and melted can be increased, and the coplanarity problem can be solved.

  When the first metal block and the second metal block have a circular shape in contact with the first conductor and the second conductor, the diameter is d, and the arrangement pitch is p, By setting the ratio of the diameter to the arrangement pitch (= d / p) to a value exceeding 0.58, the eye in the process of electrically connecting the first semiconductor device and the second semiconductor device or the wiring board The alignment accuracy could be greatly improved. That is, when the ratio is 0.58 or more, it is possible to reliably form an electric conduction path without being limited to the relative position between the first metal block and the second metal block. . Further, when the shape of the first metal block and the second metal block is a polygon including a square, the ratio of the diameter of the circle inscribed in the polygon and the arrangement pitch exceeds 0.58. By using the value, the alignment accuracy can be improved.

  The shape of the first metal block and the second metal block contacting the first conductor and the second conductor is an ellipse or an ellipse, respectively, and the major axes of the ellipse or the ellipse are By crossing, the alignment accuracy can be improved. Further, the first metal block and the second metal block are in a stripe shape in contact with the first conductor and the second conductor, respectively, and by crossing the stripes, It has become possible to further improve the alignment accuracy.

  Furthermore, when producing the first semiconductor device with a laminated structure of a semiconductor chip and an interposer, a mounting method for arranging a plurality of minute metal blocks on the semiconductor chip and the semiconductor interposer and obtaining electrical connection by joining them As a result of the adoption, a reduction in the height of the first semiconductor device itself was achieved. According to such a mounting method, the space required for the bonding wire for electrical connection becomes unnecessary, and further, the height can be further reduced as compared with the case of mounting with the conventional “single metal lump”. It became possible to plan.

  By adopting a silicon semiconductor having high mechanical strength as the material of the interposer, the thickness of the interposer portion can be reduced and a further reduction in height can be realized as compared with the resin interposer that has been widely used. When mechanical stress is applied to the interposer, it is known that the amount of deformation (for example, the amount of bending) is proportional to the Young's modulus (one index representing the mechanical strength) of the material. The Young's modulus of semiconductor silicon is 130 GPa, while the Young's modulus of the resin material varies greatly depending on the type and grade of the resin, but is about 10 to 800 MPa. That is, semiconductor silicon is 100 times or more stronger than resin. For this reason, sufficient mechanical strength was obtained even when the thickness of the interposer was 100 micrometers or less. Furthermore, semiconductor interposers are created using integrated circuit technology (resin interposers are often created using printed circuit board technology), so the wiring pattern on the surface of the interposer is miniaturized or laminated with multiple wiring layers. Also became possible.

  By partially thinning the semiconductor interposer, the height of the stacked structure could be reduced when multiple semiconductor devices were stacked. That is, in a configuration in which two semiconductor devices are stacked one above the other, a semiconductor chip that constitutes the lower semiconductor device enters the recess of the semiconductor interposer of the upper semiconductor device (the thickness of the interposer is small). It will be. As a result, a mounting method that contributes to a reduction in height was obtained.

  Furthermore, by removing the central region of the semiconductor interposer and providing an opening shape, the height can be further reduced as compared with the case described in the previous paragraph. Further, since the heat dissipation mechanism can be brought into direct contact with the back surface of the semiconductor chip, the heat dissipation effect can be greatly increased.

It is a figure which shows mounting of a semiconductor device. <Example 1> It is a figure explaining paying attention to a metal lump. It is a figure explaining the shape of a metal lump. It is a figure explaining the positional relationship of a semiconductor device. It is a figure explaining electrical connection becoming easy by the magnitude | size of a metal lump. <Example 2> It is a figure explaining that electrical connection becomes easy by arrangement | positioning of a metal lump. <Example 3> It is a figure explaining the shape and arrangement | positioning of a metal lump. <Shape and Arrangement of Metal Mass-1> <Example 4> It is a figure explaining the shape and arrangement | positioning of a metal lump. <Shape and Arrangement of Metal Mass-2> <Example 5> It is a figure explaining the shape and arrangement | positioning of a metal lump. <Shape and Arrangement of Metal Mass-3> <Example 6> It is a figure which shows mounting of a semiconductor device. <Semiconductor Device Mounting-1> <Example 7> It is a manufacturing flow of semiconductor device mounting. <Semiconductor Device Mounting-2> <Example 8> It is a figure explaining creation of a metal lump and a conductive path. <Method for Forming Conductive Path> <Example 9> It is the figure which comprised the semiconductor device in multiple stages. <Example 10> It is a figure explaining the connection of a semiconductor chip and an interposer. <Application to Electrical Connection of Semiconductor Chip and Interposer> <Example 11> It is a figure explaining the shape of a semiconductor interposer. <Shape of Semiconductor Interposer-1> <Example 12> It is a figure explaining the shape of a semiconductor interposer. <Shape of Semiconductor Interposer-2> <Example 13> FIG. 17 is a manufacturing flow for mounting the semiconductor device shown in FIG. 16; FIG. <Semiconductor Device Mounting-3> <Example 14> It is a figure which shows the structure with a large heat dissipation effect. <Semiconductor Device Mounting-4> <Example 15> It is a lamination example of a semiconductor device. <Conventional example>

  Hereinafter, an interposer according to the present invention shown in the drawings will be described in detail.

  FIG. 1 is a diagram showing mounting of a semiconductor device, which is Embodiment 1 of the present invention. In FIG. 1A, 10 is a first semiconductor device, 11 is a first main surface of 10, 12 is a first conductor disposed on 11, and 13 is a first metal disposed on 12. It is a lump. In FIG. 4A, at least two first conductors 12 are arranged, and for convenience of explanation, only one is shown. Moreover, although the example in which the four metal lumps 13 are arrange | positioned is shown by the figure (a), about the number should just be at least two. 15 is a second semiconductor device or wiring substrate, 16 is a second main surface of 15, 17 is a second conductor disposed on 16, and 18 is a second metal block disposed on 17. Reference numeral 17 denotes at least two second conductors, and only one is shown for convenience of explanation. Moreover, although the example in which four metal blocks 18 are arranged is shown in FIG. 5A, the number of the metal blocks 18 may be at least two. The metal lumps 13 and 18 are made of solder, gold-tin eutectic, or the like, and it is desirable that the size and the arrangement pitch are the same, but the present invention is not limited to this. FIG. 2A shows a state in which the metal blocks (13 and 18) are arranged to oppose each other before 10 and 15 are electrically connected. From this state, 10 and 15 are moved in the vertical direction in the figure, and the mutual positional relationship is set so that they are in mechanical contact with each other. Furthermore, by heat-treating 10 and 15 which are in mechanical contact in a high temperature atmosphere, 13 and 18 are melted and re-solidified to be integrated to form a conductive path 20. FIG. 2B shows 10 and 15 in an integrated state.

  FIG.1 (c) to FIG.1 (e) is a figure explaining the melting condition of the above-mentioned metal lump. In these drawings, only a single metal block 22 arranged at 10 and a single metal block 23 arranged at 15 are shown for convenience of explanation. FIG. 4C shows a case where both of these metal blocks are hemispheres having a radius r. Assuming a hemisphere, the height of each metal block is r, and a circle having a diameter of 2r is in contact with the first and second conductors. The sum of the volumes of the respective hemispherical metal blocks is (4π / 3) · r ^ 3. That is, the sum of the volumes of the two hemispheres is equal to the volume of the virtual whole sphere. Here, the notation “r ^ 3” represents “r to the third power”. Next, as shown in FIG. 6D, it is assumed that the two metal blocks are melted and re-solidified to change to a single cylindrical shape and the conductive path 24 is formed. The bottom of this cylinder is a circle with a diameter of 2r. Moreover, if it assumes that the total volume of a metal lump does not change even if it fuse | melts, the height of a cylinder will be 4r / 3. However, since the surface tension works when it is melted and re-solidified, the conductive path 25 has a “via barrel” shape as illustrated in FIG. As a result, the height b of the via barrel becomes a value smaller than 4r / 3. The detailed value of the height b shown in FIG. 5E depends on the surface tension and the force pressing 10 and 15 in the heat treatment process, but can be assumed to be approximately equal to r. According to such analysis, “when two hemispherical metal blocks each having the same size are brought into contact with each other and melted and re-solidified by heat treatment, the shape of a via barrel having a height approximately equal to the radius of the metal block It became clear that they are electrically connected by a conductive path. In the description in this paragraph, it is assumed that 22 and 23 are made of the same material, and that melting and re-solidification occur at substantially the same timing. However, in this embodiment, the present invention is not limited to this, and 22 and 23 may be different materials, for example, 22 may be a combination of high temperature solder and 23 may be a low temperature solder. Moreover, there is no restriction | limiting also regarding the force which presses said 10 and 15 mutually. Generally, it is experimentally determined by the number of conductors 12 and 17, the area, etc., but is not limited thereto. Further, the first semiconductor device 10 may be placed on the second semiconductor device or the wiring substrate 15 and a force for pressing with the weight of the 10 may be generated.

  FIG. 2 is a diagram for explaining the difference between the first embodiment and the conventional example, paying attention to the size of the metal block, and the same numbers as those in FIG. 1 indicate the same components. FIGS. 9A and 9B show a conventional example, and FIGS. 9C and 9D show an embodiment according to the present invention. FIGS. 7A and 7C are plan views showing a state in which a metal block for electrically connecting two semiconductor devices is arranged, and FIGS. 2B and 2D are two views. The state where the semiconductor device is electrically connected is shown as a cross-sectional view. In FIG. 2A, reference numeral 30 denotes a semiconductor device, and reference numeral 31 denotes a lower surface (corresponding to a first main surface) of the semiconductor device. Reference numeral 32 denotes a metal block for electrical connection, and FIG. 1A illustrates a case where the diameter of the metal block is 250 micrometers and the arrangement pitch is 500 micrometers. FIG. 2B shows a state in which the two semiconductor devices 30 and 35 are electrically connected using the structure illustrated in FIG. As described above, since the height of the conductive path formed by melting and re-solidifying the metal lump is approximately equal to the radius of the metal lump, FIG. . As is clear from the sectional view of FIG. 2B, which is a conventional example, in the configuration of FIG. 2A, “one“ large ”metal lump is arranged on the surface of the first conductor. The conductive path is realized by one “large” metal lump ”. On the other hand, in the embodiment according to the present invention shown in FIG. 5C, a plurality of “small” metal blocks are arranged in place of the above “large” metal blocks. FIG. 4C is an enlarged view of a part (indicated by a circle) of FIG. In FIG. 3C, a large number of the first metal masses 13 are arranged on the surface of the first conductor 12, more specifically, in a circle having a diameter of 250 micrometers. The size (diameter) of the 13 is approximately 10 micrometers, and the minimum value is approximately 5 micrometers. FIG. 2D shows a state where the first semiconductor device 10 and the second semiconductor device 15 are electrically connected in such a configuration. Note that FIG. 6D corresponds to an enlarged portion of the circle in FIG. As described above, when the diameter of the 13 is 10 micrometers, the height of the conductive path that electrically connects the first semiconductor device and the second semiconductor device is approximately 5 micrometers. As a result, it is possible to overcome the limitation of low profile, which was a problem in the prior art. In this paragraph, the above 15 and 35 are assumed to be semiconductor devices, but the 15 and 35 may be printed circuit boards or the like.

In the previous paragraph, it was described that Example 1 according to the present invention is different from the conventional example. In other words, conventional example: a single “large” metal block is placed on a conductor provided in a semiconductor device,
The conductive path is formed by the metal block.
Example 1: A plurality of “small” metal blocks are arranged on a conductor provided in a semiconductor device, and the conductive path is formed by the plurality of metal blocks.
That is the difference.

  FIG. 3 is a view for explaining the shape of the first metal block, in which the same reference numerals as those in FIG. 1 denote the same components. For convenience of explanation, the figure is shown upside down. In FIG. 2A, reference numeral 40 denotes a mask layer made of a resin film or the like laminated on the surface of the first conductor 12, and a part of the 12 regions, that is, the first metal block is not arranged. Covers the area. The mask layer is used when the first metal block 41 is formed. In particular, the metal lump is prevented from spreading laterally in the process of melting and resolidifying the metal lump. In order to prevent this, it is necessary that the surface of the mask layer be “water-repellent” (in a stricter expression, “low wettability”) in a state where the first metal block is melted. In FIGS. 4A, 4B, and 4C, reference numerals 41, 42, and 43 denote first metal blocks having different shapes. Reference numeral 41 denotes a shape close to a sphere, and 42 denotes a hemispherical shape. Shows the case of a flatter shape than the hemisphere. Up to the previous paragraph, the shape of 42 is described. However, depending on the manufacturing conditions of the first metal lump, the shape is 41 to 43. That is, the shape of the first metal mass is determined by the volume (or amount) of the metal mass when the first metal mass is arranged. Which of the shapes illustrated in FIG. 6A to FIG. 5B is the optimum shape is determined by the above-described melting and re-solidification conditions, and can be said to be a design factor. Moreover, although the said 1st metal lump similar to hemisphere was described in this paragraph, shapes other than this, for example, the shape which touches the said 1st conductor, may be a polygon containing a square. For example, when the shape is a square, the three-dimensional shape of the first metal block is a “pyramid shape with rounded tops and ridges”. Furthermore, in this paragraph, the first metal block has been described, but the same description can be applied to the second metal block.

  FIG. 4 is a view for explaining the positional relationship between the first semiconductor device and the second semiconductor device or the wiring board. The same reference numerals as those in FIG. 1 denote the same components. In the figure, the first metal lump 13 provided on the first semiconductor device 10 and the second metal lump 18 provided on the second semiconductor device or the wiring board 15 have the same shape. (Hemisphere in the figure), the same number (five in the figure each), and the same arrangement pitch. FIG. 6A shows a case where the first metal block 13 and the second metal block 18 are opposed to each other with the same “spatial phase”. In such a case, 10 and 15 are brought into contact with each other, and the upper and lower metal blocks facing each other form the conductive path by the melting and re-solidification described above. FIG. 4B shows a case where the “spatial phase” of the above-described 13 and 18 are opposed to each other with a deviation. In such a case, the upper and lower metal lumps are displaced, but are in contact with each other. Therefore, the melting and re-solidification described above occur, and the conductive path can be formed. FIG. 2C shows a case where the “spatial phase” of the above-mentioned 13 and 18 is opposed by one pitch. Even in such a case, since the upper and lower metal blocks can be in contact with each other in a shifted state, the conductive path can be formed. However, in such a case, each of the five metal blocks is arranged, but only four of them can contribute to the formation of the conductive path. On the other hand, in the case shown in FIG. 4D, since the size of the first metal block 51 and the second metal block 52 (diameter of the hemisphere) is small, depending on the value of the “spatial phase” described above, There are cases where the opposing metal mass cannot contact. In such a case, electrical connection between the first semiconductor device and the second semiconductor device or the wiring board cannot be achieved. That is, the electrical connection cannot be achieved depending on the size of the metal block and the “spatial phase”.

<The size of the metal lump>
FIG. 5 is a diagram for explaining a second embodiment that avoids the inconvenience of not achieving the electrical connection described in the previous paragraph. In the figure, the same reference numerals as those in FIG. 1 denote the same components. 4A, as in FIG. 4A, the “spatial phase” coincides, that is, the first metal block 13 and the second metal block 18 all face each other. This is a case where the spatial positions of the top vertices of the chunk are coincident. FIG. 5B shows a case where the “spatial phase” is shifted by 180 degrees, that is, the arrangement of the second metal blocks is shifted by a half pitch with respect to the arrangement of the first metal blocks. Is the case. It can be said that the 180 degree shift of the “spatial phase” is the maximum phase shift state. Assume that the distance between the first semiconductor device 10 and the second semiconductor device or the wiring substrate 15 is close to the case shown in FIG. Here, it is assumed that the arrangement of 13 and 18 is one-dimensional, that is, the above-described metal blocks are arranged in a line. Next, (1) the top of the first metal block 13 (which is the lowest point in the figure) is in contact with the surface of the first conductor 12 on the second main surface 17, and (2 ) The top of the second metal block 18 (which is the highest point in the figure) is in contact with the surface of the second conductor 17 on the first main surface, and (3) the first metal block is It is assumed that 13 and the second metal block 18 are in contact with each other (which is a curved surface). A plan view of this state is shown in FIG. 2C, and a cross-sectional view is shown in FIG. FIG. 2C shows one of the first metal blocks (indicated by 61 in the figure) and two of the second metal blocks (indicated by 62 in the figure). However, the diameter of these three metal blocks assuming a hemispherical shape is d1, and the arrangement pitch is p. Further, a sectional view taken along the line AA 'in FIG. 4C is shown in FIG. That is, FIG. 4D shows the positional relationship of the metal blocks under the conditions described in (1) to (3) above. From FIG. 4D, it is derived that the relationship between the diameter d1 of the first metal block and the second metal block and the arrangement pitch p is d1 / p = 1 / √3 = 0.58. . This relationship is a case where the metal blocks are arranged one-dimensionally. If the metal lumps are arranged two-dimensionally as shown in FIG. 5E, the relationship between the diameter d2 of the first metal lumps and the second metal lumps and the arrangement pitch p is d2. It is derived that /p=√2/√3=0.82. Note that the cross-sectional structure taken along the line BB ′ in FIG. 9E is the same as that in FIG.

  In the preceding paragraph, the first semiconductor device and the second metal mass are set to have a constant relationship between the diameter d1 (or d2) and the arrangement pitch p of the first metal mass and the second metal mass. The first metal block and the second metal block can be in contact with each other even if the positional relationship with the semiconductor device or the wiring board is shifted (even if the “spatial phase” is 180 degrees). It has been shown that the conductive path can be formed. In the conventional example, each of the first metal block and the second metal block is brought into contact with each other to form the conductive path. For this reason, when the diameters of these metal blocks are reduced, it is necessary to correctly align the positions of the first semiconductor device and the second semiconductor device or the wiring board, and include fine position adjustment. There was a problem that the assembly process was essential. However, in this embodiment, fine position adjustment is not required, and the conductive path can be reliably formed even in rough alignment, and the effect of this embodiment is great.

  In the above paragraph, the case where the metal block has a hemispherical shape is described. If the bottom surfaces of the first metal block and the second metal block are not circular but are polygons including a square, the diameters d1 and d2 described above are the diameters of the inscribed circles of the polygons. It is obvious that the same numerical relationship can be obtained by setting the above-described arrangement pitch as the polygon arrangement pitch. As described above, in order to realize the structure illustrated in FIG. 5D, the size of the bottom surfaces of the first metal block and the second metal block (denoted as d) is set to the metal block. The condition is that the value exceeds 58% of the arrangement pitch p.

<Arrangement of metal lump>
FIG. 6 is a third embodiment of the present invention and is a diagram for explaining that the electrical connection is facilitated by the arrangement of the metal blocks. In the figure, the same reference numerals as those in FIG. 5 denote the same components. This embodiment is characterized in that the first metal block and the second metal block are arranged in a “staggered arrangement”. In FIG. 7A, reference numerals 71 and 72 denote the first metal block and the second metal block, respectively, which are arranged at a pitch p in the vertical and horizontal directions. In addition, the lines are arranged in a state shifted by p / 2 for each line of each arrangement (in a “staggered arrangement” form). In Example 3, the first metal block and the second metal block have a circular shape in contact with the first conductor and the second conductor, respectively, and the diameter thereof is The case of d3 is shown. The contact state of the first metal block and the second metal block at d3 / p = 1/3 = 0.33 in this arrangement is shown in FIG. FIG. 2B is a structural cross-sectional view taken along the line CC ′ of FIG. 2A, and shows that the respective metal blocks are in contact with each other in a three-dimensional space. That is, by setting d3 / p to 33% or more, the conductive path can be reliably formed even with rough alignment.

<Shape and arrangement of metal lump-1>
FIG. 7 is a diagram for explaining the shape and arrangement of a metal lump, which is Embodiment 4 of the present invention. In this paragraph, “the shape in which the first metal block and the second metal block are in contact with the first conductor and the second conductor, respectively” is simply described as “shape”. In the figure,
(A): The shape is an ellipse, and the metal block is arranged at the intersection of the mesh of the “Grilled net”. FIG. (B): The shape is an ellipse, and the metal block is arranged in a “staggered arrangement” shape. (C): The shape is an oval, and the metal block is arranged at the intersection of the mesh of the “Makiyaki net”. (D): The shape is an oval, and the metal block is arranged in a “staggered arrangement” shape. Each case is shown.
In FIG. 8A, reference numerals 81 and 82 denote the first metal block and the second metal block, respectively. Reference numerals 83 and 84 denote the major axis directions of the respective ellipses. As an example, a case where the major axes intersect at right angles is shown. On the other hand, in the same figure (b), the metal lump is arrange | positioned at zigzag arrangement | positioning, and each major axis cross | intersects at right angle. In FIG. 8C, 85 and 86 are the first metal block and the second metal block, respectively, and the shapes are both oval. Moreover, 87 and 88 have shown the major axis direction of each ellipse, and the case where the major axis cross | intersects at right angle is shown as an example. In the same figure (d), the said 1st metal lump and said 2nd metal lump which are oval are arrange | positioned at zigzag arrangement | positioning, and each major axis cross | intersects at right angle. Although FIG. 7 shows a case where the major axes intersect at right angles, the intersecting angle is not limited to a right angle. In addition, the shape (for example, the major axis) and the arrangement pitch in this embodiment are not particularly limited, and can be appropriately selected so that the conductive path can be reliably formed even in rough alignment. It is.

<Shape and arrangement of metal lump-2>
FIG. 8 is a diagram for explaining the shape and arrangement of a metal lump, which is Embodiment 5 of the present invention. In this paragraph, “the shape in which the first metal block and the second metal block are in contact with the first conductor and the second conductor, respectively” is simply described as “shape”. In the figure,
Figure (a): When the shape is rectangular and the metal lump is arranged at the intersection of the “Makiyaki net”. Figure (b): When the shape is rectangular and the metal lump is arranged in a “staggered arrangement” shape. Are shown respectively.
In FIG. 9A, reference numerals 91 and 92 denote the first metal block and the second metal block, respectively. Reference numerals 93 and 94 denote the longitudinal directions of the respective rectangles. As an example, the case where the longitudinal directions intersect at right angles is shown. On the other hand, in the same figure (b), the metal lump is arrange | positioned at zigzag arrangement | positioning, and each longitudinal direction cross | intersects at right angle. Although FIG. 8 shows a case where the longitudinal directions intersect at right angles, the intersecting angle is not limited to a right angle. Further, the shape (for example, the size in the longitudinal direction) and the size of the arrangement pitch in this embodiment are not particularly limited, and can be appropriately selected so that the conductive path can be reliably formed even with rough alignment. Is possible.

<Shape and arrangement of metal lump-3>
FIG. 9 is a diagram for explaining the shape and arrangement of a metal lump, which is Embodiment 6 of the present invention. In FIG. 4A, reference numerals 100 and 101 denote the first metal block and the second metal block, respectively, which are arranged in a thin stripe shape. Reference numerals 102 and 103 denote the directions of the respective stripes. FIG. 4A shows a case where the stripes intersect at right angles. On the other hand, in FIG. 5B, reference numerals 104 and 105 denote the first metal block and the second metal block, respectively, which are arranged in a thin stripe shape. Reference numerals 106 and 107 denote the directions of the respective stripes. FIG. 2B shows a case where the angle at which the stripes intersect is not a right angle. In this embodiment, there is no restriction on the angle at which the stripes intersect. Further, the shape of the metal block (stripe width, etc.) and the size of the arrangement pitch are not particularly limited, and can be appropriately selected so that the conductive path can be reliably formed even with rough alignment. Furthermore, in the present embodiment, the metal lump has a stripe shape, so that the above-described alignment is easier.

  In Example 6, in the state where a set of stripes (first metal block and second metal block) is electrically connected, the stripes are arranged in a mesh shape. This mesh forms a sealed space. If air is sealed in this space, the air expands as the operating temperature rises, generating a force that breaks the electrical connection of the stripes. To do. On the other hand, if the stripes are electrically connected in a vacuum, the expansion effect does not occur, and the reliability of the electrical connection can be increased. Furthermore, since the stripes are always pressed at atmospheric pressure in a state where the vacuum is sealed, the reliability of the electrical connection can be further increased.

<Mounting of semiconductor device-1>
FIG. 10 is a seventh embodiment of the present invention, and shows a cross-sectional view of a structure in which a first semiconductor device is stacked on a second semiconductor device. FIG. 4A is a cross-sectional view of the laminated structure, and FIG. 4B is an enlarged view of a portion indicated by a circle in FIG. As shown in FIG. 4B, in this embodiment, the first semiconductor device is stacked to form the first semiconductor device, and the above-described embodiment 1 (a conductive path is formed by a plurality of “small” metal blocks). Yes. In the present embodiment, as the “semiconductor device”, a structure including a semiconductor chip and an interposer is illustrated. In FIG. 1A, reference numeral 110 denotes a first semiconductor device, which includes a first semiconductor chip 111 and a first interposer 112. Reference numeral 115 denotes a second semiconductor device, which includes a second semiconductor chip 116 and a second interposer 117. The interposers 112 and 117 are preferably made of a semiconductor having a mechanical strength higher than that of the resin material as described above, but this is not restrictive. When the interposer is made of a semiconductor material (for example, silicon), the thickness of the interposer can be reduced to a thickness of about 200 micrometers or less. As shown in the enlarged view in FIG. 5B, the 110 and 115 are described in detail in Example 1. “A plurality of“ small ”metal blocks are arranged on a conductor provided in a semiconductor device. The above-mentioned conductive path is formed by a metal lump. In FIG. 2B, reference numeral 113 denotes the first conductor provided on the first main surface (which is the lower surface in the drawing) of the first interposer 112. Reference numeral 118 denotes the second conductor provided on the second main surface (the upper surface in the figure) of the second interposer 117. The 113 and 118 are electrically connected by a conductive path 119. As described above, the 119 is formed by melting and resolidifying at least two metal blocks provided on the surfaces 113 and 118 in a high temperature atmosphere. In such a configuration, the first semiconductor device and the second semiconductor device are mechanically and electrically connected to each other and have a laminated structure. The laminated structure is electrically connected to an external circuit (not shown) made of a printed circuit board or the like by a conductive ball 120 provided on the lower surface of the second interposer 117. In FIG. 5A, the conductive ball 120 is illustrated as a single “large” shape. However, in this portion, the “conductive formed from a plurality of“ small ”metal blocks” described in the first embodiment is also used. “Road” may be adopted.

  In FIG. 10A, the interposer 112 is not uniform in thickness, but is partially thinned as indicated by 121. That is, 121 is formed corresponding to a region occupied by the semiconductor chip 116 constituting the second semiconductor device. In more general terms, “the thickness of the interposer in a specified region (region corresponding to the second semiconductor chip) in the region where the first semiconductor chip is mounted is defined as “Do not exceed the thickness of the interposer in the region where the conductor and the first metal mass are disposed”. With this configuration, it is possible to reduce (that is, reduce the height) the height of the stacked structure (indicated as “h” in FIG. 5A). In the seventh embodiment, the above-described two semiconductor devices are stacked using “conductive paths formed from a plurality of“ small ”metal blocks”, and the interposer is partially reduced in thickness. Has achieved a low profile.

<Semiconductor device mounting-2>
FIG. 11 shows an eighth embodiment of the present invention, and shows a manufacturing flow for realizing the configuration shown in FIG. In the figure, the same reference numerals as those in FIG. 10 denote the same components. In this embodiment, the interposer is described as a semiconductor interposer. FIG. 6A is a cross-sectional view showing the structure of an interposer (corresponding to 112 in FIG. 10) constituting the first semiconductor device. In FIG. 4A, reference numeral 124 denotes a first semiconductor substrate constituting the first interposer, 125 denotes a first main surface (lower surface in the drawing) of the interposer, and 126 denotes the first interposer. This is the second main surface (the upper surface in the figure). The first conductor 113 is provided on the surface of the first main surface 125, and the wiring conductor 127 is provided on the surface of the second main surface 126. The 113 and the 127 are connected to the through electrode 128. Are connected in the thickness direction (vertical direction in the figure) of the first semiconductor substrate. In the figure, a structure for electrically insulating the through electrode 128 from the first semiconductor substrate 124 is omitted. Further, the first semiconductor substrate 124 is provided with a thin region 121 shown in FIG. The 121 is easily manufactured by a known semiconductor process technique such as anisotropic etching. FIG. 2B is a diagram in which the first semiconductor chip 111 is mounted on the surface of the second main surface of the first interposer 112. Reference numeral 130 denotes connection means for connecting the connection terminal of the first semiconductor chip to the wiring conductor 127, and is, for example, a ball grid array. In addition to this, a known wire bonding may be used as the connection means. A resin layer 131 called an underfill is provided to increase the mechanical strength of the connection means after the first semiconductor chip 111 is mounted by the connection means 130. The underfill functions to absorb expansion due to heat generation in the first semiconductor chip 111 and to dissipate the heat generation to the first interposer side. In order to improve the heat dissipation effect, a resin constituting the underfill may be poured in vacuum so that air bubbles are not generated in the underfill. In FIG. 4B, reference numeral 13 denotes the first metal block provided on the surface of the first conductor 113. In the figure, it is illustrated that three first metal blocks are arranged on the surface of each first conductor. The structure shown in FIG. 4B is the structure of the first semiconductor device.

  FIG. 11C is a sectional view showing a structure of an interposer (corresponding to 115 in FIG. 10) constituting the second semiconductor device. In FIG. 2C, 132 is a second semiconductor substrate constituting the second interposer, 135 is a first main surface (lower surface in the figure) of the second interposer, and 136 is the second semiconductor substrate. This is a second main surface (upper surface in the figure) of the interposer. The second conductor 118 is provided on the surface of the second main surface 136, and the external connection conductor 133 is provided on the surface of the first main surface 135. The 118 and 133 are formed as through electrodes. 138 is connected in the thickness direction (vertical direction in the figure) of the second semiconductor substrate. In the figure, the structure for electrically insulating the through electrode 138 from the second semiconductor substrate 132 is omitted. Further, the second conductor 118 also serves as a wiring conductor in the second interposer, like the wiring conductor 127 described above. FIG. 4D is a diagram in which the second semiconductor chip 116 is mounted on the surface of the second main surface of the second interposer 117. Reference numeral 140 denotes connection means for connecting the connection terminal of the second semiconductor chip to the second conductor 118 also serving as the wiring conductor, and is, for example, a ball grid array. In addition to this, a known wire bonding may be used as the connection means. Reference numeral 141 denotes a resin layer called an underfill, which is provided to increase the mechanical strength of the connecting means after the second semiconductor chip 116 is mounted by the connecting means 140. The underfill functions to absorb expansion due to heat generation in the second semiconductor chip 116 and to dissipate heat generation to the second interposer side. In order to improve the heat dissipation effect, a resin constituting the underfill may be poured in vacuum so that air bubbles are not generated in the underfill. In FIG. 4D, reference numeral 18 denotes the second metal block provided on the surface of the second conductor 118. In the figure, it is illustrated that three second metal blocks are arranged on the surface of each second conductor. In FIG. 4D, a conductive ball 120 is disposed on the surface of the external connection conductor 133 and is used for electrical connection with an external circuit (not shown) made of a printed circuit board or the like. The structure shown in FIG. 4D is the structure of the second semiconductor device.

  FIG. 11E shows a cross-sectional structure in which the first semiconductor device in FIG. 11B is stacked and mounted on the second semiconductor device in FIG. In FIG. 4E, reference numeral 143 denotes a conductive path, which is formed by facing the first metal block 13 and the second metal block 18 and melting and resolidifying them by heat treatment in a high temperature atmosphere. Yes. In order to increase the mechanical connection strength of the conductive path, a resin layer may be poured into a region of the conductive path to form an underfill. In addition, the resin layer may flow not only in the region of the conductive path but also in a region between the first interposer and the second interposer. As shown in FIG. 5E, the upper side of the second semiconductor chip is in a form that enters the region (121) where the thickness of the first interposer is thin. The digging depth of 121 described above (the thickness of the peripheral portion of the first interposer, i.e., the region where the first conductor is present, and the thickness of the region into which the second semiconductor chip enters) The difference is determined by (1) the thickness of the second semiconductor chip, (2) the thickness of the connection means 140, and (3) the thickness of the conductive path 143. Furthermore, a gap (indicated by 144) between the lower surface of the region where the thickness of the first interposer is thin and the upper surface of the second semiconductor chip is filled with a resin having a high thermal conductivity, A configuration in which heat generated by the first semiconductor chip and the second semiconductor chip is dissipated is also possible.

  In Example 8, the case where the first semiconductor device and the second semiconductor device are composed of a semiconductor chip and a semiconductor interposer was shown. In this configuration, the first main surface of the first semiconductor device is the same as the first main surface of the first interposer, and similarly, the second main surface of the second semiconductor device. Is the same as the second main surface of the second interposer.

  In the eighth embodiment described in detail with reference to FIG. 11, the case where the second semiconductor device is constituted by the second semiconductor chip and the second interposer was shown. However, in Example 8, a wiring board such as a printed board or a printed board on which a semiconductor chip is mounted may be employed as an alternative to the second semiconductor device.

<Method for forming conductive path>
FIG. 12 is a diagram for explaining a manufacturing process for forming a conductive path by forming the first metal block and the second metal block according to the ninth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 11 denote the same components. FIGS. 12A to 12D are partial views of the first interposer, and are drawn upside down for convenience of explanation. In FIG. 12A, reference numeral 124 denotes a first semiconductor substrate constituting the first interposer, and 113 denotes the first conductor. The 113 is formed on the surface of the first main surface 124 by a known method such as vapor deposition and patterning via an oxide film (not shown). The structure 113 includes a structure in which copper or the like is laminated on a titanium foil film. In FIG. 2B, reference numeral 150 denotes an insulating layer made of an oxide film or a resin, and the insulating layer deposited or applied is patterned. In FIG. 5C, reference numeral 151 denotes a metal layer, which is a base material that becomes the first metal mass after the subsequent process. The 151 is formed on the surface of the first main surface 124 by vapor deposition or coating, and then patterned. As the material of the 151, solder (preferably lead-free solder), gold-tin alloy, or the like is selected. In FIG. 4D, reference numeral 13 denotes the first metal block that has been melted and re-solidified by treating the 151 in a high temperature atmosphere. Reference numeral 152 denotes the first interposer created by the above process. As is apparent from the above process, the insulating layer 150 serves to prevent a plurality of the first metal masses 13 from being combined with each other in the melting and resolidification process to become a “large” metal mass. There is. For this reason, it is preferable that the surface of 150 has “low wettability” with respect to the molten metal layer 151.

  In FIG. 12 (e), 153 is the second interposer created by the same manufacturing process as 152, and is opposite to 152 (shown upside down from FIG. 12 (d)). Are in contact with each other. In FIG. 9E, the “spatial phase” of 152 and 153 coincide with each other, that is, in an ideal state. However, even if this “spatial phase” is deviated, this “spatial phase” can be ignored as long as the first metal block and the second metal block can contact each other. In the above paragraph, the metal block and the arrangement pitch have been described. If the above-described certain relationship (for example, d1 / p> 1 / √3 = 0.58) is satisfied, the “spatial phase” is described. "Can be ignored.

  FIG. 12F shows a state in which the first metal lump 13 and the second metal lump 18 are melted and re-solidified to form a conductive path 119. FIG. 4G shows a state where the resin layer 154 is filled around the conductive path 119. The resin layer 154 is filled only in the region of the first conductor and the second conductor. The resin layer 154 serves to reinforce the adhesive strength of the conductive path and at the same time increase the thermal conductivity between the first interposer and the second interposer. In order to further increase the thermal conductivity, it is important that the resin layer does not contain air bubbles. For this purpose, a technique such as filling the resin in a vacuum is adopted. The FIG. 12H shows a case where the resin layer 155 is filled over the entire surfaces of the first interposer and the second interposer. In such a case, there is an advantage that the adhesive strength of the conductive path can be further increased as compared with the case of FIG.

<Multi-stage configuration>
FIG. 13 shows a tenth embodiment of the present invention, in which a semiconductor device composed of a semiconductor chip and a semiconductor interposer is configured in multiple stages. FIG. 4A shows a case where a three-layered structure is formed with a third semiconductor device 160 sandwiched between the first semiconductor device 110 and the second semiconductor device 115. FIG. 2B shows a case where a laminated structure composed of the first semiconductor device 110 and the second semiconductor device 115 is mounted on a wiring board 161. In the present embodiment, the above-described present invention is not only mounted on the second semiconductor device but also the multi-stage (in FIG. 13B, multi-stage including the wiring board). It can be easily expanded to a laminated structure of For the electrical connection between these semiconductor devices or wiring boards, as described in the preceding paragraph, “a plurality of“ small ”metal blocks are arranged on a conductor provided in a semiconductor device, and the plurality of metal blocks” The mounting method of “forming the conductive path” is adopted. As a result, (1) low profile due to the adoption of a semiconductor interposer with high mechanical strength, (2) low profile due to conductive paths generated from multiple “small” metal blocks, and (3) mounting without wire bonding. Low profile is achieved.

<Application to electrical connection between semiconductor chip and interposer>
FIG. 14 shows an embodiment 11 of the present invention, which is an example in which the semiconductor chip is applied to the interposer. In the figure, the same reference numerals as those in FIG. 10 denote the same components. In FIG. 2A, the first semiconductor chip 111 is mounted on the upper side of the first interposer 112 in a flip chip configuration. In the flip-chip configuration, as shown in the enlarged view in FIG. 4B, the feature of the present invention is that “a plurality of“ small ”metal lumps are arranged on a conductor, and a conductive path is formed by the plurality of metal lumps. It is configured to form. Specifically, a pad 170 region for electrical connection disposed on the lower surface of the first semiconductor chip 111 and an electrical connection disposed on the upper surface of the first interposer 112. At least two conductive paths are formed between the wiring conductor regions 171. By adopting such a configuration, as compared with the conventional example in which the first semiconductor chip and the first interposer are electrically connected by wire bonding, a space for bonding wires becomes unnecessary, and the first Thus, a reduction in the height of one semiconductor device 110 can be realized.

In addition, in a present Example, the naming (code | symbol) of a component is different from the other Example described in this specification. In the following, naming correspondence is described using the present Example 11 (FIG. 14) and the Example 7 (FIG. 10).
In Example 11 (FIG. 14),
(1) The semiconductor chip 111 is mounted on the upper side of the interposer 112. That is, the feature of the present invention is that “a plurality of“ small ”metal blocks are arranged on a conductor and a conductive path is formed by the plurality of metal blocks” is an upper surface of the interposer 112, and This is also the lower surface of the semiconductor chip 111.
(2) Therefore, the “first conductor” and the “first metal block” are arranged on the lower surface of the semiconductor chip 111. Further, the “second conductor” and the “second metal block” are arranged on the upper surface of the interposer 112.
(3) That is, the “second conductor” and the “second metal lump” are arranged above the interposer 112 (which is the “second main surface”).
On the other hand, in Example 7 (FIG. 10),
(1) The semiconductor device 110 composed of the semiconductor chip 111 and the interposer 112 is mounted on the upper side of the semiconductor device (or wiring board) 115. That is, the feature of the present invention is that “a plurality of“ small ”metal blocks are arranged on a conductor and a conductive path is formed by the plurality of metal blocks” is a lower surface of the interposer 112, and It is also the upper surface of the 115.
(2) For this reason, the “first conductor” and “first metal block” are arranged on the lower surface of the interposer 112. The “second conductor” and “second metal block” are arranged on the upper surface of the 115.
(3) That is, the “first conductor” and the “first metal block” are arranged below the interposer 112 (which is the “first main surface”).
As described above, when attention is paid to the “interposer”, the location and naming of the “main surface”, “conductor”, and “metal lump” are different between the eleventh embodiment and the seventh embodiment. become.

  In FIG. 14A, a resin layer 155 as an underfill is filled between the first semiconductor chip and the first interposer to increase the adhesive strength. 14C is similar to the configuration of FIG. 14A, but as shown in enlarged view in FIG. 14D, the resin layer 154 as an underfill is limited to the pad 170 region only. Filled.

<Shape of semiconductor interposer-1>
FIG. 15 is a twelfth embodiment of the present invention and shows the shape of the semiconductor interposer described above. In the figure, the same reference numerals as those in FIG. 14 denote the same components. In the figure, the thickness of the first interposer 112 is not uniform, the thickness of the region where the first semiconductor chip 111 is mounted is thin, and a recess 180 is formed. It is. The depression is formed using anisotropic etching or the like. The wiring conductor is provided along a step from a region where the thickness of the first interposer is large to a region where the thickness is small. An example of such a wiring conductor is indicated by 181. Also in this embodiment, since the first semiconductor chip is “dropped” and mounted on a part of the surface region of the first interposer, it is effective in reducing the height. In order to reduce the height, dents may be formed from both the front and back surfaces of the first interposer.

<Shape of semiconductor interposer-2>
FIG. 16 shows an embodiment 13 of the present invention, which can further reduce the height of the first semiconductor device. In the figure, the same reference numerals as those in FIG. 10 denote the same components. FIG. 2A is a structural cross-sectional view of a stacked form of the first semiconductor device and the second semiconductor device, and FIG. 2B electrically connects these two semiconductor devices. It is an enlarged view of a part. Unlike the above-described seventh embodiment (FIG. 10), in this embodiment, the central portion of the first interposer 190 is removed. That is, the first semiconductor chip has a peripheral region supported by the 190. In other words, the first interposer has an opening shape in the central portion, and the region of the central portion of the first semiconductor chip is not in contact with the first interposer. With this configuration, the “thinly processed interposer portion” of the seventh embodiment is eliminated, and the height indicated by “h2” in FIG. 16A can be further reduced. As is clear from the structural sectional view of FIG. 5A, in this embodiment, there is a restriction that the size of the second semiconductor chip is smaller than the size of the first semiconductor chip. Yes. However, the restriction can be avoided by appropriately designing the configuration of the first semiconductor device 110 and the second semiconductor device 115 and the wiring of the first interposer 190 and the second interposer 117. Further, the “second semiconductor device” in this paragraph may alternatively be a printed circuit board or a wiring board such as a printed circuit board on which a semiconductor chip is mounted.

<Semiconductor device mounting-3>
FIG. 17 is a view for explaining the embodiment 14 and shows a manufacturing flow of the semiconductor device mounting shown in FIG. In the figure, the same reference numerals as those in FIG. 11 denote the same components. FIG. 17A and FIG. 17B are diagrams illustrating a process for manufacturing the first interposer 190. In FIG. 2A, reference numeral 124 denotes a first semiconductor substrate constituting the first interposer 190, 125 denotes a first main surface (lower surface in the figure) of the first interposer, and 126 denotes the first interposer 190. It is the 2nd main surface (upper surface in a figure) of 1 interposer. The first conductor 113 is provided on the surface of the first main surface 125, and the wiring conductor 127 is provided on the surface of the second main surface 126. The 113 and the 127 are connected to the through electrode 128. Are connected in the thickness direction (vertical direction in the figure) of the first semiconductor substrate. In the figure, a structure for electrically insulating the through electrode 128 from the first semiconductor substrate 124 is omitted. Next, as shown in the sectional view of the structure in FIG. 4B, the central region of the first interposer 190 is removed by a known method such as anisotropic etching, and the opening shape 200 is formed. FIG. 3C is a diagram in which the first semiconductor chip 111 is mounted on the surface of the second main surface of the first interposer 190. As shown in FIG. 6C, only the peripheral region of the first semiconductor chip is mechanically connected to the 190-shaped peripheral region of the first semiconductor chip. Further, since the first interposer is an opening provided in the central portion, that is, there is no “thinly processed interposer portion” as shown in the seventh embodiment, the machine of the first interposer The mechanical strength will decrease. However, by mounting the first semiconductor chip, the entire laminated structure becomes a so-called “monocoque structure” and corrects a decrease in mechanical strength. Reference numeral 130 denotes connection means for connecting the connection terminal of the first semiconductor chip to the wiring conductor 127, and is, for example, a ball grid array. In addition to this, a known wire bonding may be used as the connection means. A resin layer 201 called an underfill is provided to increase the mechanical strength of the connection means after the first semiconductor chip 111 is mounted by the connection means 130. In this embodiment, the underfill is an essential component for increasing the mechanical connection strength between the first semiconductor chip and the first interposer and the mechanical strength of the entire laminated structure. ing. In FIG. 3C, reference numeral 13 denotes the first metal block provided on the surface of the first conductor 113. In the figure, it is illustrated that three first metal blocks are arranged on the surface of each first conductor. The structure shown in FIG. 3C is the structure of the first semiconductor device.

  FIG. 17D is a sectional view showing a structure of a second interposer constituting the second semiconductor device (corresponding to 115 in FIG. 16). In FIG. 4D, 132 is a second semiconductor substrate constituting the second interposer, 135 is a first main surface (lower surface in the figure) of the second interposer, and 136 is the second semiconductor substrate. This is a second main surface (upper surface in the figure) of the interposer. The second conductor 118 is provided on the surface of the second main surface 136, and the external connection conductor 133 is provided on the surface of the first main surface 135. The 118 and 133 are formed as through electrodes. 138 is connected in the thickness direction (vertical direction in the figure) of the second semiconductor substrate. In the figure, the structure for electrically insulating the through electrode 138 from the second semiconductor substrate 132 is omitted. Further, the second conductor 118 also serves as a wiring conductor in the second interposer, like the wiring conductor 127 described above. FIG. 4E is a diagram in which the second semiconductor chip 116 is mounted on the surface of the second main surface of the second interposer 117. Reference numeral 140 denotes connection means for connecting the connection terminal of the second semiconductor chip to the second conductor 118 serving also as the wiring conductor, and is, for example, a ball grid array. In addition to this, a known wire bonding may be used as the connection means. Reference numeral 141 denotes a resin layer called an underfill, which is provided to increase the mechanical strength of the connecting means after the second semiconductor chip 116 is mounted by the connecting means 140. The underfill functions to absorb expansion due to heat generation in the second semiconductor chip 116 and to dissipate heat generation to the second interposer side. In order to improve the heat dissipation effect, a resin constituting the underfill may be poured in vacuum so that air bubbles are not generated in the underfill. In FIG. 4E, reference numeral 18 denotes the second metal block provided on the surface of the second conductor 118. In the figure, it is illustrated that three second metal blocks are arranged on the surface of each second conductor. In FIG. 4E, a conductive ball 120 is disposed on the surface of the external connection conductor 133 and is used for electrical connection with an external circuit (not shown) made of a printed circuit board or the like. The structure shown in FIG. 4E is the structure of the second semiconductor device.

  FIG. 17F shows a cross section of the structure in which the first semiconductor device shown in FIG. 17C is stacked and mounted on the second semiconductor device shown in FIG. In FIG. 8 (f), reference numeral 143 denotes a conductive path, which is formed by facing the first metal block 13 and the second metal block 18 and melting and resolidifying them by heat treatment in a high temperature atmosphere. Yes. In order to increase the mechanical connection strength of the conductive path, a resin layer may be poured into a region of the conductive path to form an underfill. In addition, the resin layer may flow not only in the region of the conductive path but also in a region between the first interposer and the second interposer. As shown in FIG. 5F, the upper side of the second semiconductor chip is in a form of entering the region of the opening shape (200) of the first interposer. In addition, a resin having a high thermal conductivity is filled in a gap (indicated by 205) between the first interposer and the upper surface of the second semiconductor chip. It is also possible to dissipate heat generated by the semiconductor chip and the second semiconductor chip.

  In Example 14, the case where the first semiconductor device and the second semiconductor device were constituted by a semiconductor chip and an interposer was shown. In this configuration, the first main surface of the first semiconductor device is the same as the first main surface of the first interposer, and similarly, the second main surface of the second semiconductor device. Is the same as the second main surface of the second interposer.

  The thirteenth and fourteenth embodiments described in detail with reference to FIGS. 16 and 17 both show the case where the second semiconductor device is constituted by the second semiconductor chip and the second interposer. It was. However, in these embodiments, a wiring board such as a printed board or a printed board on which a semiconductor chip is mounted may be employed as an alternative to the second semiconductor device.

<Semiconductor device mounting-4>
FIG. 18 is a diagram for explaining Example 15, which is an example in which the present invention is applied to a configuration having a large heat dissipation effect. In the present embodiment, the first semiconductor device and the second semiconductor device are both composed of a semiconductor chip and an interposer, and both are provided with a “thinly processed interposer portion”, so that the heat dissipation mechanism and the combination can be combined. There is an advantage that becomes easier. FIG. 18A shows a structure 210 in which the first semiconductor device 110 is stacked on the second semiconductor device 115. The designated area 212 (area where the first semiconductor chip 213 is mounted) of the first interposer 211 that constitutes the 110 is processed such that the thickness of the interposer is partially reduced. In addition, the designated region 217 (the region on which the second semiconductor chip 218 is mounted) of the second interposer 216 constituting the 115 is also processed so that the thickness of the interposer is partially reduced. In the region 212, the second semiconductor chip 218 enters. Further, a space 219 is provided in a lower region of the stacked structure 210 (that is, corresponding to the 217). FIG. 2B shows a form in which the laminated structure 210 is mounted on the wiring board 220. In the space 219 described above, the heat radiating means 221 is arranged. Such heat radiating means may be formed of a lump of a material having a high thermal conductivity (for example, a metal such as copper). Moreover, you may employ | adopt heat dissipation means, such as a heat pipe and a refrigerant flow path. The present embodiment is characterized in that a heat radiating means is combined with the space 219 formed by processing the specified region of the second interposer to be thin, and the laminated structure including the heat radiating means is low. It can greatly contribute to heightening.

  Up to the previous paragraph, it was described that the bonding strength is increased by providing an underfill made of a resin or the like when metal blocks are bonded to form a conductive path. This paragraph describes this underfill. There are many types of resins used for underfill, including thermoplastic resins, thermosetting resins, and conductive resins containing conductors. Also, there are many grades with different viscosities and melting points for specific resins. In the present invention, the type and grade of resin used for underfill are not limited. For example, a material in which solder particles are mixed in a thermosetting resin is placed in a required region and heat-treated, so that “melted solder particles gather in the region where the conductor is present and re-solidify, and conductive. There is a material (also referred to as pre-applied resin) in which only the resin remains and solidifies in a region where no body exists. If a material having such characteristics is applied to the present invention, formation of a metal lump and filling of an underfill resin can be achieved simultaneously, and the effect is great.

  According to the present invention, it is possible to provide a mounting method that can easily achieve high-density mounting with a low profile. More specifically, the mechanical strength of the interposer is ensured by adopting the semiconductor interposer, the electrical connectivity is secured by arranging at least two small metal blocks in parallel, and the high required for wire bonding. The problem of low profile was solved by eliminating space in the vertical direction. For this reason, in addition to mobile phones and digital cameras, in a wide range of fields such as in-vehicle equipment and industrial equipment, it is possible to achieve both low power consumption and high reliability, not to mention lighter and smaller equipment. Yes, it is highly available.

1, 2 Interposer 3 Conductive ball 4 Total thickness 10, 30, 110 First semiconductor device 11, 31, 125, 135 First main surface 12, 22, 113 First conductor 13, 41, 42, 43 51, 61, 71, 81, 85, 91, 100, 104
First metal block 15, 35, 115 Second semiconductor device or wiring board 16, 126, 136 Second main surface 17, 118 Second conductor 18, 23, 52, 62, 72, 82, 86, 92 , 101, 105
Second metal block 20, 24, 25, 119, 143 Conductive path 32 Metal block 40 Mask layer 83, 84, 87, 88 Longitudinal direction 93, 94 Longitudinal direction 102, 103, 106, 107 direction 111, 213 First Semiconductor chip 112, 152, 190, 211 First interposer 116, 218 Second semiconductor chip 117, 153, 216 Second interposer 120 Conductive ball 121, 212, 217 Thinly processed interposer portion 124 First Semiconductor substrate 127, 171, 181 Wiring conductor 128, 138 Through electrode 130, 140 Connection means 131, 141, 154, 155, 201 Resin layer (underfill)
132 Second semiconductor substrate 133 External connection conductor 144, 205 Air gap 150 Insulating layer 151 Metal layer 160 Third semiconductor device 161, 220 Wiring substrate 170 Pad 180 Depression 200 Opening shape 210 Multilayer structure 219 Space 221 Heat dissipation means

Claims (8)

A mounting method for mounting a surface mount type semiconductor device in which terminals for electrical connection are arranged in a matrix on a wiring board in which terminals for electrical connection are arranged in a matrix,
The first main surface of the semiconductor device is provided with at least two first conductors for electrically connecting the semiconductor device to the wiring board,
Each of the first conductors is provided with at least two first metal blocks,
The second main surface of the wiring board is provided with at least two second conductors for electrically connecting the wiring board to the semiconductor device,
Each of the second conductors is provided with at least two second metal blocks,
A method for mounting a semiconductor device, wherein the semiconductor device and the wiring substrate are electrically connected by joining the first metal block and the second metal block. The semiconductor device includes a stacked structure of a semiconductor chip and a semiconductor interposer, and the first conductor and the first metal block are disposed on a main surface of the semiconductor interposer opposite to a main surface on which the semiconductor chip is disposed. The mounting method according to claim 1, wherein: is arranged. The first metal block and the second metal block have a circular shape in contact with the first conductor and the second conductor, respectively, and
3. The mounting method according to claim 1, wherein a ratio between the circular diameter and the arrangement pitch of the first metal block and the second metal block is greater than 0.58. 4. The first metal block and the second metal block are polygonal in contact with the first conductor and the second conductor, respectively, and
The diameter of the circle inscribed in the polygon and the ratio of the arrangement pitch of the first metal mass and the second metal mass is a value exceeding 0.58. How to implement Each of the first metal block and the second metal block is in the shape of an ellipse or an ellipse in contact with the first conductor and the second conductor, and
The major axis of the ellipse or the ellipse constituting the first metal block and the major axis of the ellipse or the ellipse constituting the second metal block intersect each other. 2. The mounting method according to 2. The first metal block and the second metal block are respectively in a stripe shape in contact with the first conductor and the second conductor, and
3. The mounting method according to claim 1, wherein the stripe forming the first metal block and the stripe forming the second metal block intersect each other. The thickness of the semiconductor interposer in a specified region in the region where the semiconductor chip is mounted is equal to the thickness of the semiconductor interposer in the region where the first conductor and the first metal block are disposed. The mounting method according to claim 1, wherein the mounting method does not exceed. The mounting method according to claim 1, wherein the semiconductor interposer has an opening shape at a central portion, and a semiconductor chip is mounted on an upper portion of the opening shape.