JP2014053597A - Chip type electronic component and connection structure - Google Patents

Chip type electronic component and connection structure Download PDF

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JP2014053597A
JP2014053597A JP2013160978A JP2013160978A JP2014053597A JP 2014053597 A JP2014053597 A JP 2014053597A JP 2013160978 A JP2013160978 A JP 2013160978A JP 2013160978 A JP2013160978 A JP 2013160978A JP 2014053597 A JP2014053597 A JP 2014053597A
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substrate
chip
electronic component
type electronic
bump electrodes
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Gyorei To
暁黎 杜
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip type electronic component of which excellent connection can be achieved by suppressing warpage of a substrate during flip-chip mounting, and to provide a connection structure thereof.SOLUTION: In a chip type electronic component 1, a passivation film 6 having a thickness satisfying a relation Hb>Hp≥(1/3)Hb is formed in a region where bump electrodes 4, 5 are not arranged on the mounting surface 2a of a substrate 2. Consequently, in a connection structure 30, volume difference of an anisotropic conductive adhesive can be suppressed between a region where the bump electrodes 4, 5 are arranged and a region where the bump electrodes are not arranged, and thereby warpage of the substrate 2 due to the difference in cure shrinkage amount of the anisotropic conductive adhesive can be suppressed during flip-chip mounting. Since warpage of the substrate 2 can be suppressed, peeling of the bump electrodes 4, 5, arranged along the long side of the substrate 2, off from an electrode 22 can be avoided, and excellent connection state can be maintained.

Description

本発明は、チップ型電子部品及び接続構造体に関する。   The present invention relates to a chip-type electronic component and a connection structure.

電子機器の小型化・薄型化に伴い、チップ型電子部品の高密度実装技術の確立が要求されている。従来のチップの実装方法としては、例えばリードフレームを用いた方法がある。この従来の方法は、リードフレーム上のチップをワイヤで回路基板に接続して樹脂封止を行うものであるが、ワイヤのスペースを確保する関係上、実装密度を向上させるのが困難であった。   With the downsizing and thinning of electronic devices, establishment of high-density mounting technology for chip-type electronic components is required. As a conventional chip mounting method, for example, there is a method using a lead frame. In this conventional method, the chip on the lead frame is connected to the circuit board with a wire to perform resin sealing, but it is difficult to improve the mounting density because of securing the wire space. .

そこで、近年では、チップ型電子部品を高密度実装できる技術としてフリップチップ実装が注目されてきている。この方法は、チップ側のバンプ電極と回路基板側の電極とを異方導電性接着剤等を用いて接続するものである。例えば特許文献1に記載の方法では、バンプ電極と回路基板上の電極とを異方導電性接着剤で接続するに際し、接続部に予め超音波を印加し、金属を溶融させて接続性を担保している。   Therefore, in recent years, flip-chip mounting has attracted attention as a technology that enables high-density mounting of chip-type electronic components. In this method, the bump electrode on the chip side and the electrode on the circuit board side are connected using an anisotropic conductive adhesive or the like. For example, in the method described in Patent Document 1, when connecting the bump electrode and the electrode on the circuit board with an anisotropic conductive adhesive, an ultrasonic wave is applied to the connection portion in advance to melt the metal and ensure connectivity. doing.

特開2010−251789JP2010-251789

ところで、上述したようなフリップチップ実装方法には、チップ側のバンプ電極と回路基板側の電極との間に異方導電性接着剤を配置した後、異方導電性接着剤に光や熱を加えて硬化する工程が含まれる場合がある。この工程においては、異方導電性接着剤の硬化収縮が生じるが、チップにおいてバンプ電極が形成されている領域と形成されていない領域では異方導電性接着剤の厚さが異なるため、硬化収縮量に差異が生じることがある。このため、硬化収縮量が大きい領域、すなわち、バンプ電極が形成されていない領域にむかってチップの基板に反りが生じてしまうおそれがある。このような問題は、基板が薄い場合に特に顕著となりやすく、基板に反りが生じるとチップ型電子部品と回路基板との接続不良の発生が問題となる。   By the way, in the flip chip mounting method as described above, after an anisotropic conductive adhesive is disposed between the bump electrode on the chip side and the electrode on the circuit board side, light or heat is applied to the anisotropic conductive adhesive. In addition, a curing step may be included. In this process, curing shrinkage of the anisotropic conductive adhesive occurs, but the thickness of the anisotropic conductive adhesive is different between the area where the bump electrode is formed and the area where the bump electrode is not formed on the chip. Differences in quantity may occur. For this reason, there is a possibility that the substrate of the chip is warped toward the region where the amount of cure shrinkage is large, that is, the region where the bump electrode is not formed. Such a problem is particularly noticeable when the substrate is thin. When the substrate is warped, a problem of poor connection between the chip-type electronic component and the circuit substrate becomes a problem.

本発明は、上記課題の解決のためになされたものであり、フリップチップ実装時の基板の反りを抑制することにより良好な接続を実現できるチップ型電子部品、及びその接続構造体を提供することを目的とする。   The present invention has been made to solve the above problems, and provides a chip-type electronic component capable of realizing good connection by suppressing warpage of the substrate during flip-chip mounting, and a connection structure thereof. With the goal.

本発明に係るチップ型電子部品は、基板と、基板の一面側に配列されたバンプ電極と、基板の上記一面側にバンプ電極の配列方向に沿って形成されたパッシベーション膜と、を備えたチップ型電子部品であって、パッシベーション膜の厚さHpとバンプ電極の厚さHbとが、Hb>Hp≧(1/3)Hbを満たすことを特徴としている。   A chip-type electronic component according to the present invention includes a substrate, a bump electrode arranged on one side of the substrate, and a passivation film formed along the arrangement direction of the bump electrode on the one side of the substrate. The electronic component is characterized in that the thickness Hp of the passivation film and the thickness Hb of the bump electrode satisfy Hb> Hp ≧ (1/3) Hb.

このチップ型電子部品では、バンプ電極が配列されていない領域において、上記関係を満たす厚さのパッシベーション膜が形成されている。このパッシベーション膜により、チップ型電子部品をフリップチップ実装する際に、バンプ電極が配列されている領域と配列されていない領域との間の異方導電性接着剤の体積の差を小さくすることが可能となり、異方導電性接着剤の硬化収縮量の差による基板の反りを抑制できる。また、実装時にパッシベーション膜が異物によって損傷することも抑制できる。これにより、良好な接続を実現できる。   In this chip-type electronic component, a passivation film having a thickness satisfying the above relationship is formed in a region where the bump electrodes are not arranged. With this passivation film, when flip chip mounting a chip-type electronic component, it is possible to reduce the volume difference of the anisotropic conductive adhesive between the region where the bump electrodes are arranged and the region where the bump electrodes are not arranged. This makes it possible to suppress the warpage of the substrate due to the difference in the amount of cure shrinkage of the anisotropic conductive adhesive. Further, it is possible to prevent the passivation film from being damaged by foreign matters during mounting. Thereby, a favorable connection is realizable.

また、パッシベーション膜は、バンプ電極の列間に延在していることが好ましい。この場合、異方導電性接着剤の硬化収縮量の差による基板の反りを一層抑制できる。   Further, the passivation film preferably extends between the rows of bump electrodes. In this case, it is possible to further suppress the warpage of the substrate due to the difference in the curing shrinkage amount of the anisotropic conductive adhesive.

また、パッシベーション膜の厚さは、3μm以上であることが好ましい。この場合、異物が入り込む空間が減少し、異物の侵入を防止することができる。したがって、異物によるパッシベーション膜の損傷が抑制され、パッシベーション膜の保護膜としての機能を維持することができる。   The thickness of the passivation film is preferably 3 μm or more. In this case, the space into which the foreign substance enters is reduced, and the entry of the foreign substance can be prevented. Therefore, damage to the passivation film due to foreign substances is suppressed, and the function of the passivation film as a protective film can be maintained.

また、チップ型電子部品は、バンプ電極を含まない厚さが0.3mm以下であることが好ましい。0.3mm以下の薄型のチップ型電子部品では、異方導電性接着剤の硬化収縮による基板の反りが顕著に発生しやすい。したがって、パッシベーション膜の厚さとバンプ電極の厚さとを上記関係とすることで、薄型のチップ型電子部品においても基板の反りを効果的に抑制できる。   The chip-type electronic component preferably has a thickness not including the bump electrode of 0.3 mm or less. In a thin chip-type electronic component having a thickness of 0.3 mm or less, warpage of the substrate due to curing shrinkage of the anisotropic conductive adhesive tends to occur remarkably. Therefore, by setting the thickness of the passivation film and the thickness of the bump electrode in the above relationship, the warpage of the substrate can be effectively suppressed even in a thin chip type electronic component.

また、本発明に係る接続構造体は、上記のチップ型電子部品のバンプ電極を、異方導電性接着剤の硬化物を介して回路基板の電極に接続したことを特徴としている。   The connection structure according to the present invention is characterized in that the bump electrode of the chip-type electronic component is connected to the electrode of the circuit board through a cured product of anisotropic conductive adhesive.

この接続構造体では、チップ型電子部品において、パッシベーション膜の厚さとバンプ電極の厚さとが上記関係を満たしている。したがって、チップ型電子部品をフリップチップ実装する際に、バンプ電極が配列されている領域と配列されていない領域との間の異方導電性接着剤の体積の差を小さくすることが可能となり、異方導電性接着剤の硬化収縮量の差による基板の反りを抑制できる。また、実装時にパッシベーション膜が異物によって損傷することも抑制できる。これにより良好な接続を実現できる。   In this connection structure, in the chip-type electronic component, the thickness of the passivation film and the thickness of the bump electrode satisfy the above relationship. Therefore, when flip-chip mounting the chip-type electronic component, it becomes possible to reduce the volume difference of the anisotropic conductive adhesive between the region where the bump electrode is arranged and the region where the bump electrode is not arranged, The board | substrate curvature by the difference in the amount of cure shrinkage of an anisotropic conductive adhesive can be suppressed. Further, it is possible to prevent the passivation film from being damaged by foreign matters during mounting. Thereby, a good connection can be realized.

本発明によれば、フリップチップ実装時の基板の反りを抑制することにより、良好な接続を実現できる。   According to the present invention, good connection can be realized by suppressing the warpage of the substrate during flip chip mounting.

本発明の一実施形態に係るチップ型電子部品を示す模式的平面図である。1 is a schematic plan view showing a chip-type electronic component according to an embodiment of the present invention. 図1におけるII−II線模式的断面図である。FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. 本発明の一実施形態に係る接続構造体を示す模式的断面図である。It is a typical sectional view showing the connection structure concerning one embodiment of the present invention. 比較例に係る接続構造体を示す模式的断面図である。It is typical sectional drawing which shows the connection structure which concerns on a comparative example.

以下、図面を参照しながら本発明に係るチップ型電子部品及び接続構造体の好適な実施形態について詳細に説明する。   Hereinafter, preferred embodiments of a chip-type electronic component and a connection structure according to the present invention will be described in detail with reference to the drawings.

図1は、本発明の一実施形態に係るチップ型電子部品1を示す模式的平面図である。また、図2は、図1におけるII−II線模式的断面図である。図1及び図2に示すように、チップ型電子部品1は、基板2と、バンプ電極4,5と、パッシベーション膜6とを備えている。このチップ型電子部品1は、例えばタッチパネル等の電子機器に適用されるICチップ或いは回路基板であり、後述する回路基板20に接続されて接続構造体30を形成する。   FIG. 1 is a schematic plan view showing a chip-type electronic component 1 according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. As shown in FIGS. 1 and 2, the chip-type electronic component 1 includes a substrate 2, bump electrodes 4 and 5, and a passivation film 6. The chip-type electronic component 1 is an IC chip or a circuit board that is applied to an electronic device such as a touch panel, for example, and is connected to a circuit board 20 described later to form a connection structure 30.

基板2は、例えば長方形状をなす半導体基板である。基板2の厚さは、例えば0.1〜1.1mm程度となっている。半導体としては、特に制限はなく、シリコン、ゲルマニウムなどの元素半導体、ガリウムヒ素、インジウムリンなどの化合物半導体といった各種半導体を用いることができる。基板2の一面側は、回路基板20に対する実装面2aとなっており、バンプ電極4,5及びパッシベーション膜6が配列されている。なお、基板2の形状は、長方形状に限られず、正方形状や台形状等であってもよい。   The substrate 2 is a semiconductor substrate having a rectangular shape, for example. The thickness of the substrate 2 is, for example, about 0.1 to 1.1 mm. There is no restriction | limiting in particular as a semiconductor, Various semiconductors, such as elemental semiconductors, such as silicon and germanium, and compound semiconductors, such as gallium arsenide and indium phosphorus, can be used. One surface side of the substrate 2 is a mounting surface 2a for the circuit substrate 20, and bump electrodes 4 and 5 and a passivation film 6 are arranged. In addition, the shape of the board | substrate 2 is not restricted to a rectangular shape, Square shape, trapezoid shape, etc. may be sufficient.

バンプ電極4,5は、基板2の実装面2aに設けられた接続端子(不図示)上に形成されている。バンプ電極4は、基板2の一方の長辺に沿って千鳥状に配列されている。また、バンプ電極5は、基板2の他方の長辺に沿って一列に配列されている。パッシベーション膜6は、バンプ電極4とバンプ電極5との間の領域において、バンプ電極4,5の配列方向に沿って扁平な直方体形状に形成されている。   The bump electrodes 4 and 5 are formed on connection terminals (not shown) provided on the mounting surface 2 a of the substrate 2. The bump electrodes 4 are arranged in a staggered pattern along one long side of the substrate 2. The bump electrodes 5 are arranged in a line along the other long side of the substrate 2. The passivation film 6 is formed in a flat rectangular parallelepiped shape along the arrangement direction of the bump electrodes 4, 5 in the region between the bump electrode 4 and the bump electrode 5.

接続端子は、基板2が回路基板である場合には、配線導体と同時にパターン形成してもよく、銅箔等の金属箔において不要な部分をエッチング除去して形成してもよい。また、絶縁基板の上に接続端子の形状に合わせて無電解めっきで形成してもよい。一方、接続端子は、基板2が半導体基板である場合には、例えばアルミニウムによって構成される。この場合、接続端子の表面に、ニッケル、金、プラチナ等による貴金属めっきを行ってもよい。   When the substrate 2 is a circuit board, the connection terminal may be formed at the same time as the wiring conductor, or may be formed by removing unnecessary portions of a metal foil such as a copper foil by etching. Further, it may be formed on the insulating substrate by electroless plating in accordance with the shape of the connection terminal. On the other hand, the connection terminal is made of aluminum, for example, when the substrate 2 is a semiconductor substrate. In this case, noble metal plating with nickel, gold, platinum or the like may be performed on the surface of the connection terminal.

バンプ電極4,5は、回路基板20との接続に用いられる電極であり、例えばニッケルや金のバンプ、或いははんだボールによって形成されている。バンプ電極4,5は、はんだバンプ、銅バンプ、銅ピラー先端にはんだ又はスズ層が形成された構造のバンプ、金バンプ等によって形成してもよい。また、微細接続化への対応から、銅バンプや銅ピラー先端にはんだまたはスズ層が形成された構造のバンプを用いてもよい。なお、バンプ電極4,5の数、位置については、用途、使用目的に応じて適宜選択することができる。バンプ電極4,5の断面形状も、適宜選択可能である。   The bump electrodes 4 and 5 are electrodes used for connection to the circuit board 20 and are formed of, for example, nickel or gold bumps or solder balls. The bump electrodes 4 and 5 may be formed by solder bumps, copper bumps, bumps having a structure in which a solder or tin layer is formed at the tip of a copper pillar, gold bumps, or the like. Moreover, you may use the bump of the structure in which the solder or the tin layer was formed in the copper bump or the copper pillar tip from the correspondence to fine connection. In addition, about the number and position of bump electrode 4 and 5, it can select suitably according to a use and a use purpose. The cross-sectional shape of the bump electrodes 4 and 5 can also be selected as appropriate.

バンプ電極4,5の形成方法としては、エッチングやめっき等の汎用の方法を用いることができる。例えばバンプ電極4,5の形成箇所以外の導体部分を厚さ方向にハーフエッチングして突起部分を形成し、更に薄くなった導体部分の回路部分を残しつつ、他の部分をエッチング除去することによってバンプ電極4,5を形成することができる。また、基板2の実装面2a上に回路を形成した後に、接続端子の箇所だけめっきによって厚くする方法によりバンプ電極4,5を形成してもよい。   As a method for forming the bump electrodes 4 and 5, a general-purpose method such as etching or plating can be used. For example, a conductor portion other than the formation location of the bump electrodes 4 and 5 is half-etched in the thickness direction to form a projection portion, and the other portion is etched away while leaving the circuit portion of the thinner conductor portion. Bump electrodes 4 and 5 can be formed. Further, after forming a circuit on the mounting surface 2a of the substrate 2, the bump electrodes 4 and 5 may be formed by a method in which only the connection terminal portions are thickened by plating.

バンプ電極4,5の厚さHbは、特に制限はないが、例えば9〜18μmとなっている。なお、バンプ電極4,5の厚さHbは、上記のバンプ形成方法において調節することが可能であり、その厚さHbは、既存の膜厚測定装置を用いて測定することができる。また、バンプ電極4,5が配列された領域外にダミーバンプ(不図示)を更に形成してもよい。上記領域にダミーバンプを形成すると、チップ型電子部品1を実装する回路基板20に対してチップ型電子部品1の姿勢を平行にした状態でフリップチップ実装し易くなる。これにより、実装の作業性を向上できる。   The thickness Hb of the bump electrodes 4 and 5 is not particularly limited, but is, for example, 9 to 18 μm. Note that the thickness Hb of the bump electrodes 4 and 5 can be adjusted in the above bump forming method, and the thickness Hb can be measured using an existing film thickness measuring apparatus. Further, dummy bumps (not shown) may be further formed outside the region where the bump electrodes 4 and 5 are arranged. When dummy bumps are formed in the region, flip chip mounting is facilitated in a state where the posture of the chip electronic component 1 is parallel to the circuit board 20 on which the chip electronic component 1 is mounted. Thereby, the workability of mounting can be improved.

一方、パッシベーション膜6は、外部からの水分、酸素等の侵入を防止する保護膜であり、例えば窒化ケイ素、酸化ケイ素などを用いて、CVD法、蒸着法、スパッタ法といった既知の製膜法によって形成されている。本実施形態では、パッシベーション膜6は、基板2のバンプ電極4,5間に長尺状に形成されているが、パッシベーション膜6は長尺形状に限られず、矩形のパッシベーション膜をバンプ電極4,5間に点在させるようにしてもよい。また、パッシベーション膜6は、バンプ電極4,5の配列位置によっては、バンプ電極4,5間ではなく、バンプ電極4,5よりも外側の領域に配置してもよい。   On the other hand, the passivation film 6 is a protective film that prevents intrusion of moisture, oxygen, and the like from the outside. For example, using a silicon nitride, silicon oxide, or the like, a known film forming method such as CVD, vapor deposition, or sputtering is used. Is formed. In the present embodiment, the passivation film 6 is formed in a long shape between the bump electrodes 4, 5 of the substrate 2, but the passivation film 6 is not limited to a long shape, and a rectangular passivation film is used as the bump electrode 4. You may make it interspersed between five. Further, the passivation film 6 may be arranged not in the area between the bump electrodes 4 and 5 but in a region outside the bump electrodes 4 and 5 depending on the arrangement position of the bump electrodes 4 and 5.

このパッシベーション膜6の厚さHpは、バンプ電極4,5の厚さHbに対して、Hb>Hp≧(1/3)Hbを満たしている。また、パッシベーション膜6の厚さHpは、例えばHbが9μmのときは3μm以上、Hbが12μm以上のときは4μm以上、Hbが18μmのときは6μm以上となっている。さらに、基板2との関係において、パッシベーション膜6の厚さHpは、バンプ電極4,5の厚さを除いたチップ型電子部品1の厚さが0.3mm以下となるように決定される。すなわち、パッシベーション膜6の厚さと基板2の厚さとの合計が0.3mm以下となるように決定される。この場合、基板2の厚さは0.3mm未満となるように設定される。なお、パッシベーション膜6の厚さHpは、上記のパッシベーション膜形成方法において調節することが可能であり、その厚さHpは、既存の膜厚測定装置を用いて測定することができる。   The thickness Hp of the passivation film 6 satisfies Hb> Hp ≧ (1/3) Hb with respect to the thickness Hb of the bump electrodes 4 and 5. The thickness Hp of the passivation film 6 is, for example, 3 μm or more when Hb is 9 μm, 4 μm or more when Hb is 12 μm or more, and 6 μm or more when Hb is 18 μm. Further, in relation to the substrate 2, the thickness Hp of the passivation film 6 is determined so that the thickness of the chip-type electronic component 1 excluding the thickness of the bump electrodes 4 and 5 is 0.3 mm or less. That is, the sum of the thickness of the passivation film 6 and the thickness of the substrate 2 is determined to be 0.3 mm or less. In this case, the thickness of the substrate 2 is set to be less than 0.3 mm. The thickness Hp of the passivation film 6 can be adjusted in the above-described passivation film forming method, and the thickness Hp can be measured using an existing film thickness measuring apparatus.

続いて、上述したチップ型電子部品1を用いた接続構造体について説明する。   Subsequently, a connection structure using the chip-type electronic component 1 described above will be described.

図3は、本発明の一実施形態に係る接続構造体を示す模式的断面図である。同図に示すように、接続構造体30は、異方導電性接着剤の硬化物10を介してチップ型電子部品1と回路基板20とをフリップチップ接続してなる構造体である。   FIG. 3 is a schematic cross-sectional view showing a connection structure according to an embodiment of the present invention. As shown in the figure, the connection structure 30 is a structure in which the chip-type electronic component 1 and the circuit board 20 are flip-chip connected via a cured product 10 of anisotropic conductive adhesive.

回路基板20は、例えば表面に電極22を有するガラス基板24である。ガラス基板24としては、例えばコーニングガラス、ソーダガラス等を用いることができる。ガラス基板24の形状としては、長方形を想定しているが、チップ型電子部品1の形状合わせて、正方形、台形等、適宜選択することができる。回路基板20は、ガラス基板に限られず、通常の回路基板、フレキシブルプリント配線板、半導体チップ等を用いてもよい。回路基板の場合、ガラスエポキシ、ポリイミド、ポリエステル、セラミックなどの絶縁基板表面に形成された銅などの金属層の不要な箇所をエッチング除去して配線パターンを形成したもの、絶縁基板表面に銅めっきなどによって配線パターンを形成したもの、絶縁基板表面に導電性物質を印刷して配線パターンを形成したものなどを用いることができる。   The circuit board 20 is, for example, a glass substrate 24 having electrodes 22 on the surface. As the glass substrate 24, for example, coning glass or soda glass can be used. The shape of the glass substrate 24 is assumed to be a rectangle, but a square, a trapezoid, or the like can be appropriately selected according to the shape of the chip electronic component 1. The circuit board 20 is not limited to a glass substrate, and a normal circuit board, a flexible printed wiring board, a semiconductor chip, or the like may be used. In the case of a circuit board, an unnecessary part of a metal layer such as copper formed on the surface of an insulating substrate such as glass epoxy, polyimide, polyester, or ceramic is removed by etching to form a wiring pattern, or the surface of the insulating substrate is plated with copper. For example, a wiring pattern may be formed by using a conductive material printed on the surface of an insulating substrate.

電極22は、チップ型電子部品1が備えるバンプ電極4,5の位置に対応させてガラス基板24上に形成されている。電極22としては、例えば酸化インジウム錫(ITO)からなる透明電極用いることができる。透明電極としては、酸化インジウム亜鉛(IZO)などを用いてもよい。透明電極の形成方法としては、スパッタリング法、エレクトロンビーム法等の公知の方法を用いることができる。また、電極22として、アルミニウム、クロム、銀等からなる電極をガラス基板24上に形成してもよい。   The electrode 22 is formed on the glass substrate 24 so as to correspond to the positions of the bump electrodes 4 and 5 provided in the chip-type electronic component 1. As the electrode 22, for example, a transparent electrode made of indium tin oxide (ITO) can be used. As the transparent electrode, indium zinc oxide (IZO) or the like may be used. As a method for forming the transparent electrode, a known method such as a sputtering method or an electron beam method can be used. Further, as the electrode 22, an electrode made of aluminum, chromium, silver, or the like may be formed on the glass substrate 24.

異方導電性接着剤は、熱または光により硬化する樹脂組成物12と、導電性粒子14とを含有する。樹脂組成物12を構成する樹脂としては、例えば熱可塑性樹脂、熱硬化性樹脂、熱可塑性樹脂及び熱硬化性樹脂の混合系、光硬化性樹脂が用いられる。熱可塑性樹脂としては、スチレン樹脂系、ポリエステル樹脂系があり、熱硬化性樹脂としては、エポキシ樹脂系、シリコーン樹脂系が知られている。熱可塑性樹脂、熱硬化性樹脂を用いる場合は、通常、加熱加圧を必要とする。熱可塑性樹脂では樹脂を流動させ被着体との密着力を得るため、また熱硬化性樹脂では更に樹脂の硬化反応を行うためである。また、光硬化性樹脂を用いる場合は、低温での接続が求められる場合に有用である。光硬化性樹脂は、硬化に加熱を要しないことから、チップ型電子部品1とガラス基板24との熱膨張係数の差に起因するチップ型電子部品1の反りが抑制されるので好ましい。   The anisotropic conductive adhesive contains a resin composition 12 that is cured by heat or light, and conductive particles 14. As the resin constituting the resin composition 12, for example, a thermoplastic resin, a thermosetting resin, a mixed system of a thermoplastic resin and a thermosetting resin, or a photocurable resin is used. As the thermoplastic resin, there are a styrene resin type and a polyester resin type, and as the thermosetting resin, an epoxy resin type and a silicone resin type are known. When a thermoplastic resin or a thermosetting resin is used, heating and pressing are usually required. This is because the thermoplastic resin allows the resin to flow to obtain adhesion to the adherend, and the thermosetting resin further performs a resin curing reaction. Moreover, when using a photocurable resin, it is useful when the connection at low temperature is calculated | required. Since the photocurable resin does not require heating for curing, it is preferable because warpage of the chip type electronic component 1 due to a difference in thermal expansion coefficient between the chip type electronic component 1 and the glass substrate 24 is suppressed.

導電性粒子14としては、例えばAu、Ag、Ni、Cu、Pd、はんだ等の金属粒子、カーボン粒子が用いられる。また、導電性粒子14は、Ni、Cu等の遷移金属類の表面をAu、Pd等の貴金属類で被覆したものであってもよい。また、ガラス、セラミック、プラスチック等の非導電性粒子の表面を導電性物質で被覆する等の方法により、非導電性粒子表面に導通層を形成し、さらに最外層を貴金属類で構成したものや、熱溶融金属粒子を用いる場合、加熱加圧により変形性を有するので、接続時に電極との接触面積が増加し、信頼性を向上できる。   As the conductive particles 14, for example, metal particles such as Au, Ag, Ni, Cu, Pd, solder, and carbon particles are used. Further, the conductive particles 14 may be those in which the surface of a transition metal such as Ni or Cu is coated with a noble metal such as Au or Pd. In addition, a conductive layer is formed on the surface of non-conductive particles by a method such as coating the surface of non-conductive particles such as glass, ceramic, and plastic with a conductive material, and the outermost layer is made of noble metals. In the case of using hot-melt metal particles, since it has deformability by heating and pressing, the contact area with the electrode increases at the time of connection, and the reliability can be improved.

接続構造体30は、以下の方法により得ることができる。すなわち、接続構造体30は、チップ型電子部品1側のバンプ電極4,5と回路基板20側の電極22とを位置合わせし、バンプ電極4,5と電極22との間に異方導電性接着剤を介在させた状態で、チップ型電子部品1と回路基板20とを加圧しながら熱または光により異方導電性接着剤を硬化させ、異方導電性接着剤の硬化物10とすることによって形成される。   The connection structure 30 can be obtained by the following method. That is, the connection structure 30 aligns the bump electrodes 4 and 5 on the chip-type electronic component 1 side with the electrode 22 on the circuit board 20 side, and anisotropically conductive between the bump electrodes 4 and 5 and the electrode 22. With the adhesive interposed, the anisotropic conductive adhesive is cured by heat or light while pressing the chip-type electronic component 1 and the circuit board 20 to obtain a cured product 10 of the anisotropic conductive adhesive. Formed by.

このとき、チップ型電子部品1では、上述したように、基板2の実装面2aにおいて、バンプ電極4,5が配列されていない領域に、Hb>Hp≧(1/3)Hbを満たす厚さのパッシベーション膜6が形成されている。また、パッシベーション膜6の厚さは、3μm以上となっている。したがって、接続構造体30では、バンプ電極4,5が配列されている領域と配列されていない領域との間の異方導電性接着剤の体積差を抑えることができ、フリップチップ実装をする際の異方導電性接着剤の硬化収縮量の差による基板2の反りを抑制することができる。基板2の反りを抑制できることで、基板2の長辺に沿って配列されるバンプ電極4,5が電極22から剥離することを回避でき、良好な接続状態を維持できる。なお、接続状態については、例えばバンプ電極4,5と電極22との間の接続抵抗を測定することにより評価することができる。   At this time, in the chip-type electronic component 1, as described above, the thickness satisfying Hb> Hp ≧ (1/3) Hb in the region where the bump electrodes 4 and 5 are not arranged on the mounting surface 2a of the substrate 2. The passivation film 6 is formed. The thickness of the passivation film 6 is 3 μm or more. Therefore, in the connection structure 30, the volume difference of the anisotropic conductive adhesive between the region where the bump electrodes 4 and 5 are arranged and the region where the bump electrodes 4 and 5 are not arranged can be suppressed. Warpage of the substrate 2 due to the difference in curing shrinkage of the anisotropic conductive adhesive can be suppressed. Since the warpage of the substrate 2 can be suppressed, it is possible to avoid the bump electrodes 4 and 5 arranged along the long side of the substrate 2 from being peeled off from the electrode 22 and maintain a good connection state. The connection state can be evaluated, for example, by measuring the connection resistance between the bump electrodes 4 and 5 and the electrode 22.

また、チップ型電子部品1では、バンプ電極4,5間に異物が入り込みにくいため、実装時にパッシベーション膜6が異物によって損傷することも抑制できる。これにより、より確実に良好な接続を実現できる。このような薄型のチップ型電子部品1であっても、上記関係を満たす厚さのパッシベーション膜6をバンプ電極4,5間に設けることにより、基板2の反りを十分に抑制することができる。   Further, in the chip-type electronic component 1, foreign matter is unlikely to enter between the bump electrodes 4, 5, so that the passivation film 6 can be prevented from being damaged by foreign matter during mounting. Thereby, a favorable connection can be realized more reliably. Even in such a thin chip-type electronic component 1, the warp of the substrate 2 can be sufficiently suppressed by providing the passivation film 6 having a thickness satisfying the above relationship between the bump electrodes 4 and 5.

図4は、比較例に係る接続構造体を示す模式的断面図である。同図に示すように、比較例に係る接続構造体100は、バンプ電極4,5間にパッシベーション膜6を形成していない(或いはHp<(1/3)Hbとなるパッシベーション膜が形成される)点で本実施形態に係る接続構造体30と異なっている。この接続構造体100では、接続構造体30と比較して、バンプ電極4,5が配列されている領域と配列されていない領域とで、異方導電性接着剤の体積差が大きくなる。   FIG. 4 is a schematic cross-sectional view showing a connection structure according to a comparative example. As shown in the figure, in the connection structure 100 according to the comparative example, the passivation film 6 is not formed between the bump electrodes 4 and 5 (or a passivation film satisfying Hp <(1/3) Hb is formed. ) Is different from the connection structure 30 according to the present embodiment. In this connection structure 100, compared with the connection structure 30, the volume difference of the anisotropic conductive adhesive is large between the area where the bump electrodes 4 and 5 are arranged and the area where the bump electrodes 4 and 5 are not arranged.

したがって、接続構造体100では、フリップチップ実装の際、バンプ電極4,5が配列されていない領域における異方導電性接着剤の硬化収縮量が、バンプ電極4,5が配列されている領域に比べ大きくなり、例えば回路基板20側に向かって凸となるように基板2の反りが発生する。このため、バンプ電極4,5と電極22とが乖離して接続不良が生じるおそれがある。したがって、本実施形態のように、Hb>Hp≧(1/3)Hbを満たす厚さのパッシベーション膜6を形成することが、基板の反りによる接続不良を抑える観点から有用である。   Therefore, in the connection structure 100, when flip chip mounting is performed, the amount of cure shrinkage of the anisotropic conductive adhesive in the region where the bump electrodes 4 and 5 are not arranged is in the region where the bump electrodes 4 and 5 are arranged. The warpage of the substrate 2 occurs so as to be larger, for example, convex toward the circuit substrate 20 side. For this reason, there is a possibility that the bump electrodes 4 and 5 and the electrode 22 are separated from each other and connection failure occurs. Therefore, as in the present embodiment, it is useful to form the passivation film 6 having a thickness satisfying Hb> Hp ≧ (1/3) Hb from the viewpoint of suppressing connection failure due to the warpage of the substrate.

1…チップ型電子部品、2…基板、4,5…バンプ電極、6…パッシベーション膜、10…異方導電性接着剤の硬化物、20…回路基板、22…電極、30…接続構造体。   DESCRIPTION OF SYMBOLS 1 ... Chip-type electronic component, 2 ... Board | substrate, 4, 5 ... Bump electrode, 6 ... Passivation film | membrane, 10 ... Hardened | cured material of anisotropic conductive adhesive, 20 ... Circuit board, 22 ... Electrode, 30 ... Connection structure.

Claims (5)

基板と、前記基板の一面側に配列されたバンプ電極と、前記基板の前記一面側に前記バンプ電極の配列方向に沿って形成されたパッシベーション膜と、を備えたチップ型電子部品であって、
前記パッシベーション膜の厚さHpと前記バンプ電極の厚さHbとが、Hb>Hp≧(1/3)Hbを満たすことを特徴とするチップ型電子部品。
A chip-type electronic component comprising: a substrate; a bump electrode arranged on one side of the substrate; and a passivation film formed along the arrangement direction of the bump electrode on the one side of the substrate,
A chip-type electronic component, wherein the thickness Hp of the passivation film and the thickness Hb of the bump electrode satisfy Hb> Hp ≧ (1/3) Hb.
前記パッシベーション膜は、前記バンプ電極の列間に延在していることを特徴とする請求項1記載のチップ型電子部品。   The chip-type electronic component according to claim 1, wherein the passivation film extends between the bump electrode rows. 前記パッシベーション膜の厚さHpは3μm以上であることを特徴とする請求項1又は2記載のチップ型電子部品。   The chip-type electronic component according to claim 1, wherein a thickness Hp of the passivation film is 3 μm or more. 前記チップ型電子部品は、前記バンプ電極を含まない厚さが0.3mm以下であることを特徴とする請求項1から3のいずれか一項記載のチップ型電子部品。   4. The chip-type electronic component according to claim 1, wherein the thickness of the chip-type electronic component not including the bump electrode is 0.3 mm or less. 5. 請求項1から4のいずれか一項記載のチップ型電子部品の前記バンプ電極を、異方導電性接着剤の硬化物を介して回路基板の電極に接続したことを特徴とする接続構造体。   5. A connection structure, wherein the bump electrode of the chip-type electronic component according to claim 1 is connected to an electrode of a circuit board through a cured product of an anisotropic conductive adhesive.
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