JP5328792B2 - プロセッサの非常にアソシエティビティの高いキャッシュメモリ用のセカンドチャンス置換機構 - Google Patents

プロセッサの非常にアソシエティビティの高いキャッシュメモリ用のセカンドチャンス置換機構 Download PDF

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JP5328792B2
JP5328792B2 JP2010524027A JP2010524027A JP5328792B2 JP 5328792 B2 JP5328792 B2 JP 5328792B2 JP 2010524027 A JP2010524027 A JP 2010524027A JP 2010524027 A JP2010524027 A JP 2010524027A JP 5328792 B2 JP5328792 B2 JP 5328792B2
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JP2010538390A (ja
JP2010538390A5 (enExample
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ディー． ウィリアムズ ジェイムス
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/124—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being minimized, e.g. non MRU

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2010524027A 2007-09-04 2008-09-04 プロセッサの非常にアソシエティビティの高いキャッシュメモリ用のセカンドチャンス置換機構 Active JP5328792B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/849,515 2007-09-04
US11/849,515 US7861041B2 (en) 2007-09-04 2007-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor
PCT/US2008/010368 WO2009032275A1 (en) 2007-09-04 2008-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor

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JP2010538390A JP2010538390A (ja) 2010-12-09
JP2010538390A5 JP2010538390A5 (enExample) 2013-07-18
JP5328792B2 true JP5328792B2 (ja) 2013-10-30

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US (1) US7861041B2 (enExample)
EP (1) EP2198370B1 (enExample)
JP (1) JP5328792B2 (enExample)
KR (1) KR101509628B1 (enExample)
CN (1) CN101918925B (enExample)
TW (1) TWI451330B (enExample)
WO (1) WO2009032275A1 (enExample)

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US9268721B2 (en) 2010-11-25 2016-02-23 International Business Machines Corporation Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US9063945B2 (en) * 2011-06-14 2015-06-23 International Business Machines Corporation Apparatus and method to copy data
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
CN105938447B (zh) * 2015-03-06 2018-12-14 华为技术有限公司 数据备份装置及方法
US10402337B2 (en) * 2017-08-03 2019-09-03 Micron Technology, Inc. Cache filter
US10725782B2 (en) 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
CN108304214B (zh) * 2017-12-13 2022-05-13 超聚变数字技术有限公司 一种立即数的完整性的校验方法及装置
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
US11561895B2 (en) 2019-09-05 2023-01-24 Advanced Micro Devices, Inc. Oldest operation wait time indication input into set-dueling
US12346265B2 (en) 2019-12-16 2025-07-01 Advanced Micro Devices, Inc. Cache line re-reference interval prediction using physical page address

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JPH0222751A (ja) * 1988-07-11 1990-01-25 Mitsubishi Electric Corp 優先順位決定手段
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH10198603A (ja) * 1997-01-08 1998-07-31 Canon Inc 情報処理システム及びその制御方法、情報処理装置
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6490656B1 (en) * 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
US6732238B1 (en) * 2001-06-08 2004-05-04 Tensilica, Inc. Set-associative cache memory having variable time decay rewriting algorithm
JP3988485B2 (ja) * 2002-02-25 2007-10-10 セイコーエプソン株式会社 キャッシュ回路、情報処理装置及び電子機器
US7062610B2 (en) * 2002-09-30 2006-06-13 Advanced Micro Devices, Inc. Method and apparatus for reducing overhead in a data processing system with a cache
US6901483B2 (en) * 2002-10-24 2005-05-31 International Business Machines Corporation Prioritizing and locking removed and subsequently reloaded cache lines
JP4009304B2 (ja) * 2003-09-19 2007-11-14 松下電器産業株式会社 キャッシュメモリおよびキャッシュメモリ制御方法
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JP4036206B2 (ja) * 2004-03-31 2008-01-23 日本電気株式会社 セットアソシアティブキャッシュシステム及びキャッシュメモリの制御方法
US8806103B2 (en) * 2004-04-28 2014-08-12 Hewlett-Packard Development Company, L.P. System and method for interleaving memory
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache

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TWI451330B (zh) 2014-09-01
CN101918925B (zh) 2017-05-03
KR20100054155A (ko) 2010-05-24
WO2009032275A1 (en) 2009-03-12
US20090063776A1 (en) 2009-03-05
JP2010538390A (ja) 2010-12-09
CN101918925A (zh) 2010-12-15
TW200912742A (en) 2009-03-16
KR101509628B1 (ko) 2015-04-08
EP2198370A1 (en) 2010-06-23
US7861041B2 (en) 2010-12-28
EP2198370B1 (en) 2012-07-11

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