JP2010538390A5 - - Google Patents

Download PDF

Info

Publication number
JP2010538390A5
JP2010538390A5 JP2010524027A JP2010524027A JP2010538390A5 JP 2010538390 A5 JP2010538390 A5 JP 2010538390A5 JP 2010524027 A JP2010524027 A JP 2010524027A JP 2010524027 A JP2010524027 A JP 2010524027A JP 2010538390 A5 JP2010538390 A5 JP 2010538390A5
Authority
JP
Japan
Prior art keywords
storage location
block storage
eligible
recently accessed
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010524027A
Other languages
English (en)
Japanese (ja)
Other versions
JP5328792B2 (ja
JP2010538390A (ja
Filing date
Publication date
Priority claimed from US11/849,515 external-priority patent/US7861041B2/en
Application filed filed Critical
Publication of JP2010538390A publication Critical patent/JP2010538390A/ja
Publication of JP2010538390A5 publication Critical patent/JP2010538390A5/ja
Application granted granted Critical
Publication of JP5328792B2 publication Critical patent/JP5328792B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

JP2010524027A 2007-09-04 2008-09-04 プロセッサの非常にアソシエティビティの高いキャッシュメモリ用のセカンドチャンス置換機構 Active JP5328792B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/849,515 2007-09-04
US11/849,515 US7861041B2 (en) 2007-09-04 2007-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor
PCT/US2008/010368 WO2009032275A1 (en) 2007-09-04 2008-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor

Publications (3)

Publication Number Publication Date
JP2010538390A JP2010538390A (ja) 2010-12-09
JP2010538390A5 true JP2010538390A5 (enExample) 2013-07-18
JP5328792B2 JP5328792B2 (ja) 2013-10-30

Family

ID=40002967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010524027A Active JP5328792B2 (ja) 2007-09-04 2008-09-04 プロセッサの非常にアソシエティビティの高いキャッシュメモリ用のセカンドチャンス置換機構

Country Status (7)

Country Link
US (1) US7861041B2 (enExample)
EP (1) EP2198370B1 (enExample)
JP (1) JP5328792B2 (enExample)
KR (1) KR101509628B1 (enExample)
CN (1) CN101918925B (enExample)
TW (1) TWI451330B (enExample)
WO (1) WO2009032275A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9268721B2 (en) 2010-11-25 2016-02-23 International Business Machines Corporation Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US9063945B2 (en) * 2011-06-14 2015-06-23 International Business Machines Corporation Apparatus and method to copy data
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
CN105938447B (zh) * 2015-03-06 2018-12-14 华为技术有限公司 数据备份装置及方法
US10402337B2 (en) * 2017-08-03 2019-09-03 Micron Technology, Inc. Cache filter
US10725782B2 (en) 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
CN108304214B (zh) * 2017-12-13 2022-05-13 超聚变数字技术有限公司 一种立即数的完整性的校验方法及装置
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
US11561895B2 (en) 2019-09-05 2023-01-24 Advanced Micro Devices, Inc. Oldest operation wait time indication input into set-dueling
US12346265B2 (en) 2019-12-16 2025-07-01 Advanced Micro Devices, Inc. Cache line re-reference interval prediction using physical page address

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0222751A (ja) * 1988-07-11 1990-01-25 Mitsubishi Electric Corp 優先順位決定手段
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH10198603A (ja) * 1997-01-08 1998-07-31 Canon Inc 情報処理システム及びその制御方法、情報処理装置
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6490656B1 (en) * 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
US6732238B1 (en) * 2001-06-08 2004-05-04 Tensilica, Inc. Set-associative cache memory having variable time decay rewriting algorithm
JP3988485B2 (ja) * 2002-02-25 2007-10-10 セイコーエプソン株式会社 キャッシュ回路、情報処理装置及び電子機器
US7062610B2 (en) * 2002-09-30 2006-06-13 Advanced Micro Devices, Inc. Method and apparatus for reducing overhead in a data processing system with a cache
US6901483B2 (en) * 2002-10-24 2005-05-31 International Business Machines Corporation Prioritizing and locking removed and subsequently reloaded cache lines
JP4009304B2 (ja) * 2003-09-19 2007-11-14 松下電器産業株式会社 キャッシュメモリおよびキャッシュメモリ制御方法
US7502887B2 (en) * 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
JP4036206B2 (ja) * 2004-03-31 2008-01-23 日本電気株式会社 セットアソシアティブキャッシュシステム及びキャッシュメモリの制御方法
US8806103B2 (en) * 2004-04-28 2014-08-12 Hewlett-Packard Development Company, L.P. System and method for interleaving memory
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache

Similar Documents

Publication Publication Date Title
JP2010538390A5 (enExample)
US11237972B2 (en) Method and apparatus for controlling cache line storage in cache memory
US7814276B2 (en) Data cache architecture and cache algorithm used therein
US8898424B2 (en) Memory address translation
US10860495B2 (en) Storage circuitry responsive to a tag-matching command
JP3620473B2 (ja) 共有キャッシュメモリのリプレイスメント制御方法及びその装置
US10120750B2 (en) Cache memory, error correction circuitry, and processor system
US9189423B2 (en) Method and apparatus for controlling cache refills
US20100318742A1 (en) Partitioned Replacement For Cache Memory
US8180965B2 (en) System and method for cache access prediction
US20150364191A1 (en) Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency
US20130238856A1 (en) System and Method for Cache Organization in Row-Based Memories
US8583873B2 (en) Multiport data cache apparatus and method of controlling the same
US20190095331A1 (en) Multi-level system memory with near memory capable of storing compressed cache lines
US10108549B2 (en) Method and apparatus for pre-fetching data in a system having a multi-level system memory
US6823426B2 (en) System and method of data replacement in cache ways
US9846647B2 (en) Cache device and control method threreof
US10176096B2 (en) Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
US7975093B2 (en) Cache with high access store bandwidth
JP2008529181A5 (enExample)
US10783083B2 (en) Cache management device, system and method
US20160378671A1 (en) Cache memory system and processor system
US20180018122A1 (en) Providing memory bandwidth compression using compression indicator (ci) hint directories in a central processing unit (cpu)-based system
US20130042076A1 (en) Cache memory access method and cache memory apparatus
KR102710288B1 (ko) 비트 카운터를 이용하는 컴퓨팅 시스템 및 방법