TWI451330B - 快取記憶體系統以及快取資料取代之方法 - Google Patents

快取記憶體系統以及快取資料取代之方法 Download PDF

Info

Publication number
TWI451330B
TWI451330B TW097132347A TW97132347A TWI451330B TW I451330 B TWI451330 B TW I451330B TW 097132347 A TW097132347 A TW 097132347A TW 97132347 A TW97132347 A TW 97132347A TW I451330 B TWI451330 B TW I451330B
Authority
TW
Taiwan
Prior art keywords
storage location
block storage
count value
appropriate
cache memory
Prior art date
Application number
TW097132347A
Other languages
English (en)
Chinese (zh)
Other versions
TW200912742A (en
Inventor
James D Williams
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200912742A publication Critical patent/TW200912742A/zh
Application granted granted Critical
Publication of TWI451330B publication Critical patent/TWI451330B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/124—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being minimized, e.g. non MRU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW097132347A 2007-09-04 2008-08-25 快取記憶體系統以及快取資料取代之方法 TWI451330B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/849,515 US7861041B2 (en) 2007-09-04 2007-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor

Publications (2)

Publication Number Publication Date
TW200912742A TW200912742A (en) 2009-03-16
TWI451330B true TWI451330B (zh) 2014-09-01

Family

ID=40002967

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097132347A TWI451330B (zh) 2007-09-04 2008-08-25 快取記憶體系統以及快取資料取代之方法

Country Status (7)

Country Link
US (1) US7861041B2 (enExample)
EP (1) EP2198370B1 (enExample)
JP (1) JP5328792B2 (enExample)
KR (1) KR101509628B1 (enExample)
CN (1) CN101918925B (enExample)
TW (1) TWI451330B (enExample)
WO (1) WO2009032275A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI758654B (zh) * 2017-08-03 2022-03-21 美商美光科技公司 快取篩選器

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9268721B2 (en) 2010-11-25 2016-02-23 International Business Machines Corporation Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US9063945B2 (en) * 2011-06-14 2015-06-23 International Business Machines Corporation Apparatus and method to copy data
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
CN105938447B (zh) * 2015-03-06 2018-12-14 华为技术有限公司 数据备份装置及方法
US10725782B2 (en) 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
CN108304214B (zh) * 2017-12-13 2022-05-13 超聚变数字技术有限公司 一种立即数的完整性的校验方法及装置
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
US11561895B2 (en) 2019-09-05 2023-01-24 Advanced Micro Devices, Inc. Oldest operation wait time indication input into set-dueling
US12346265B2 (en) 2019-12-16 2025-07-01 Advanced Micro Devices, Inc. Cache line re-reference interval prediction using physical page address

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200407709A (en) * 2002-09-30 2004-05-16 Advanced Micro Devices Inc Method and apparatus for reducing overhead in a data processing system with a cache
TW200411389A (en) * 2002-10-24 2004-07-01 Ibm Weighted cache line replacement
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
US20050223173A1 (en) * 2004-03-31 2005-10-06 Nec Corporation Set associative cache system and control method for cache memories

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0222751A (ja) * 1988-07-11 1990-01-25 Mitsubishi Electric Corp 優先順位決定手段
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH10198603A (ja) * 1997-01-08 1998-07-31 Canon Inc 情報処理システム及びその制御方法、情報処理装置
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6490656B1 (en) * 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6732238B1 (en) * 2001-06-08 2004-05-04 Tensilica, Inc. Set-associative cache memory having variable time decay rewriting algorithm
JP3988485B2 (ja) * 2002-02-25 2007-10-10 セイコーエプソン株式会社 キャッシュ回路、情報処理装置及び電子機器
JP4009304B2 (ja) * 2003-09-19 2007-11-14 松下電器産業株式会社 キャッシュメモリおよびキャッシュメモリ制御方法
US7502887B2 (en) * 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
US8806103B2 (en) * 2004-04-28 2014-08-12 Hewlett-Packard Development Company, L.P. System and method for interleaving memory
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
TW200407709A (en) * 2002-09-30 2004-05-16 Advanced Micro Devices Inc Method and apparatus for reducing overhead in a data processing system with a cache
TW200411389A (en) * 2002-10-24 2004-07-01 Ibm Weighted cache line replacement
US20050223173A1 (en) * 2004-03-31 2005-10-06 Nec Corporation Set associative cache system and control method for cache memories

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI758654B (zh) * 2017-08-03 2022-03-21 美商美光科技公司 快取篩選器

Also Published As

Publication number Publication date
JP5328792B2 (ja) 2013-10-30
CN101918925B (zh) 2017-05-03
KR20100054155A (ko) 2010-05-24
WO2009032275A1 (en) 2009-03-12
US20090063776A1 (en) 2009-03-05
JP2010538390A (ja) 2010-12-09
CN101918925A (zh) 2010-12-15
TW200912742A (en) 2009-03-16
KR101509628B1 (ko) 2015-04-08
EP2198370A1 (en) 2010-06-23
US7861041B2 (en) 2010-12-28
EP2198370B1 (en) 2012-07-11

Similar Documents

Publication Publication Date Title
TWI451330B (zh) 快取記憶體系統以及快取資料取代之方法
US6496902B1 (en) Vector and scalar data cache for a vector multiprocessor
US6725343B2 (en) System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
EP0734553B1 (en) Split level cache
USRE45078E1 (en) Highly efficient design of storage array utilizing multiple pointers to indicate valid and invalid lines for use in first and second cache spaces and memory subsystems
US9513904B2 (en) Computer processor employing cache memory with per-byte valid bits
US8180981B2 (en) Cache coherent support for flash in a memory hierarchy
US9384134B2 (en) Persistent memory for processor main memory
CN101493796B (zh) 存储器内、页面内目录高速缓存一致性配置
US20100318741A1 (en) Multiprocessor computer cache coherence protocol
US8185692B2 (en) Unified cache structure that facilitates accessing translation table entries
US20060155934A1 (en) System and method for reducing unnecessary cache operations
JP2006517040A (ja) キャッシュラインサイズが異なる第一レベルキャッシュと第二レベルキャッシュを備えたマイクロプロセッサ
CN101727405A (zh) 虚拟地址高速缓冲存储器和方法以及处理器
EP2866148B1 (en) Storage system having tag storage device with multiple tag entries associated with same data storage line for data recycling and related tag storage device
US8639885B2 (en) Reducing implementation costs of communicating cache invalidation information in a multicore processor
TWI235916B (en) Multilevel cache structure and method using multiple issue algorithm with over subscription avoidance for high bandwidth cache pipeline
CN101727406B (zh) 组相联方式的高速缓存装置、高速缓存方法及处理器系统
CN105027137B (zh) 用于针对增强型安全检查的页走查扩展的装置和方法
US6507892B1 (en) L1 cache memory
US7882309B2 (en) Method and apparatus for handling excess data during memory access
US20090006777A1 (en) Apparatus for reducing cache latency while preserving cache bandwidth in a cache subsystem of a processor
US6240487B1 (en) Integrated cache buffers
US10013352B2 (en) Partner-aware virtual microsectoring for sectored cache architectures
Kandalkar et al. High Performance Cache Architecture Using Victim Cache