KR101509628B1 - 프로세서의 하이 어소시에이티브 캐시 메모리를 위한 ｓｃｒ 매커니즘 - Google Patents

프로세서의 하이 어소시에이티브 캐시 메모리를 위한 ｓｃｒ 매커니즘 Download PDF

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KR101509628B1
KR101509628B1 KR20107007196A KR20107007196A KR101509628B1 KR 101509628 B1 KR101509628 B1 KR 101509628B1 KR 20107007196 A KR20107007196 A KR 20107007196A KR 20107007196 A KR20107007196 A KR 20107007196A KR 101509628 B1 KR101509628 B1 KR 101509628B1
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KR20100054155A (ko
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제임스 디. 윌리암스
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/124—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being minimized, e.g. non MRU

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR20107007196A 2007-09-04 2008-09-04 프로세서의 하이 어소시에이티브 캐시 메모리를 위한 ｓｃｒ 매커니즘 Active KR101509628B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/849,515 2007-09-04
US11/849,515 US7861041B2 (en) 2007-09-04 2007-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor
PCT/US2008/010368 WO2009032275A1 (en) 2007-09-04 2008-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor

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KR20100054155A KR20100054155A (ko) 2010-05-24
KR101509628B1 true KR101509628B1 (ko) 2015-04-08

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US (1) US7861041B2 (enExample)
EP (1) EP2198370B1 (enExample)
JP (1) JP5328792B2 (enExample)
KR (1) KR101509628B1 (enExample)
CN (1) CN101918925B (enExample)
TW (1) TWI451330B (enExample)
WO (1) WO2009032275A1 (enExample)

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US9268721B2 (en) 2010-11-25 2016-02-23 International Business Machines Corporation Holding by a memory controller multiple central processing unit memory access requests, and performing the multiple central processing unit memory requests in one transfer cycle
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US9063945B2 (en) * 2011-06-14 2015-06-23 International Business Machines Corporation Apparatus and method to copy data
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
CN105938447B (zh) * 2015-03-06 2018-12-14 华为技术有限公司 数据备份装置及方法
US10402337B2 (en) * 2017-08-03 2019-09-03 Micron Technology, Inc. Cache filter
US10725782B2 (en) * 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
CN108304214B (zh) * 2017-12-13 2022-05-13 超聚变数字技术有限公司 一种立即数的完整性的校验方法及装置
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
US11561895B2 (en) 2019-09-05 2023-01-24 Advanced Micro Devices, Inc. Oldest operation wait time indication input into set-dueling
US12346265B2 (en) 2019-12-16 2025-07-01 Advanced Micro Devices, Inc. Cache line re-reference interval prediction using physical page address

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US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement

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US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH10198603A (ja) * 1997-01-08 1998-07-31 Canon Inc 情報処理システム及びその制御方法、情報処理装置
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6490656B1 (en) 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6732238B1 (en) 2001-06-08 2004-05-04 Tensilica, Inc. Set-associative cache memory having variable time decay rewriting algorithm
JP3988485B2 (ja) * 2002-02-25 2007-10-10 セイコーエプソン株式会社 キャッシュ回路、情報処理装置及び電子機器
US7062610B2 (en) * 2002-09-30 2006-06-13 Advanced Micro Devices, Inc. Method and apparatus for reducing overhead in a data processing system with a cache
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JP4036206B2 (ja) * 2004-03-31 2008-01-23 日本電気株式会社 セットアソシアティブキャッシュシステム及びキャッシュメモリの制御方法
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Also Published As

Publication number Publication date
CN101918925B (zh) 2017-05-03
TWI451330B (zh) 2014-09-01
TW200912742A (en) 2009-03-16
KR20100054155A (ko) 2010-05-24
WO2009032275A1 (en) 2009-03-12
US20090063776A1 (en) 2009-03-05
CN101918925A (zh) 2010-12-15
JP2010538390A (ja) 2010-12-09
EP2198370A1 (en) 2010-06-23
US7861041B2 (en) 2010-12-28
JP5328792B2 (ja) 2013-10-30
EP2198370B1 (en) 2012-07-11

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