JP5326256B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device suitable for a ferroelectric memory.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, with respect to semiconductor memory devices, for example, in order to realize high integration of DRAM, as a capacitor insulating film of a capacitor element constituting the DRAM, a ferroelectric material or a high material is used instead of conventional silicon oxide or silicon nitride. Technologies using dielectric materials have been widely researched and developed.

  In addition, in order to realize a nonvolatile RAM that can perform a write operation and a read operation at a lower voltage and at a higher speed, a technique using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been actively researched and developed. Yes. Such a semiconductor memory device is called a ferroelectric memory (FeRAM).

  A ferroelectric memory stores information using the hysteresis characteristics of a ferroelectric. A ferroelectric memory is provided with a ferroelectric capacitor, and the ferroelectric capacitor is configured such that a ferroelectric film is sandwiched between a pair of electrodes as a capacitive dielectric film. The ferroelectric film generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. Further, if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read by detecting this spontaneous polarization. A ferroelectric memory operates at a lower voltage than a flash memory, and can be written at high speed with low power consumption. Then, use of a logic embedded chip (SoC: System on Chip) having a ferroelectric memory for an IC card or the like is being studied.

As the ferroelectric film, a PZT-based material film, a Bi layered structure compound film, or the like is used. Examples of the PZT-based material include lead zirconate titanate (PZT) itself and those obtained by doping a PZT film with La, Ca, Sr and / or Si. Examples of the Bi layer structure compound include SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ), and the like. The ferroelectric film is formed in an amorphous state or a fine equiaxed crystal (microcrystal) state on the lower electrode film by a sol-gel method or a sputtering method, and is then columnarized by heat treatment. Further, it may be formed in a columnar crystallized state on the lower electrode by MOCVD (Metal Organic Chemical Vapor Deposition) method.

  In addition, as a material for the electrode, a metal that is difficult to oxidize or a conductive oxide is used. For example, platinum, iridium, iridium oxide, etc. are mentioned. That is, platinum group metals or oxides thereof are mainly used. In addition, aluminum is mainly used as a wiring material.

  However, when a ferroelectric film is formed by a sol-gel method or a sputtering method, it is necessary to make the structure of the lower electrode complicated in order to increase the orientation or suppress the leakage current. In particular, in the case of the sol-gel method, it may be difficult to obtain a sufficient amount of switching charge. Further, when a ferroelectric film is formed by the MOCVD method, irregularities are likely to be formed on the surface thereof, and it is difficult to obtain a sufficient amount of switching charge, and process deterioration may occur.

JP 11-292626 A JP 2001-127262 A JP 2000-91270 A JP 2002-246564 A JP 2005-183842 A JP 2006-73648 A JP 2001-237392 A JP 2003-218325 A JP 2004-153006 A JP 2004-296735 A Japanese Patent Laid-Open No. 2004-221469 JP-A-9-260612 JP-A-5-347391 JP 2000-82792 A JP 2000-31403 A JP 2006-216837 A JP 2002-57297 A JP 2006-278550 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of satisfactorily aligning a ferroelectric film without making the structure of a lower electrode complicated even when a sputtering method is mainly employed. is there.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

In the method for manufacturing the semiconductor device, a lower electrode film formed above the substrate, then on the lower electrode film, a first ferroelectric film, metal organic chemical vapor deposition or metal organic decomposition method To form. Next, an amorphous second ferroelectric film having a film thickness larger than that of the first ferroelectric film is formed on the first ferroelectric film by a sputtering method or a sol-gel method. Next, a part of the second ferroelectric film is crystallized, and a third ferroelectric film is formed on the second ferroelectric film crystallized by the sputtering method or sol-gel method. To do. Next, a conductive film is formed on the third ferroelectric film. Then, after forming the conductive film, the second ferroelectric film and the third ferroelectric film are crystallized.

  According to the present invention, since the capacitive insulating film is composed of at least two layers and the formation method thereof is appropriately defined, the orientation of the capacitive insulating film can be adjusted without complicating the structure of the lower electrode film. It can be good.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of each memory cell of the ferroelectric memory will be described together with its manufacturing method.

(First reference example )
First , a first reference example will be described. 1A to 1S are sectional views sequentially showing the steps of producing the ferroelectric memory according to the first reference example (semiconductor device).

In the first reference example , first, as shown in FIG. 1A, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type semiconductor substrate 31. An element isolation insulating film 32 is formed by embedding an insulating film such as silicon oxide therein. Note that an element isolation insulating film may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, ap well 33 is formed by introducing a p-type impurity into the active region. Next, the gate insulating film 34 is formed by thermally oxidizing the surface of the active region. Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the semiconductor substrate 31, and this is patterned by a photolithography technique to form the gate electrode 35. At this time, the two gate electrodes 35 are arranged in parallel with each other on the p-well 33. These gate electrodes 35 function as part of the word line of the memory.

  Next, the extension layer 36 is formed on both sides of the gate electrode 35 by introducing n-type impurities (ion implantation) using the gate electrode 35 as a mask. Thereafter, an insulating film is formed on the entire upper surface of the semiconductor substrate 31 and etched back to form an insulating sidewall 38 beside the gate electrode 35. As the insulating film, for example, a silicon oxide film is formed by a CVD method.

  Subsequently, impurity diffusion layers 37 are formed on both sides of the gate electrode 35 by introducing n-type impurities (ion implantation) using the sidewall 38 and the gate electrode 35 as a mask. The two sets of extension layer 36 and impurity diffusion layer 37 constitute the source and drain of the MOS transistor.

  Next, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the semiconductor substrate 31 by sputtering, and this refractory metal layer is heated to react with silicon. As a result, a refractory metal silicide layer 39 is formed on the gate electrode 35, and a refractory metal silicide layer 40 is formed on the impurity diffusion layer 37. Then, the unreacted refractory metal layer on the element isolation insulating film 32 and the like is removed by wet etching.

  Next, for example, a silicon oxynitride film 41 having a thickness of about 200 nm is formed on the entire upper surface of the semiconductor substrate 31 by plasma CVD. Next, a silicon oxide film 42 having a thickness of about 1000 nm is formed on the silicon oxynitride film 41 by, for example, a plasma CVD method using TEOS gas as a source gas. Thereafter, the upper surface of the silicon oxide film 42 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. In this planarization, the thickness of the silicon oxide film 42 is set to about 700 nm from the upper surface of the semiconductor substrate 31.

  Next, a contact hole exposing the silicide layer 40 is formed by patterning the silicon oxide film 42 and the silicon oxynitride film 41 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film (adhesion film) 43 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 44 is formed in the contact hole and on the silicon oxide film 42. The thickness of the W film 44 is about 300 nm from the upper surface of the silicon oxide film 42. Subsequently, by performing CMP, the glue film 43 and the W film 44 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 43 and the W film 44 on the silicon oxide film 42 are completely removed.

  Next, for example, a silicon oxynitride film 45 having a thickness of about 130 nm is formed as an antioxidant film on the silicon oxide film 42 and the contact plug by plasma CVD. Further, a silicon oxide film 46 having a thickness of about 300 nm is formed on the silicon oxynitride film 45 by, for example, a plasma CVD method using TEOS gas as a source gas. A silicon nitride film or an aluminum oxide film may be formed as the antioxidant film instead of the silicon oxynitride film 45.

  Next, as shown in FIG. 1B, a contact hole exposing the silicide layer 40 is formed by patterning the silicon oxide film 46 and the silicon oxynitride film 45 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film 47 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and side portions of the contact hole. Thereafter, a tungsten film (W film) 48 is formed in the contact hole and on the silicon oxide film 46. The thickness of the W film 48 is about 300 nm from the upper surface of the silicon oxide film 46. Subsequently, by performing CMP, the glue film 47 and the W film 48 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 47 and the W film 48 on the silicon oxide film 46 are completely removed by overpolishing. As the slurry, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 46 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 46. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the semiconductor substrate 31 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the semiconductor substrate 31 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the semiconductor substrate 31 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

Next, a Ti film having a thickness of about 20 nm is formed on the silicon oxide film 46 and the contact plug. In the formation of the Ti film, for example, a sputtering apparatus in which a target is provided at a position separated from the semiconductor substrate 31 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 5 seconds in a state where the set temperature of the semiconductor substrate 31 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. In this reference example , since the surface of the silicon oxide film 46 is subjected to NH ₃ plasma treatment before the Ti film is formed, the Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film 46 is thus captured. The surface of the can be moved freely. As a result, the Ti film is self-organized and its surface is strongly oriented in the (002) plane. Thereafter, by performing RTA (Rapid Thermal Annealing) at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film is changed to a TiN film 51 whose surface is strongly oriented to the (111) plane as shown in FIG. 1C. .

Subsequently, a TiAlN film 52 having a thickness of about 100 nm is formed on the TiN film 51 as an oxygen diffusion barrier film, for example, by reactive sputtering. At this time, for example, a target obtained by alloying Ti and Al is used. The set temperature of the semiconductor substrate 31 is 400 ° C., the pressure in the chamber is 253.3 Pa, Ar is supplied at a flow rate of 40 sccm, and N ₂ is supplied at a flow rate of 10 sccm. The sputter power is, for example, 1.0 kW.

  Next, an Ir film 53 having a thickness of 60 nm to 100 nm is formed on the TiAlN film 52 by sputtering, for example. At this time, the set temperature of the semiconductor substrate 31 is 450 ° C., the pressure in the chamber is 0.2 Pa, and the atmosphere in the chamber is an Ar atmosphere. The sputter power is, for example, 0.3 kW. The Ir film 53 is oriented in the (111) plane in order to take over the orientation of the TiN film 51. Further, instead of the Ir film 53, a film of a metal belonging to the platinum group (Ru, Rh, Pd or the like) may be formed.

  Next, the crystallinity of the Ir film 53 is improved by performing RTA at 650 ° C. to 750 ° C. for 60 seconds in an atmosphere of an inert gas such as Ar. Further, the RTA improves the adhesion between the TiN film 51, the TiAlN film 52, and the Ir film 53.

Thereafter, as shown in FIG. 1D, an Ir oxide film 54 having a thickness of 5 to 50 nm (for example, 25 nm) is formed on the Ir film 53 by sputtering, for example. The degree of oxidation of the Ir oxide film 54 is set lower than the stoichiometric composition. Further, as the Ir oxide film 54, an amorphous film is formed or a film made of fine equiaxed crystals is formed. Note that the Ir oxide film 54 is oriented in the (111) plane in order to take over the orientation of the Ir film 53. In forming such an Ir oxide film 54, for example, the set temperature of the semiconductor substrate 31 is 20 ° C. to 300 ° C., the pressure in the chamber is 0.11 Pa, and the atmosphere in the chamber is a mixed atmosphere of Ar and oxygen. . The sputter power is, for example, 1 kW, and the ratio of O ₂ gas in the sputter gas is 2% to 30%.

Subsequently, the semiconductor substrate 31 on which the Ir oxide film 54 and the like are formed is placed on a stage in a chamber of an MOCVD (metal organic chemical vapor deposition) apparatus. Next, the temperature of the semiconductor substrate 31 is raised to 620 ° C. while supplying, for example, 2000 sccm of O ₂ gas into the chamber. During this temperature rise, the Ir oxide film 54 is further oxidized almost uniformly and becomes columnar crystals.

When the temperature of the semiconductor substrate 31 reaches 620 ° C., the flow rate of the gas supplied into the chamber is changed. For example, the flow rate of Ar gas is 1375 sccm, and the flow rate of O ₂ gas is 625 sccm.

Next, a large amount of Pb, Zr, and Ti raw materials are supplied into the chamber so that the amount of O ₂ gas in the chamber is insufficient for forming the PZT (Pb [Zr, Ti] O ₃ ) film. For example, a large amount of Pb, Zr, and Ti materials are supplied into the chamber so that the amount of O ₂ in the chamber is 0.33 times the amount required for forming the PZT film. Further, the pressure in the chamber is set to 665 Pa.

In this reference example , for example, the following three types of liquid raw materials are prepared. First, a liquid raw material for Pb in which tetrakisdimethyl heptanedionate lead (Pb (DMHD) ₂ ) is dissolved in butyl acetate at a concentration of 0.2 mol / L is prepared. Second, a liquid raw material for Zr in which tetrakisdimethyl heptanedionate zirconium (Zr (DMHD) ₄ ) is dissolved in butyl acetate at a concentration of 0.1 mol / L is prepared. Thirdly, a liquid raw material for Ti in which bisisopropoxybisdipivaloylmethanate titanium (Ti (O-iPr) ₂ (DPM) ₂ ) is dissolved in butyl acetate at a concentration of 0.1 mol / L is prepared. Keep it. These liquid raw materials are supplied together with a butyl acetate solvent to the vaporizer of the MOCVD apparatus so that the total flow rate is 1.2 mL / min.

When Pb, Zr, and Ti raw materials are supplied into the chamber under such conditions, excess Pb, Zr, and Ti with respect to the O ₂ gas begin to combine with oxygen in the Ir oxide film 54. As a result, as shown in FIG. 1E, the Ir oxide film 54 is reduced, and the whole is changed to an Ir film 54a made of columnar crystals. The crystal constituting the Ir film 54 a is smaller than the crystal constituting the Ir film 53. In parallel with this change, an initial PZT film 55a in which oxygen is less than the stoichiometric composition is formed on the Ir film 54a by the MOCVD method. The Ir film 54a is oriented in the (111) plane similarly to the Ir oxide film 54, and the initial PZT film 55a is also oriented in the (111) plane. The initial PZT film 55a has a thickness of, for example, 2.5 nm to 10 nm.

  If an initial PZT film 55a having a thickness of less than 2.5 nm is to be formed, it is difficult to ensure time for sufficiently reducing the Ir oxide film 54. For this reason, the orientation of the initial PZT film 55a may be insufficient. On the other hand, when the thickness of the initial PZT film 55a exceeds 10 nm, the influence of oxygen deficiency or the like increases, and it may be difficult to secure a sufficient amount of switching charge.

After the initial PZT film 55a having a predetermined thickness is formed, the supply of Pb, Zr, and Ti raw materials is stopped and the flow rate of the gas supplied into the chamber is changed. For example, the supply of Ar gas is also stopped, and the flow rate of O ₂ gas is set to 4500 sccm.

Next, Pb, Zr, and Ti raw materials are supplied into the chamber at the same flow rate as when the initial PZT film 55a is formed. Further, the set temperature of the semiconductor substrate 31 is kept at 620 ° C., and the pressure in the chamber is kept at 665 Pa. However, since the flow rate of O ₂ gas is 4500 sccm, unlike the formation of the initial PZT film 55a, the amount of O ₂ in the chamber is more than the amount required for forming the PZT film (for example, 6. 77 times).

  When Pb, Zr and Ti raw materials are supplied into the chamber under such conditions, an intermediate PZT film 55b containing sufficient oxygen is formed on the initial PZT film 55a by MOCVD as shown in FIG. 1F. The intermediate PZT film 55b is oriented in the (111) plane in order to take over the orientation of the initial PZT film 55a. The thickness of the intermediate PZT film 55b is, for example, 7.5 nm to 10 nm, and the total thickness of the initial PZT film 55a and the intermediate PZT film 55b is about 20 nm. The initial PZT film 55a and the intermediate PZT film 55b may be formed by a metal organic decomposition (MOD) method.

The formation speed of the intermediate PZT film 55b is set higher than the formation speed of the initial PZT film 55a. For example, the formation rate of the initial PZT film 55a is preferably 0.1 nm / second or less, more preferably 0.05 nm / second or less, and even more preferably 0.04 nm / second or less. On the other hand, the formation speed of the intermediate PZT film 55b is preferably 0.17 nm / second. If the formation rate of the initial PZT film 55a exceeds 0.1 nm / second, the surface of the intermediate PZT film 55b tends to be rough, and the switching charge amount of the ferroelectric capacitor may be lowered. For example, when the initial PZT film 55a is formed at a speed of 0.1 nm / second or less, a switching charge amount of 40 μC / cm ² is obtained, whereas the initial PZT film 55a is formed at a speed of 0.17 nm / second. If formed, the switching charge may be 32 μC / cm ² .

  Regarding the formation speed of the initial PZT film 55a and the intermediate PZT film 55b, it is preferable to adjust the flow rates of the butyl acetate solvent and the liquid raw materials in forming them according to the formation speed of the PZT film. For example, when forming at a rate of 0.04 nm / second, the flow rate of the butyl acetate solvent is 0.95 mL / min, the flow rate of the Pb liquid source is 0.1 mL / min, and the flow rate of the Zr liquid source is The flow rate of the liquid raw material for Ti is 0.08 mL / min. For example, when forming at a rate of 0.17 nm / second, the flow rate of the butyl acetate solvent is 0.30 mL / min, the flow rate of the liquid raw material for Pb is 0.26 mL / min, The flow rate is 0.34 mL / min, and the flow rate of the liquid raw material for Ti is 0.30 mL / min.

After the intermediate PZT film 55b having a predetermined thickness is formed, an amorphous ferroelectric film 55c is formed by sputtering as shown in FIG. 1F. In this case, for example, the temperature of the semiconductor substrate 31 is 50 ° C., the sputtering power is 1 kW, and the pressure in the chamber of the RF sputtering apparatus in an argon atmosphere is 1.0 Pa. At this time, the component of the ferroelectric film 55c (for example, the Pb amount of PZT) can be adjusted by controlling the flow rate of the argon gas. The material of the ferroelectric film 55c is not particularly limited. For example, the ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and at least one selected from rare earth elements, B = A ferroelectric material of at least one selected from Ti, Zr, Nb, Ta, W, Mn, Fe, Co, and Cr) is used. In particular, for example, PZT (CSPLZT) to which 5 mol% of Ca, 2 mol% of La, and 2.5 mol% of Sr are added is preferable. The crystal structure of these materials corresponds to an ABO ₃ type perovskite structure as a unit. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they do not have to be the same in each unit. The same applies to the B atom. The thickness of the ferroelectric film 55c is 70 nm to 250 nm (for example, 100 nm). A capacitor insulating film 55 is composed of the initial PZT film 55a, the intermediate PZT film 55b, and the ferroelectric film 55c. In place of the ferroelectric material, a high dielectric material such as oxide Zr or Pb-based material may be used.

Next, rapid thermal annealing (RTA) under normal pressure is performed in an oxygen atmosphere or an oxygen atmosphere containing an inert gas, thereby forming the entire capacitor insulating film 55 into columnar crystals. In this RTA, it is preferable to raise the semiconductor substrate 31 to a temperature (for example, 570 ° C.) higher by 15 ° C. to 60 ° C. than the crystallization temperature of the capacitive insulating film 55. The upper limit of this temperature is, for example, 620 ° C. For example, the flow rate of Ar gas is 1980 sccm, the flow rate of O ₂ gas is 25 sccm, and the time is 90 seconds. Since the crystallization of the capacitive insulating film 55 occurs from the interface with the Ir film 53, the capacitive insulating film 55 takes over the orientation of the Ir film 53. If this temperature is too low, crystallization of the capacitor insulating film 55 becomes insufficient, and sufficient orientation may not be obtained. On the other hand, if the temperature is too high, the surface of the capacitive insulating film 55 may start to crystallize early, and the orientation is likely to be disturbed. Moreover, the temperature increase rate at the time of this RTA shall be 40 to 150 degree-C / min (for example, 125 degreeC).

  Note that RTA may be performed under reduced pressure. In this case, it is preferable to raise the semiconductor substrate 31 to a range from a temperature 5 ° C. lower than the crystallization temperature of the capacitive insulating film 55 to a temperature 50 ° C. higher than the crystallization temperature.

Next, as shown in FIG. 1G, an Ir oxide film 56 having a thickness of 50 nm is formed on the capacitor insulating film 55 by, eg, sputtering. At this time, the set temperature of the semiconductor substrate 31 is set to 300 ° C., Ar is supplied into the chamber at a flow rate of 140 sccm, and O ₂ is supplied at a flow rate of 60 sccm. Further, the sputter power is, for example, about 1 kW to 2 kW. Instead of the Ir oxide film 56, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

Next, R ₂ is performed at 725 ° C. for 60 seconds while supplying O ₂ at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm into the chamber, so that the entire capacitor insulating film 55 is converted into a columnar crystal. To do. In addition, the plasma damage of the Ir oxide film 56 is recovered by this RTA, and oxygen vacancies in the capacitor insulating film 55 are compensated.

Thereafter, an Ir oxide film 57 having a thickness of 50 nm to 100 nm is formed on the Ir oxide film 56 by sputtering, for example. When the atmosphere in the chamber is a mixed atmosphere of Ar and O ₂ , the pressure in the chamber is 0.8 Pa, and the sputtering power is 1.0 kW, the thickness of the Ir oxide film 57 becomes about 125 nm in about 45 seconds. The composition of the Ir oxide film 57 is preferably closer to the stoichiometric composition of IrO ₂ than the composition of the Ir oxide film 56. This is because such a composition suppresses the catalytic action against hydrogen, suppresses the problem that the capacitive insulating film 55 is reduced by hydrogen radicals, and improves the hydrogen resistance of the ferroelectric capacitor. . The temperature of the semiconductor substrate 31 when forming the Ir oxide film 57 is preferably 100 ° C. or lower. This is to suppress abnormal growth of the Ir oxide film 57. Further, instead of the Ir oxide film 57, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

  Next, as shown in FIG. 1H, an Ir film 58 having a thickness of 50 nm to 100 nm is formed on the Ir oxide film 57 by sputtering, for example, for the purpose of suppressing hydrogen diffusion and process deterioration. At this time, the atmosphere in the chamber is an Ar atmosphere, the pressure in the chamber is 1 Pa, and the sputtering power is 1.0 kW. In place of the Ir film 58, a noble metal film such as a Pt film, Ru film, Rh film, or Pd film may be formed. Further, an alloy film such as a TiNi film, a TiAl film, or a TaAl film may be formed.

  Thereafter, backside cleaning is performed in order to remove the material of the PZT film attached to the backside of the semiconductor substrate 31. Subsequently, as shown in FIG. 1I, a titanium nitride film (TiN film) 61 and a silicon oxide film 62 are sequentially formed on the Ir film 58. The TiN film 61 is formed by sputtering, for example. The silicon oxide film 62 is formed by, for example, a CVD method using TEOS gas. Instead of the TiN film 61, a TiAlN film may be formed.

  Next, as shown in FIG. 1J, the silicon oxide film 62 is patterned into an island shape.

  Next, as shown in FIG. 1K, the TiN film 61 is etched using the silicon oxide film 62 as a mask. As a result, a hard mask composed of the island-like TiN film 61 and the silicon oxide film 62 is formed.

Next, using the TiN film 61 and the silicon oxide film 62 as a mask, plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas is performed using an Ir film 58, an Ir oxide film 57, The process is performed on the Ir oxide film 56, the capacitor insulating film 55, the Ir film 54a, and the Ir film 53. As a result, the upper electrode 63 is formed.

  Subsequently, as shown in FIG. 1L, the silicon oxide film 62 is removed by dry etching or wet etching.

Next, as shown in FIG. 1M, the TiAlN film 52 and the TiN film 51 are patterned by performing dry etching using the Ir film 58 or the like as a mask. In this reference example , the lower electrode 60 is composed of the Ir film 54a, the Ir film 53, the TiAlN film 52, and the TiN film 51. Note that the TiAlN film 52 and the TiN film 51 can be regarded as barrier metal films.

  Next, as shown in FIG. 1N, a protective film 65 covering the ferroelectric capacitor is formed on the silicon oxide film 46. As the protective film 65, an aluminum oxide film having a thickness of about 20 nm is formed by sputtering, for example. As the protective film 65, an aluminum oxide film having a thickness of 2 nm to 5 nm may be formed by MOCVD.

Thereafter, as shown in FIG. 1O, recovery annealing is performed in an oxygen-containing atmosphere in order to recover the damage of the ferroelectric film. The conditions for this recovery annealing are not particularly limited. For example, the set temperature of the semiconductor substrate 31 is set to 550 ° C. to 700 ° C. In particular, when the capacitive insulating film 55 as in this reference example is formed, recovery annealing is performed in an oxygen atmosphere at 600 ° C. for 60 minutes.

  Thereafter, as shown in FIG. 1P, a new protective film 66 is formed on the protective film 65. As the protective film 66, an aluminum oxide film having a thickness of 30 nm to 40 nm is formed by, for example, a CVD method.

  Next, as shown in FIG. 1Q, a silicon oxide film 67 having a thickness of about 1500 nm is formed as an interlayer insulating film on the protective film 66 by, for example, plasma TEOSCVD. At this time, for example, a mixed gas composed of TEOS gas, oxygen gas, and helium gas is used as the source gas. Thereafter, the surface of the silicon oxide film 67 is planarized by, eg, CMP. Note that as the interlayer insulating film, for example, an insulating inorganic film or the like may be formed.

Subsequently, heat treatment is performed in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result, moisture in the silicon oxide film 67 is removed, and the film quality of the silicon oxide film 67 changes, so that it is difficult for moisture to enter the silicon oxide film 67.

  Thereafter, a protective film (barrier film) 68 is formed on the silicon oxide film 67 by, for example, sputtering or CVD. As the protective film 68, for example, an aluminum oxide film having a thickness of 20 nm to 100 nm is formed. Since the protective film 68 is formed on the planarized silicon oxide film 67, the protective film 68 also becomes flat.

  Next, a silicon oxide film 69 having a thickness of 300 nm to 500 nm is formed as an interlayer insulating film on the protective film 68 by, for example, plasma TEOSCVD. Thereafter, the surface of the silicon oxide film 69 is planarized by, eg, CMP. Note that a silicon oxynitride film, a silicon nitride film, or the like may be formed as the interlayer insulating film.

  Next, as shown in FIG. 1R, the silicon oxide film 69, the protective film 68, and the silicon oxide film 67 are patterned by photolithography to form a contact hole that exposes the upper electrode 63. Thereafter, heat treatment is performed in an oxygen atmosphere at 550 ° C. to recover oxygen vacancies generated in the capacitor insulating film 55 when the contact holes are formed. Subsequently, a filling material is formed in the contact hole, and a silicon oxide film 69, a protective film 68, a silicon oxide film 67, a protective film 66, a protective film 65, a silicon oxide film 46, and silicon oxynitride are formed by photolithography. By patterning the film 45, a contact hole exposing the contact plug made of the glue film 43 and the W film 44 is formed.

Next, the embedding material is removed, and a glue film (adhesion film) 70 is formed by sequentially forming a Ti film and a TiN film on the bottom and sides of each contact hole. At this time, for example, a Ti film is formed by sputtering, and a TiN film is formed thereon by MOCVD. However, when the TiN film is formed by the MOCVD method, a treatment in a plasma of a mixed gas of nitrogen and hydrogen is required to remove carbon from the TiN film. In this reference example , since the outermost surface of the upper electrode 63 is the Ir film 58, the upper electrode 63 is not reduced even if this plasma treatment is performed. Further, only the TiN film may be formed as the glue film 70.

  Thereafter, a tungsten film (W film) 71 is formed in the contact hole and on the silicon oxide film 69. The thickness of the W film 71 is about 300 nm from the upper surface of the silicon oxide film 69. Subsequently, by performing CMP, the glue film 70 and the W film 71 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 70 and the W film 71 on the silicon oxide film 69 are completely removed by overpolishing.

  Subsequently, as shown in FIG. 1S, a wiring composed of a Ti film 72, a TiN film 73, an AlCu film 74, a TiN film 75, and a Ti film 76 is formed on the silicon oxide film 69 and the contact plug. In forming the wiring, for example, by sputtering, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are used. Films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

According to the first reference example , since the thin initial PZT film 55a is formed on the lower electrode 60 which can be easily formed with a simple structure, a thick ferroelectric film 55c is formed thereon by sputtering. Even if formed, the orientation of the capacitor insulating film 55 becomes good. That is, since the initial PZT film 55a takes over the orientation of the Ir films 53 and 54a, the capacitive insulating film 55 having a good orientation can be obtained. Further, when the Ir film 54a and the ferroelectric film 55c formed by the sputtering method are in contact with each other, the leakage current increases with the diffusion of Ir. In this reference example , the initial PZT film 55a is formed by the MOCVD method. Therefore, the leakage current is suppressed. Further, the effect of suppressing the leakage current is further strengthened by the intermediate PZT film 55b. Furthermore, since the ferroelectric film 55c formed by the sputtering method occupies most of the capacitive insulating film 55, the surface irregularities are suppressed.

Here, FIG. 6 shows a flowchart of the process of forming the ferroelectric capacitor in the first reference example . In contrast to such a first reference example , in the embodiment, as shown in FIG. 7A, after annealing, a further ferroelectric film is formed by sputtering or sol-gel method. The composition of this ferroelectric film is, for example, the same as that of the ferroelectric film 55c. The thickness is about 10 nm to 40 nm (for example, 20 nm to 30 nm). If this ferroelectric film is too thick, subsequent crystallization tends to be insufficient, and low voltage operation may be difficult, and the switching charge may be reduced. By providing such a ferroelectric film, the interface with the upper electrode can be made more stable.

Further, as shown in FIG. 7B, the formation of the intermediate PZT film 55b in the first reference example may be omitted.

  Further, as shown in FIG. 8A, with respect to the example shown in FIG. 7A, after the ferroelectric film 55c is annealed, another ferroelectric film is formed by MOCVD at a temperature of about 620 ° C. It may be formed. The thickness of the ferroelectric film is, for example, about 70 nm to 120 nm. By providing such a ferroelectric film, surface irregularities are further suppressed. After this, it is preferable to perform a heat treatment at 620 ° C. to 640 ° C. in an oxygen-containing atmosphere before forming the ferroelectric film by the final sputtering method. By this heat treatment, moisture and impurities attached to the surface of the ferroelectric film formed by the MOCVD method are released from the atmosphere, and the electrical characteristics are improved.

  Further, as shown in FIG. 8B, the formation of the intermediate PZT film 55b in the example shown in FIG. 8A may be omitted. However, although the intermediate PZT film 55b may be omitted as described above, it is preferable to provide the intermediate PZT film 55b having a thickness of 5 nm to 15 nm in order to more reliably suppress the diffusion of Ir. Regardless of the presence or absence of the intermediate PZT film 55b, the total thickness of the initial PZT film 55a and the intermediate PZT film 55b is preferably 2 nm to 20 nm.

(Second reference example )
Next , a second reference example will be described. 2A to 2C are sectional views sequentially showing the steps of producing the ferroelectric memory according to a second reference example (semiconductor device).

In the second reference example , first, similarly to the first reference example , the surface of the silicon oxide film 46 is processed up to NH ₃ plasma processing. However, in forming a contact plug composed of the glue film 47 and the W film 48, as shown in FIG. 2A, a recess 80 may be formed on the surface of the contact plug. The depth of the recess 80 is, for example, about 20 nm to 50 nm.

When the same processing as in the first reference example is performed with such a recess 80 present, a recess reflecting the recess 80 is formed on the surface of the TiN film 51 and the like, and the orientation of the capacitive insulating film 55 is lowered. Sometimes. Therefore, in the second reference example , as shown in FIG. 2B, a Ti film 81 having a thickness of about 100 nm is formed on the silicon oxide film 46 and the contact plug. In forming the Ti film 81, for example, a sputtering apparatus in which a target is provided at a position separated from the semiconductor substrate 31 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 35 seconds in a state where the set temperature of the semiconductor substrate 31 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. Also in this reference example , since the NH ₃ plasma treatment is performed on the surface of the silicon oxide film 46 before the Ti film 81 is formed, the Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film The surface of 46 can be moved freely. As a result, the Ti film 81 is self-organized and its surface is strongly oriented in the (002) plane.

  Thereafter, the surface of the Ti film 81 is planarized by, eg, CMP. The thickness of the planarized Ti film 81 is, for example, 50 nm to 100 nm from the surface of the silicon oxide film 46. This thickness control is performed by time control, for example.

Subsequently, the surface of the Ti film 81 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 81 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 81. Next, as in the first reference example , by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 2C, the Ti film was TiN whose surface was strongly oriented to the (111) plane. The film 51 is used.

Thereafter, similarly to the first reference example , the processing after the formation of the TiAlN film 52 is performed.

According to such a second reference example , a ferroelectric capacitor having good characteristics can be obtained even when the recess 80 is formed.

(Third reference example )
Next , a third reference example will be described. Figures 3A and 3B are sectional views sequentially showing the steps of producing the ferroelectric memory according to the third reference example (semiconductor device).

In the third reference example , first, similarly to the second reference example , processing up to the formation of the Ti film 81 is performed. Thereafter, as shown in FIG. 3A, the surface of the Ti film 81 is planarized by, eg, CMP, until the surface of the silicon oxide film 46 is exposed. That is, unlike the second reference example , the Ti film 81 on the silicon oxide film 46 is completely removed.

Subsequently, similarly to the second reference example , the surface of the Ti film 81 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 81 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 81. Next, as in the first and second reference examples , by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 3B, the surface of the Ti film is strongly against the (111) plane. An oriented TiN film 51 is formed.

Thereafter, similarly to the first and second reference examples , the processing after the formation of the TiAlN film 52 is performed.

With such a third reference example, the same effect as the second reference example is obtained.

(Fourth reference example )
Next , a fourth reference example will be described. 4A to 4C are sectional views sequentially showing the steps of producing the ferroelectric memory according to the fourth reference example (semiconductor device).

In the fourth reference example , first, as shown in FIG. 4A, similarly to the first reference example , the processes up to the formation of the contact plug composed of the glue film 43 and the W film 44 are performed. However, the contact plug composed of the glue film 43 and the W film 44 is not formed on the silicide layer 40 shared by the two MOS transistors.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 42 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 42. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the semiconductor substrate 31 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the semiconductor substrate 31 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the semiconductor substrate 31 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

Next, as shown in FIG. 4B, a TiN film 51 is formed on the silicon oxide film 42 and the contact plug. The formation method of the TiN film 51 is the same as that of the first reference example . Thereafter, processing from the formation of the TiAlN film 52 to the formation of the protective film 66 is performed.

Thereafter, as shown in FIG. 4C, the silicon oxide film 67 is formed and planarized as in the first reference example . Next, contact holes reaching the silicide layer 40 shared by the two MOS transistors are formed in the silicon oxide film 67, the protective film 66, the protective film 65, the silicon oxide film 42, and the silicon oxynitride film 41. Then, a contact plug composed of the glue film 70 and the W film 71 is formed in the contact hole. Further, a hole exposing the upper electrode 63 is formed in a state where the contact plug is covered with an antioxidant film (not shown) or the like.

  Subsequently, wirings and pads made of a Ti film 72, a TiN film 73, an AlCu film 74, a TiN film 75, and a Ti film 76 are formed on the silicon oxide film 67, on the contact plug, and in the hole. In forming the wiring and pads, for example, a sputtering method is used to form a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a thickness of 70 nm. TiN films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

According to such a fourth reference example , the ferroelectric capacitor can be completed with fewer steps than the first reference example .

In any embodiment and reference example , the ferroelectric film 55c may be formed by a sol-gel method. The material of the initial PZT film 55a and the intermediate PZT film 55b is, for example, an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr and at least one selected from rare earth elements, B = Ti, Zr, A ferroelectric material of at least one selected from Nb and Ta is used. Further, the content of impurities in each ferroelectric film is preferably 5 mol% or less for each element, and preferably 12 mol% or less as a whole.

Next, the results of experiments actually performed by the present inventors will be described. In this experiment, samples with different thicknesses of the initial PZT film 55a and the intermediate PZT film 55b were manufactured according to the first reference example . Table 1 shows the thicknesses of the initial PZT film 55a and the intermediate PZT film 55b of each sample.

A ferroelectric film 55c having a thickness of 90 nm was formed on the intermediate PZT film 55b by sputtering. Next, Ar gas was supplied into the chamber at a flow rate of 1980 sccm, O ₂ gas was supplied at a flow rate of 25 sccm, and RTA was performed at 570 ° C. for 90 seconds. Thereafter, another ferroelectric film having a thickness of 20 nm was formed by sputtering as in the example shown in FIG. Subsequently, an Ir oxide film constituting the upper electrode was formed and heat treatment was performed. Then, the entire crystal structure of the capacitive insulating film was analyzed by an X-ray diffraction method. This analysis was performed at three locations, the center portion and the right end portion when the orientation flat of the semiconductor substrate 31 was positioned at the lower end. The results are shown in FIGS. 5A to 5D. 5A shows the integrated intensity of orientation to the (100) plane, FIG. 5B shows the integrated intensity of orientation to the (101) plane, and FIG. 5C shows the integrated intensity of orientation to the (111) plane. FIG. 5D shows the orientation ratio of the (222) plane.

  As shown in FIGS. 5A to 5D, in any sample, the orientation to (100) and (101) was low, and the orientation to (111) was strong. For this reason, the orientation ratio to (222) was as good as 97% or more. From this result, good results can be obtained if the thickness of the initial PZT film 55a is 5 nm to 10 nm, and 2 nm to 12 nm is particularly preferable. If the initial PZT film 55a is too thick, there are relatively many oxygen vacancies in the initial PZT film 55a, making it difficult to obtain a high switching charge amount. On the other hand, if the initial PZT film 55a is too thin, it is difficult to stabilize the orientation of the ferroelectric film 55c.

  Patent Document 11 describes that after the formation of the PZT film by the MOCVD method, a perovskite crystallized PZT film is formed by the sputtering method. However, when the inventors of the present invention prepared samples by this method and observed the surfaces of these samples using an SEM, as shown in FIG. 9A, many irregularities were generated on the surface of the PZT film. Furthermore, when the cross section near the convex portion was observed using TEM, the crystals constituting the PZT film were not oriented to the (111) plane, as shown in FIG. 9B. Such a phenomenon was particularly remarkable at the peripheral portion of the wafer. The main cause is considered to be that a crystallized PZT film is formed by a sputtering method.

It is a cross-sectional view showing a manufacturing method of a ferroelectric memory according to the first embodiment. FIG. 1B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1A. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1B. FIG. 2C is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1C. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1D. FIG. 2E is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1E. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1F. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1G. 1H is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1H. FIG. 11 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1I; FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1J. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1K. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1L. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1M. 1N is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1N; FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 10. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1P. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1Q. FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1R; It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 2nd reference example . FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 2A. FIG. 2B is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2B. It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 3rd reference example . FIG. 3B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 3A. It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 4th reference example . FIG. 4B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4A. FIG. 4B is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 4B. It is a graph which shows the integrated intensity | strength of the orientation to a (100) plane. It is a graph which shows the integrated intensity | strength of the orientation to a (101) plane. It is a graph which shows the integrated intensity | strength of the orientation to a (111) plane. It is a graph which shows the orientation rate of a (222) plane. It is a flowchart which shows the outline | summary of a reference example . Is a flowchart showing an overview of an embodiment of the present invention. It is a flowchart which shows the outline | summary of the modification of a reference example . It is a figure which shows the SEM photograph of the sample manufactured by the conventional method. It is a figure which shows the other SEM photograph of the sample manufactured by the conventional method.

Explanation of symbols

55: Capacitance insulating film 55a: Initial PZT film 55b: Intermediate PZT film 55c: Ferroelectric film

Claims (3)

Forming a lower electrode film above the substrate;
On the lower electrode film, a first ferroelectric film, forming by metal organic chemical vapor deposition or metal organic decomposition method,
Forming an amorphous second ferroelectric film having a thickness larger than that of the first ferroelectric film on the first ferroelectric film by a sputtering method or a sol-gel method;
Crystallization of a part of the second ferroelectric film;
Forming a third ferroelectric film on the second ferroelectric film obtained by crystallizing the part by a sputtering method or a sol-gel method;
Forming a conductive film on the third ferroelectric film;
Crystallizing the second ferroelectric film and the third ferroelectric film after forming the conductive film;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the first ferroelectric film is 2 nm to 20 nm. The step of forming the first ferroelectric film includes:
Forming a first oxide ferroelectric film;
Forming a second oxide ferroelectric film having an oxygen concentration higher than that of the first oxide ferroelectric film on the first oxide ferroelectric film;
The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that it has a.

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