JP5200581B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method thereof.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, with respect to semiconductor memory devices, for example, in order to realize high integration of DRAM, as a capacitor insulating film of a capacitor element constituting the DRAM, a ferroelectric material or a high material is used instead of conventional silicon oxide or silicon nitride. Technologies using dielectric materials have been widely researched and developed.

  In addition, in order to realize a nonvolatile RAM that can perform a write operation and a read operation at a lower voltage and at a higher speed, a technique using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been actively researched and developed. Yes. Such a semiconductor memory device is called a ferroelectric memory (FeRAM).

  A ferroelectric memory stores information using the hysteresis characteristics of a ferroelectric. A ferroelectric memory is provided with a ferroelectric capacitor, and the ferroelectric capacitor is configured such that a ferroelectric film is sandwiched between a pair of electrodes as a capacitive dielectric film. The ferroelectric film generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. Further, if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read by detecting this spontaneous polarization. A ferroelectric memory operates at a lower voltage than a flash memory, and can be written at high speed with low power consumption. Then, use of a logic embedded chip (SoC: System on Chip) having a ferroelectric memory for an IC card or the like is being studied.

As the ferroelectric film, a PZT-based material film, a Bi layered structure compound film, or the like is used. Examples of the PZT-based material include lead zirconate titanate (PZT) itself and those obtained by doping a PZT film with La, Ca, Sr and / or Si. Examples of the Bi layer structure compound include SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ), and the like. The ferroelectric film is formed in an amorphous state or a fine equiaxed crystal (microcrystal) state on the lower electrode film by a sol-gel method or a sputtering method, and is then columnarized by heat treatment. Further, it may be formed in a columnar crystallized state on the lower electrode by MOCVD (Metal Organic Chemical Vapor Deposition) method.

  In addition, as a material for the electrode, a metal that is difficult to oxidize or a conductive oxide is used. For example, platinum, iridium, iridium oxide, etc. are mentioned. That is, platinum group metals or oxides thereof are mainly used. In addition, aluminum is mainly used as a wiring material.

The structure of the ferroelectric capacitor is roughly divided into a planar type structure and a stack type structure. Of these, the stack type structure is suitable for miniaturization. In the stack structure, the lower electrode is composed of a plurality of conductive films. Examples of such a conductive film include a TiN film, a TiAlN film, an Ir film, an IrO ₂ film, a Pt film, and a SrRuO ₃ film. A part of the conductive film also functions as a barrier metal film that prevents oxidation of the contact plug located under the lower electrode.

  The characteristics (especially switching charge amount) and yield of a ferroelectric capacitor often depend on the orientation of columnar crystals constituting the ferroelectric film. The orientation of the columnar layer is easily affected by the orientation of the surface of the lower electrode. Therefore, in order to improve the characteristics and the yield, it is necessary to appropriately control the orientation of the crystals constituting the lower electrode.

  Various proposals have been made regarding the structure of the lower electrode. However, so far, nothing can sufficiently contribute to improving the characteristics and yield of the ferroelectric capacitor.

JP 2005-159165 A JP 2003-197874 A JP 2001-237392 A JP 2002-151656 A JP 2002-261251 A JP 2000-91270 A JP 2003-68991 A JP 2004-253627 A JP 2003-282844 A US Pat. No. 6,600,688 US Pat. No. 6,528,328 US Pat. No. 6,548,343 US Pat. No. 6,596,547 US Pat. No. 6,635,497 US Pat. No. 6,686,236 US Pat. No. 6,872,669 US Pat. No. 6,287,637 US Pat. No. 6,617,626 B2 US Pat. No. 6,627,930 B1 JP 2001-28426 A JP-A-8-273436 JP 2000-31407 A JP 2003-218325 A JP 2002-368200 A JP 2003-46064 A JP 2003-142659 A JP 2006-41425 A Japanese Patent No. 2923753 JP 2003-324101 A Appl. Phys. Lett., Vol. 77, No. 19, P.3036 (2000) Jpn. J. Appl. Phys. Lett., Vol. 32, No. 9B, P.4168 (1993) Jpn. J. Appl. Phys. Lett., Vol. 33, No. 9B, P.5211 (1994)

Patent Document 29 described above discloses that a PZT film has a two-layer structure. However, when the inventors of the present invention have verified this technique, it has been difficult to obtain sufficient characteristics although the intended purpose has been achieved. For example, the orientation of the PZT film was not sufficient, and the variation in orientation was large. The results of this verification are shown in FIGS. 19A to 19D. FIG. 19A shows the integrated intensity of orientation to the (111) plane at the center of the wafer, and FIG. 19B shows the integrated intensity of orientation to the (111) plane at the periphery of the wafer. FIG. 19C shows the orientation rate of the (222) plane at the center of the wafer, and FIG. 19D shows the orientation rate of the (222) plane at the peripheral portion of the wafer. Here, the orientation ratio is expressed as “I ₂₂₂ when the orientation strength to the (222) plane is represented by I ₂₂₂ , the orientation strength to the (100) plane is represented by I ₁₀₀ , and the orientation strength to the (101) plane is represented by I _101. / (I ₁₀₀ + I ₁₀₁ + I ₂₂₂ ) ”. As shown in FIGS. 19A to 19D, the orientation toward the (111) plane was low overall, and the orientation in the peripheral portion was particularly low.

  Moreover, when the surface of these samples was observed using SEM, as shown to FIG. 20A, many unevenness | corrugations had arisen on the surface of the PZT film | membrane. Furthermore, when the cross section near the convex portion was observed using SEM, as shown in FIG. 20B, the crystals constituting the PZT film were not oriented in the (111) plane. Such a phenomenon was particularly remarkable at the peripheral portion of the wafer.

  As a result of intensive studies to find out the cause, the inventor of the present application has found that the crystal orientation in the surface layer portion of the lower electrode is not uniform as in other conventional techniques.

  An object of the present invention is to provide a semiconductor device capable of obtaining a high switching charge amount based on the presence of a dielectric film having excellent orientation and a method for manufacturing the same.

In the method for manufacturing a semiconductor device according to the present invention, a lower electrode is formed above a substrate, an oxide dielectric film is formed on the lower electrode, and an upper electrode is formed on the oxide dielectric film. Then, when forming the lower electrode, a first noble metal film is formed, and then a noble metal oxide film is formed on the first noble metal film. In forming the oxide dielectric film, a lower layer film is formed on the noble metal oxide film by metal organic chemical vapor deposition, and the noble metal oxide film is changed to a second noble metal film by reduction. Thereafter, a core film that is thicker than the lower layer film and higher in oxidation degree than the lower layer film is formed on the lower layer film at a deposition rate higher than the deposition rate of the lower layer film. The crystal grains constituting the second noble metal film are smaller than the crystal grains constituting the first noble metal film.

  The semiconductor device according to the present invention includes a lower electrode formed above a substrate, an oxide dielectric film formed on the lower electrode, an upper electrode formed on the oxide dielectric film, Is provided. The lower electrode is in contact with the first noble metal film, the upper surface of the first noble metal film and the lower surface of the oxide dielectric film, and has a second crystal grain size smaller than that of the first noble metal film. And a noble metal film. The oxide dielectric film includes a lower layer film in contact with the upper surface of the second noble metal film, a core in contact with the upper surface of the lower layer film, thicker than the lower layer film, and higher in oxidation degree than the lower layer film. And a membrane.

  According to the present invention, since the configuration of the lower electrode and the dielectric film is made appropriate, it is possible to obtain a good alignment with little variation. For this reason, a high switching charge amount can be obtained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of each memory cell of the ferroelectric memory will be described together with its manufacturing method.

(First embodiment)
First, a first embodiment of the present invention will be described. 1A to 1S are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps.

  In the first embodiment, first, as shown in FIG. 1A, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon substrate 1. An element isolation insulating film 2 is formed by embedding an insulating film such as silicon oxide therein. Note that an element isolation insulating film may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, a p-type impurity is introduced into the active region to form a p-well 3. Next, the gate insulating film 4 is formed by thermally oxidizing the surface of the active region. Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1 and patterned by a photolithography technique to form the gate electrode 5. At this time, two gate electrodes 5 are arranged in parallel with each other on the p-well 3. These gate electrodes 5 function as part of the word lines of the memory.

  Next, the extension layer 6 is formed on both sides of the gate electrode 5 by introducing n-type impurities (ion implantation) using the gate electrode 5 as a mask. Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 and etched back to form insulating sidewalls 8 beside the gate electrode 5. As the insulating film, for example, a silicon oxide film is formed by a CVD method.

  Subsequently, impurity diffusion layers 7 are formed on both sides of the gate electrode 5 by introducing n-type impurities (ion implantation) using the sidewall 8 and the gate electrode 5 as a mask. The two sets of extension layer 6 and impurity diffusion layer 7 constitute the source and drain of the MOS transistor.

  Next, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate 1 by sputtering, and the refractory metal layer is heated to react with silicon. As a result, a refractory metal silicide layer 9 is formed on the gate electrode 5, and a refractory metal silicide layer 10 is formed on the impurity diffusion layer 7. Then, the unreacted refractory metal layer on the element isolation insulating film 2 and the like is removed by wet etching.

  Next, for example, a silicon oxynitride film 11 having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 1 by plasma CVD. Next, a silicon oxide film 12 having a thickness of about 1000 nm is formed on the silicon oxynitride film 11 by, for example, a plasma CVD method using TEOS gas as a source gas. Thereafter, the upper surface of the silicon oxide film 12 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. In this planarization, the thickness of the silicon oxide film 12 is set to about 700 nm from the upper surface of the silicon substrate 1.

  Next, a contact hole exposing the silicide layer 10 is formed by patterning the silicon oxide film 12 and the silicon oxynitride film 11 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film (adhesion film) 13 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 14 is formed in the contact hole and on the silicon oxide film 12. The thickness of the W film 14 is about 300 nm from the upper surface of the silicon oxide film 12. Subsequently, by performing CMP, the glue film 13 and the W film 14 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 13 and the W film 14 on the silicon oxide film 12 are completely removed.

  Next, for example, a silicon oxynitride film 15 having a thickness of about 130 nm is formed as an antioxidant film on the silicon oxide film 12 and the contact plug by plasma CVD. Further, a silicon oxide film 16 having a thickness of about 300 nm is formed on the silicon oxynitride film 15 by, for example, a plasma CVD method using TEOS gas as a source gas. A silicon nitride film or an aluminum oxide film may be formed as an antioxidant film instead of the silicon oxynitride film 15.

  Next, as shown in FIG. 1B, a contact hole exposing the silicide layer 10 is formed by patterning the silicon oxide film 16 and the silicon oxynitride film 15 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film 17 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 18 is formed in the contact hole and on the silicon oxide film 16. The thickness of the W film 18 is about 300 nm from the upper surface of the silicon oxide film 16. Subsequently, by performing CMP, the glue film 17 and the W film 18 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 17 and the W film 18 on the silicon oxide film 16 are completely removed by overpolishing. As the slurry, for example, SSW2000 manufactured by Cabot Microelectronics Corporation is used.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 16 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 16. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the silicon substrate 1 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the silicon substrate 1 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the silicon substrate 1 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

Next, a Ti film having a thickness of about 20 nm is formed on the silicon oxide film 16 and the contact plug. In the formation of the Ti film, for example, a sputtering apparatus in which a target is provided at a position separated from the silicon substrate 1 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 5 seconds in a state where the set temperature of the silicon substrate 1 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. In the present embodiment, since the surface of the silicon oxide film 16 is subjected to NH ₃ plasma treatment before the Ti film is formed, Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film 16 The surface of the can be moved freely. As a result, the Ti film is self-organized and its surface is strongly oriented in the (002) plane. Thereafter, by performing RTA (Rapid Thermal Annealing) at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film is changed to a TiN film 21 whose surface is strongly oriented to the (111) plane as shown in FIG. 1C. .

Subsequently, a TiAlN film 22 having a thickness of about 100 nm is formed as an oxygen diffusion barrier film on the TiN film 21 by, for example, reactive sputtering. At this time, for example, a target obtained by alloying Ti and Al is used. The set temperature of the silicon substrate 1 is 400 ° C., the pressure in the chamber is 253.3 Pa, Ar is supplied at a flow rate of 40 sccm, and N ₂ is supplied at a flow rate of 10 sccm. The sputter power is, for example, 1.0 kW.

  Next, an Ir film 23 having a thickness of 60 nm to 100 nm is formed as a first noble metal film on the TiAlN film 22 by, for example, sputtering. At this time, the set temperature of the silicon substrate 1 is 450 ° C., the pressure in the chamber is 0.2 Pa, and the atmosphere in the chamber is an Ar atmosphere. The sputter power is, for example, 0.3 kW. Note that the Ir film 23 is oriented in the (111) plane in order to take over the orientation of the TiN film 21. Further, instead of the Ir film 23, a film of a metal belonging to the platinum group (Ru, Rh, Pd or the like) may be formed.

  Next, RTA is performed at 650 ° C. to 750 ° C. for 60 seconds in an atmosphere of an inert gas such as Ar, thereby improving the crystallinity of the Ir film 23. In addition, the adhesion between the TiN film 21, the TiAlN film 22, and the Ir film 23 is improved by this RTA.

Thereafter, as shown in FIG. 1D, an Ir oxide film 24 having a thickness of 5 to 50 nm (for example, 25 nm) is formed as a noble metal oxide on the Ir film 23 by, eg, sputtering. The degree of oxidation of the Ir oxide film 24 is set lower than the stoichiometric composition. As the Ir oxide film 24, an amorphous film is formed, or a film made of fine equiaxed crystals is formed. Note that the Ir oxide film 24 is oriented in the (111) plane in order to take over the orientation of the Ir film 23. In forming such an Ir oxide film 24, for example, the set temperature of the silicon substrate 1 is set to 20 ° C. to 300 ° C., the pressure in the chamber is set to 0.11 Pa, and the atmosphere in the chamber is set to a mixed atmosphere of Ar and oxygen. . The sputter power is, for example, 1 kW, and the ratio of O ₂ gas in the sputter gas is 2% to 30%.

Subsequently, the silicon substrate 1 on which the Ir oxide film 24 and the like are formed is placed on a stage in a chamber of a MOCVD (metal organic chemical vapor deposition) apparatus. Next, the silicon substrate 1 is heated to 620 ° C. while supplying, for example, 2000 sccm of O ₂ gas into the chamber. During this temperature increase, the Ir oxide film 24 is further uniformly oxidized to form columnar crystals.

When the temperature of the silicon substrate 1 reaches 620 ° C., the flow rate of the gas supplied into the chamber is changed. For example, the flow rate of Ar gas is 1375 sccm, and the flow rate of O ₂ gas is 625 sccm.

Next, a large amount of Pb, Zr, and Ti raw materials are supplied into the chamber so that the amount of O ₂ gas in the chamber is insufficient for forming the PZT (Pb [Zr, Ti] O ₃ ) film. For example, a large amount of Pb, Zr, and Ti materials are supplied into the chamber so that the amount of O ₂ in the chamber is 0.33 times the amount required for forming the PZT film. Further, the pressure in the chamber is set to 665 Pa.

In the present embodiment, for example, the following three types of liquid raw materials are prepared. First, a liquid raw material for Pb in which tetrakisdimethyl heptanedionate lead (Pb (DMHD) ₂ ) is dissolved in butyl acetate at a concentration of 0.2 mol / L is prepared. Second, a liquid raw material for Zr in which tetrakisdimethyl heptanedionate zirconium (Zr (DMHD) ₄ ) is dissolved in butyl acetate at a concentration of 0.1 mol / L is prepared. Thirdly, a liquid raw material for Ti in which bisisopropoxybisdipivaloylmethanate titanium (Ti (O-iPr) ₂ (DPM) ₂ ) is dissolved in butyl acetate at a concentration of 0.1 mol / L is prepared. Keep it. These liquid raw materials are supplied together with a butyl acetate solvent to the vaporizer of the MOCVD apparatus so that the total flow rate is 1.2 mL / min.

When Pb, Zr, and Ti raw materials are supplied into the chamber under such conditions, excess Pb, Zr, and Ti with respect to the O ₂ gas begin to combine with oxygen in the Ir oxide film 24. As a result, as shown in FIG. 1E, the Ir oxide film 24 is reduced, and the whole is changed to an Ir film 24a (second noble metal film) made of columnar crystals. The crystal constituting the Ir film 24a is smaller than the crystal constituting the Ir film 23. In parallel with this change, an initial PZT film 25a in which oxygen is less than the stoichiometric composition is formed as a lower layer film on the Ir film 24a by the MOCVD method. The Ir film 24a is oriented in the (111) plane similarly to the Ir oxide film 24, and the initial PZT film 25a is also oriented in the (111) plane. The initial PZT film 25a has a thickness of, for example, 2.5 nm to 10 nm.

  If an initial PZT film 25a having a thickness of less than 2.5 nm is to be formed, it is difficult to ensure time for sufficiently reducing the Ir oxide film 24. For this reason, the orientation of the initial PZT film 25a may be insufficient. On the other hand, when the thickness of the initial PZT film 25a exceeds 10 nm, the influence of oxygen deficiency or the like increases, and it may be difficult to secure a sufficient amount of switching charge.

After the initial PZT film 25a having a predetermined thickness is formed, the supply of Pb, Zr and Ti raw materials is stopped and the flow rate of the gas supplied into the chamber is changed. For example, the supply of Ar gas is also stopped, and the flow rate of O ₂ gas is set to 4500 sccm.

Next, Pb, Zr, and Ti raw materials are supplied into the chamber at the same flow rate as when the initial PZT film 25a is formed. Further, the set temperature of the silicon substrate 1 is kept at 620 ° C., and the pressure in the chamber is kept at 665 Pa. However, since the flow rate of the O ₂ gas is 4500 sccm, unlike the initial PZT film 25a, the amount of O ₂ in the chamber is larger than the amount required for forming the PZT film (for example, 6. 77 times).

  When raw materials of Pb, Zr and Ti are supplied into the chamber under such conditions, a core PZT film 25b containing sufficient oxygen is formed on the initial PZT film 25a as a core film by MOCVD as shown in FIG. 1F. Is done. The core PZT film 25b is oriented in the (111) plane in order to take over the orientation of the initial PZT film 25a. The thickness of the core PZT film 25b is, for example, 90 nm to 97.5 nm, and the total thickness of the initial PZT film 25a and the core PZT film 25b is about 100 nm.

The formation speed of the core PZT film 25b is set higher than the formation speed of the initial PZT film 25a. For example, the formation rate of the initial PZT film 25a is preferably 0.1 nm / second or less, more preferably 0.05 nm / second or less, and even more preferably 0.04 nm / second or less. On the other hand, the formation rate of the core PZT film 25b is preferably 0.17 nm / second. If the formation rate of the initial PZT film 25a exceeds 0.1 nm / second, the surface of the core PZT film 25b tends to be rough, and the switching charge amount of the ferroelectric capacitor may be lowered. For example, when the initial PZT film 25a is formed at a speed of 0.1 nm / second or less, a switching charge amount of 40 μC / cm ² is obtained, whereas the initial PZT film 25a is formed at a speed of 0.17 nm / second. If formed, the switching charge may be 32 μC / cm ² .

  Regarding the formation speed of the initial PZT film 25a and the core PZT film 25b, it is preferable to adjust the flow rates of the butyl acetate solvent and the liquid raw materials in forming them according to the formation speed of the PZT film. For example, when forming at a rate of 0.04 nm / second, the flow rate of the butyl acetate solvent is 0.95 mL / min, the flow rate of the Pb liquid source is 0.1 mL / min, and the flow rate of the Zr liquid source is The flow rate of the liquid raw material for Ti is 0.08 mL / min. For example, when forming at a rate of 0.17 nm / second, the flow rate of the butyl acetate solvent is 0.30 mL / min, the flow rate of the liquid raw material for Pb is 0.26 mL / min, The flow rate is 0.34 mL / min, and the flow rate of the liquid raw material for Ti is 0.30 mL / min.

  After the core PZT film 25b having a predetermined thickness is formed, an amorphous cap PZT film 25c is formed by sputtering, for example, as shown in FIG. 1F. The thickness of the cap PZT film 25c is 1 nm to 30 nm (for example, 20 nm).

  As a result, a PZT film 25 having a flat surface composed of the initial PZT film 25a, the core PZT film 25b, and the cap PZT film 25c is obtained.

Next, as shown in FIG. 1G, an Ir oxide film 26 having a thickness of 50 nm is formed on the PZT film 25 by sputtering, for example. At this time, the set temperature of the silicon substrate 1 is set to 300 ° C., Ar is supplied into the chamber at a flow rate of 140 sccm, and O ₂ is supplied at a flow rate of 60 sccm. Further, the sputter power is, for example, about 1 kW to 2 kW. Instead of the Ir oxide film 26, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

Next, while supplying O ₂ at a flow rate of 20 sccm into the chamber and performing RTA at 725 ° C. for 60 seconds while supplying Ar at a flow rate of 2000 sccm, the PZT film 25 is completely crystallized. In addition, the plasma damage of the Ir oxide film 26 is recovered by this RTA, and oxygen vacancies in the PZT film 25 are compensated.

Thereafter, an Ir oxide film 27 having a thickness of 50 nm to 100 nm is formed on the Ir oxide film 26 by, eg, sputtering. When the atmosphere in the chamber is a mixed atmosphere of Ar and O ₂ , the pressure in the chamber is 0.8 Pa, and the sputtering power is 1.0 kW, the thickness of the Ir oxide film 27 becomes about 125 nm in about 45 seconds. The composition of the Ir oxide film 27 is preferably closer to the stoichiometric composition of IrO ₂ than the composition of the Ir oxide film 26. This is because such a composition suppresses the catalytic action against hydrogen, suppresses the problem that the PZT film 25 is reduced by hydrogen radicals, and improves the hydrogen resistance of the ferroelectric capacitor. The temperature of the silicon substrate 1 when forming the Ir oxide film 27 is preferably 100 ° C. or lower. This is to suppress abnormal growth of the Ir oxide film 27. Further, instead of the Ir oxide film 27, an oxide film of Ru, Rh, Re, Os, or Pd may be formed. Further, a conductive oxide film such as a SrRuO ₃ film may be formed. Moreover, you may use what laminated | stacked these.

  Next, as shown in FIG. 1H, an Ir film 28 having a thickness of 50 nm to 100 nm is formed on the Ir oxide film 27 by sputtering, for example, for the purpose of suppressing hydrogen diffusion and process deterioration. At this time, the atmosphere in the chamber is an Ar atmosphere, the pressure in the chamber is 1 Pa, and the sputtering power is 1.0 kW. Instead of the Ir film 28, a noble metal film such as a Pt film, Ru film, Rh film, or Pd film may be formed. Further, an alloy film such as a TiNi film, a TiAl film, or a TaAl film may be formed.

  Thereafter, in order to remove the material of the PZT film adhering to the back surface of the silicon substrate 1, back surface cleaning is performed. Subsequently, as shown in FIG. 1I, a titanium nitride film (TiN film) 31 and a silicon oxide film 32 are sequentially formed on the Ir film 28. The TiN film 31 is formed by sputtering, for example. The silicon oxide film 32 is formed by, for example, a CVD method using TEOS gas. Instead of the TiN film 31, a TiAlN film may be formed.

  Next, as shown in FIG. 1J, the silicon oxide film 32 is patterned into an island shape.

  Next, as shown in FIG. 1K, the TiN film 31 is etched using the silicon oxide film 32 as a mask. As a result, a hard mask composed of the island-like TiN film 31 and the silicon oxide film 32 is formed.

Next, using the TiN film 31 and the silicon oxide film 32 as a mask, plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas is performed using the Ir film 28, the Ir oxide film 27, For the Ir oxide film 26, the PZT film 25, the Ir film 24a, and the Ir film 23. As a result, the upper electrode 33 is formed.

  Subsequently, as shown in FIG. 1L, the silicon oxide film 32 is removed by dry etching or wet etching.

  Next, as shown in FIG. 1M, the TiAlN film 22 and the TiN film 21 are patterned by performing dry etching using the Ir film 28 or the like as a mask. In the present embodiment, the lower electrode 30 is composed of the Ir film 24a, the Ir film 23, the TiAlN film 22 and the TiN film 21. Note that the TiAlN film 22 and the TiN film 21 can be regarded as barrier metal films.

  Next, as shown in FIG. 1N, a protective film 35 covering the ferroelectric capacitor is formed on the silicon oxide film 16. As the protective film 35, an aluminum oxide film having a thickness of about 20 nm is formed by sputtering, for example. As the protective film 35, an aluminum oxide film having a thickness of 2 nm to 5 nm may be formed by MOCVD.

  Thereafter, as shown in FIG. 1O, recovery annealing is performed in an oxygen-containing atmosphere in order to recover the damage of the ferroelectric film. The conditions for this recovery annealing are not particularly limited. For example, the set temperature of the silicon substrate 1 is set to 550 ° C. to 700 ° C. In particular, when the PZT film 25 is formed as a ferroelectric film as in this embodiment, recovery annealing is performed in an oxygen atmosphere at 600 ° C. for 60 minutes.

  Thereafter, as shown in FIG. 1P, a new protective film 36 is formed on the protective film 35. As the protective film 36, an aluminum oxide film having a thickness of 30 nm to 40 nm is formed by, for example, a CVD method.

  Next, as shown in FIG. 1Q, a silicon oxide film 37 having a thickness of about 1500 nm is formed as an interlayer insulating film on the protective film 36 by, for example, plasma TEOSCVD. At this time, for example, a mixed gas composed of TEOS gas, oxygen gas, and helium gas is used as the source gas. Thereafter, the surface of the silicon oxide film 37 is planarized by, eg, CMP. Note that as the interlayer insulating film, for example, an insulating inorganic film or the like may be formed.

Subsequently, heat treatment is performed in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result, moisture in the silicon oxide film 37 is removed, the film quality of the silicon oxide film 37 changes, and moisture hardly enters the silicon oxide film 37.

  Thereafter, a protective film (barrier film) 38 is formed on the silicon oxide film 37 by, for example, sputtering or CVD. As the protective film 38, for example, an aluminum oxide film having a thickness of 20 nm to 100 nm is formed. Since the protective film 38 is formed on the planarized silicon oxide film 37, the protective film 38 also becomes flat.

  Next, a silicon oxide film 39 having a thickness of 300 nm to 500 nm is formed as an interlayer insulating film on the protective film 38 by, for example, plasma TEOSCVD. Thereafter, the surface of the silicon oxide film 39 is planarized by, eg, CMP. Note that a silicon oxynitride film, a silicon nitride film, or the like may be formed as the interlayer insulating film.

  Next, as shown in FIG. 1R, a contact hole exposing the upper electrode 33 is formed by patterning the silicon oxide film 39, the protective film 38 and the silicon oxide film 37 by photolithography. Thereafter, heat treatment is performed in an oxygen atmosphere at 550 ° C. to recover oxygen vacancies generated in the PZT film 25 during contact hole formation. Subsequently, a filling material is formed in the contact hole, and the silicon oxide film 39, the protective film 38, the silicon oxide film 37, the protective film 36, the protective film 35, the silicon oxide film 16, and the silicon oxynitride are formed by photolithography. By patterning the film 15, a contact hole exposing the contact plug made of the glue film 13 and the W film 14 is formed.

  Next, the buried material is removed, and a glue film (adhesion film) 40 is formed by sequentially forming a Ti film and a TiN film on the bottom and sides of each contact hole. At this time, for example, a Ti film is formed by sputtering, and a TiN film is formed thereon by MOCVD. However, when the TiN film is formed by the MOCVD method, a treatment in a plasma of a mixed gas of nitrogen and hydrogen is required to remove carbon from the TiN film. In the present embodiment, since the outermost surface of the upper electrode 33 is the Ir film 28, the upper electrode 33 is not reduced even if this plasma treatment is performed. Further, only the TiN film may be formed as the glue film 40.

  Thereafter, a tungsten film (W film) 41 is formed in the contact hole and on the silicon oxide film 39. The thickness of the W film 41 is about 300 nm from the upper surface of the silicon oxide film 39. Subsequently, by performing CMP, the glue film 40 and the W film 41 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 40 and the W film 41 on the silicon oxide film 39 are completely removed.

  Subsequently, as shown in FIG. 1S, a wiring composed of a Ti film 42, a TiN film 43, an AlCu film 44, a TiN film 45, and a Ti film 46 is formed on the silicon oxide film 39 and the contact plug. In forming the wiring, for example, by sputtering, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are used. Films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

  In the first embodiment, since the initial PZT film 25a is formed while the Ir oxide film 24 is changed to the Ir film 24a by reduction, abnormal oxidation does not occur, and the orientation of the initial PZT film 25a is It will be very good. Further, the variation in orientation is suppressed, and the orientation ratio of the (222) plane of the core PZT film 25b that greatly affects the switching charge amount of the ferroelectric capacitor exceeds 90%. Therefore, a high yield can be obtained.

  The average grain size of the crystals constituting the Ir film 24a is smaller than the average grain size of the crystals constituting the Ir film 23, for example, 20 nm or less.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. 2A to 2C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention in the order of steps.

In the second embodiment, first, similarly to the first embodiment, the process up to the NH ₃ plasma process is performed on the surface of the silicon oxide film 16. However, in forming a contact plug composed of the glue film 17 and the W film 18, a recess 50 may be formed on the surface of the contact plug as shown in FIG. 2A. The depth of the recess 50 is, for example, about 20 nm to 50 nm.

If the same processing as in the first embodiment is performed with such a recess 50 present, a recess reflecting the recess 50 is formed on the surface of the TiN film 21 and the like, and the orientation of the PZT film 25 is lowered. There is. Therefore, in the second embodiment, as shown in FIG. 2B, a Ti film 51 having a thickness of about 100 nm is formed on the silicon oxide film 16 and the contact plug. In forming the Ti film 51, for example, a sputtering apparatus in which a target is provided at a position separated from the silicon substrate 1 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 35 seconds in a state where the set temperature of the silicon substrate 1 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. Also in this embodiment, since the surface of the silicon oxide film 16 is subjected to NH ₃ plasma treatment before the Ti film 51 is formed, Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film The surface of 16 can be moved freely. As a result, the Ti film 51 is self-organized and its surface is strongly oriented in the (002) plane.

  Thereafter, the surface of the Ti film 51 is planarized by, eg, CMP. The thickness of the planarized Ti film 51 is, for example, 50 nm to 100 nm from the surface of the silicon oxide film 16. This thickness control is performed by time control, for example.

Subsequently, the surface of the Ti film 51 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 51 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 51. Next, as in the first embodiment, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 2C, the Ti film is TiN whose surface is strongly oriented to the (111) plane. The film 21 is used.

  Thereafter, similarly to the first embodiment, processing after the formation of the TiAlN film 22 is performed.

  According to such a second embodiment, a ferroelectric capacitor having good characteristics can be obtained even when the recess 50 is formed.

(Third embodiment)
Next, a third embodiment of the present invention will be described. 3A and 3B are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention in the order of steps.

  In the third embodiment, first, similarly to the second embodiment, processing up to the formation of the Ti film 51 is performed. Thereafter, as shown in FIG. 3A, the surface of the Ti film 51 is flattened by, for example, a CMP method until the surface of the silicon oxide film 16 is exposed. That is, unlike the second embodiment, the Ti film 51 on the silicon oxide film 16 is completely removed.

Subsequently, similarly to the second embodiment, the surface of the Ti film 51 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 51 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 51. Next, as in the first and second embodiments, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film has a strong (111) surface as shown in FIG. 3B. The TiN film 21 is oriented.

  Thereafter, similarly to the first and second embodiments, the processing after the formation of the TiAlN film 22 is performed.

  According to the third embodiment, the same effect as that of the second embodiment can be obtained.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. 4A to 4C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the fourth embodiment of the present invention in the order of steps.

  In the fourth embodiment, first, as shown in FIG. 4A, similarly to the first embodiment, the processes up to the formation of the contact plug composed of the glue film 13 and the W film 14 are performed. However, the contact plug composed of the glue film 13 and the W film 14 is not formed on the silicide layer 10 shared by the two MOS transistors.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 12 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 12. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the silicon substrate 1 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the silicon substrate 1 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the silicon substrate 1 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

  Next, as shown in FIG. 4B, a TiN film 21 is formed on the silicon oxide film 12 and the contact plug. The method for forming the TiN film 21 is the same as that in the first embodiment. Thereafter, processing from the formation of the TiAlN film 22 to the formation of the protective film 36 is performed.

  Thereafter, as shown in FIG. 4C, the silicon oxide film 37 is formed and planarized in the same manner as in the first embodiment. Next, contact holes reaching the silicide layer 10 shared by the two MOS transistors are formed in the silicon oxide film 37, the protective film 36, the protective film 35, the silicon oxide film 12, and the silicon oxynitride film 11. Then, a contact plug composed of the glue film 40 and the W film 41 is formed in the contact hole. Further, a hole exposing the upper electrode 33 is formed in a state where the contact plug is covered with an antioxidant film (not shown) or the like.

  Subsequently, wirings and pads made of the Ti film 42, the TiN film 43, the AlCu film 44, the TiN film 45, and the Ti film 46 are formed on the silicon oxide film 37, the contact plug, and the hole. In forming the wiring and pads, for example, a sputtering method is used to form a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a thickness of 70 nm. TiN films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

  According to the fourth embodiment, the ferroelectric capacitor can be completed with fewer steps than the first embodiment.

  Note that the structure of the ferroelectric capacitor may be a planar structure instead of a stack structure. In this case, a Pt film or the like can be used as the lower electrode 30. Further, a titanium film, an aluminum oxide film, an aluminum nitride film, a TiAlN film, a tantalum oxide film, a titanium oxide film and / or a zirconium oxide film are preferably provided as an adhesion layer between the lower electrode 30 and the silicon oxide film 16. .

Further, as the oxide dielectric film, for example, a film having a Bi layer structure or a perovskite structure can be formed. Examples of such a film include a film represented by the general formula ABO ₃ such as PZT, SBT, BLT, and Bi-based layered compound doped with a small amount of La, Ca, Sr, and / or Si, in addition to the PZT film. . A dielectric film may be used in place of the ferroelectric film.

  In addition, some of the above-mentioned patent documents describe that a PZT film is formed on an iridium film by MOCVD. However, these techniques cannot avoid the oxidation of the surface of the Ir film at the initial stage of the formation of the PZT film, and the above effects cannot be obtained. In addition, there is a description that a PZT film is formed on an iridium oxide film by MOCVD. However, these techniques are not sufficiently reduced because the oxygen concentration in the iridium oxide film is set high. That is, the iridium oxide film cannot be changed to an iridium film, and the above effects cannot be obtained.

  Next, the results of experiments actually performed by the present inventors will be described.

(First experiment)
In the first experiment, the formation temperature of the Ir oxide film 24 was investigated. In the first experiment, an Ir oxide film 24 having a thickness of 30 nm was formed by using an Ar gas flow rate of 186 sccm, an O ₂ gas flow rate of 14 sccm (O ₂ ratio: 7%), a sputter power of 0.5 kW, and a formation rate: The film was formed on the Ir film 23 under the condition of 1.6 nm / second in the same manner as in the first embodiment (time: 19 seconds). Moreover, the temperature of the silicon substrate 1 was made into room temperature (25 degreeC), 50 degreeC, 100 degreeC, 100 degreeC, 200 degreeC, and 300 degreeC. Thereafter, both the initial PZT film 25a and the core PZT film 25b were formed at a rate of 0.17 nm / second by MOCVD. Further, a reference sample in which the initial PZT film 25a and the core PZT film 25b were directly formed on the Ir film 23 without forming the Ir oxide film 24 was also produced. Then, the crystal structure of the core PZT film 25b was analyzed by the X-ray diffraction method. This analysis was performed at three locations, a center portion, an upper end portion, and a right end portion when the orientation flat of the disc-shaped silicon substrate 1 was positioned at the lower end. The results are shown in FIGS. 5A to 5D. 5A shows the integrated intensity of orientation to the (100) plane, FIG. 5B shows the integrated intensity of orientation to the (101) plane, and FIG. 5C shows the integrated intensity of orientation to the (111) plane. FIG. 5D shows the orientation ratio of the (222) plane.

  As shown in FIGS. 5A to 5D, particularly good results were obtained when the Ir oxide film 24 was formed at room temperature to 100 ° C. That is, the orientation to the (100) plane and the orientation to the (101) plane were low, and the orientation to the (111) plane was high. Therefore, the orientation rate of (222) was high. Furthermore, the variation in orientation was low. This is because the Ir oxide film 24 formed at room temperature is an amorphous film, and the Ir oxide film 24 formed at 50 ° C. or 100 ° C. is made of fine crystals, so that oxidation and reduction in the chamber are almost uniform. It is thought that it is because it is done.

  Further, when the Ir oxide film 24 was formed at 200 ° C. or 300 ° C., a slightly inferior result was obtained as compared with the case where it was formed at room temperature to 100 ° C. This is presumably because the degree of oxidation of the Ir oxide film 24 is high and the reduction to the Ir film 24a is insufficient due to the cooperative action with the high-speed formation of the initial PZT film 25a.

  On the other hand, the reference sample in which the Ir oxide film 24 was not formed was inferior to the sample in which the Ir oxide film 24 was formed. That is, the orientation to the (100) plane and the (101) plane was high, and the orientation to the (111) plane was low. Therefore, the orientation rate of (222) was low. In particular, the orientation toward the (111) plane at the right end was weak and the variation was large.

  From the result of the first experiment, it is considered that the formation temperature of the Ir oxide film 24 is particularly preferably room temperature to 100 ° C.

(Second experiment)
In the second experiment, the thickness of the Ir oxide film 24 was investigated. In the second experiment, an Ir oxide film 24 having various thicknesses was formed on the Ir film 23 under the same conditions as in the first experiment. In consideration of the result of the first experiment, the formation temperature was set to 60 ° C. The thickness of the Ir oxide film 24 was 15 nm, 25 nm, 35 nm, 40 nm, and 50 nm. Thereafter, both the initial PZT film 25a and the core PZT film 25b were formed at a rate of 0.17 nm / second by MOCVD. Then, the crystal structure of the PZT film 25b was analyzed by the X-ray diffraction method. This analysis was performed at four locations of the center portion, the upper end portion, the right end portion, and the lower end portion when the orientation flat of the disc-shaped silicon substrate 1 was positioned at the lower end. The results are shown in FIGS. 6A to 6D. 6A shows the integrated intensity of orientation to the (100) plane, FIG. 6B shows the integrated intensity of orientation to the (101) plane, and FIG. 6C shows the integrated intensity of orientation to the (111) plane. FIG. 6D shows the orientation ratio of the (222) plane.

  As shown in FIGS. 6A to 6D, particularly good results were obtained when the thickness was 25 nm to 40 nm. That is, the orientation to the (100) plane and the orientation to the (101) plane were low, and the orientation to the (111) plane was high. Therefore, the orientation rate of (222) was high. Furthermore, the variation in orientation was low. This is presumably because the oxidation and reduction in the chamber are performed almost uniformly.

  Further, when the thickness was 15 nm, a slightly inferior result was obtained as compared with the case where the thickness was 25 nm to 40 nm. This is presumably because not only the Ir oxide film 24 is oxidized in the chamber, but also a slight abnormal oxidation occurs in the Ir film 23, and this portion is unlikely to become a crystal with good orientation upon reduction. Note that the abnormal oxidation of the Ir film 23 can be suppressed by adjusting the formation conditions (for example, the atmosphere) of the initial PZT film 25a.

  Even when the thickness was 50 nm, a slightly inferior result was obtained as compared with the case where the thickness was 25 nm to 40 nm. This is considered to be because the Ir oxide film 24 is thick and the reduction to the Ir film 24a is insufficient due to the cooperative action with the high-speed formation of the initial PZT film 25a.

  From the result of the second experiment, it is considered that the thickness of the Ir oxide film 24 is particularly preferably 25 nm to 40 nm.

(Third experiment)
In the third experiment, the proportion of O ₂ gas in the atmospheric gas when forming the Ir oxide film 24 was investigated. In the third experiment, an Ir oxide film 24 having a thickness of 30 nm was formed on the Ir film 23 under the same conditions as in the first experiment in various atmospheres. In consideration of the result of the first experiment, the formation temperature was set to 60 ° C. The ratio of O ₂ gas is 5% (Ar gas flow rate: 190 sccm, O ₂ gas flow rate: 10 sccm), 7% (Ar gas flow rate: 186 sccm, O ₂ gas flow rate: 14 sccm), 10% (Ar gas flow) Flow rate: 180 sccm, O ₂ gas flow rate: 20 sccm), 20% (Ar gas flow rate: 160 sccm, O ₂ gas flow rate: 40 sccm), 25% (Ar gas flow rate: 150 sccm, O ₂ gas flow rate: 50 sccm) ), 30% (Ar gas flow rate: 140 sccm, O ₂ gas flow rate: 60 sccm), 35% (Ar gas flow rate: 130 sccm, O ₂ gas flow rate: 70 sccm). Thereafter, both the initial PZT film 25a and the core PZT film 25b were formed at a rate of 0.17 nm / second by MOCVD. Then, the crystal structure of the PZT film 25b was analyzed by the X-ray diffraction method. This analysis was performed at five locations of the center portion, the upper end portion, the right end portion, the lower end portion, and the left end portion when the orientation flat of the disc-shaped silicon substrate 1 was positioned at the lower end. The results are shown in FIGS. 7A to 7D. 7A shows the integrated intensity of orientation to the (100) plane, FIG. 7B shows the integrated intensity of orientation to the (101) plane, and FIG. 7C shows the integrated intensity of orientation to the (111) plane. FIG. 7D shows the orientation ratio of the (222) plane.

As shown in FIGS. 7A to 7D, particularly good results were obtained when the proportion of O ₂ was 5% to 10%. That is, the orientation to the (100) plane and the orientation to the (101) plane were low, and the orientation to the (111) plane was high. Therefore, the orientation rate of (222) was high. Furthermore, the variation in orientation was low. This is presumably because the oxidation and reduction in the chamber are performed almost uniformly.

Further, when the ratio of O ₂ was 20% to 35%, a slightly inferior result was obtained as compared with the case where the ratio of O ₂ was 5% to 10%. This is presumably because the degree of oxidation of the Ir oxide film 24 is high and the reduction to the Ir film 24a is insufficient due to the cooperative action with the high-speed formation of the initial PZT film 25a.

From the result of the third experiment, when the sputtering power is 0.5 kW and the formation rate of the initial PZT film 25a is 0.17 nm / second, the ratio of O ₂ is particularly preferably 5% to 10%. Conceivable.

Note that the sputter power, the formation speed, and the ratio of O ₂ affect the specific resistance of the Ir oxide film 24. Then, for example, Ir formed under the conditions of sputtering power: 0.5 kW, formation rate: 1.5 nm / second, O ₂ ratio: 5% (Ar gas flow rate: 190 sccm, O ₂ gas flow rate: 10 sccm) The specific resistance of the oxide film 24 is as follows: sputter power: 1.0 kW, formation rate: 3.0 nm / second, O ₂ ratio: 10% (Ar gas flow rate: 180 sccm, O ₂ gas flow rate: 20 sccm) This is equivalent to the specific resistance of the formed Ir oxide film 24. In any Ir oxide film 24, the specific resistance is about 300 Ω · cm. Sputter power: 2.0 kW, formation rate: 6.0 nm / second, O ₂ ratio: 18% (Ar gas flow rate: 164 sccm, O ₂ gas flow rate: 36 sccm) It is the same.

Accordingly, the preferred ratio of O ₂ gas also changes depending on the sputter power and / or the formation rate. For example, when the formation rate of the Ir oxide film 24 is 1.0 nm / second or more and less than 2.5 nm / second, the ratio of O ₂ gas is preferably 2% to 15%. When the formation rate of the Ir oxide film 24 is 2.5 nm / second or more and less than 4.0 nm / second, the ratio of O ₂ gas is preferably 4% to 20%. When the formation rate of the Ir oxide film 24 is 4.0 nm / second or more and 7.0 nm / second or less, the ratio of O ₂ gas is preferably 5% to 30%. In particular, the sputter power is preferably 0.5 kW, and the O ₂ gas ratio is preferably 5% to 7%.

(Fourth experiment)
In the fourth experiment, the formation rate of the initial PZT film 25a was investigated. In the fourth experiment, an Ir oxide film 24 having a thickness of 30 nm is formed by using an Ar gas flow rate of 186 sccm, an O ₂ gas flow rate of 14 sccm (O ₂ ratio: 7%), a sputter power of 0.5 kW, and a formation rate: The film was formed on the Ir film 23 in the same manner as in the first embodiment under the conditions of 1.6 nm / second and formation temperature: 60 ° C. Thereafter, an initial PZT film 25a was formed by MOCVD, and a core PZT film 25b was further formed under conditions of a formation temperature: 620 ° C. and a formation rate: 0.17 nm / second. In forming the initial PZT film 25a, the formation temperature was set to 600 ° C. or 620 ° C., and the formation rate was set to 0.04 nm / second or 0.17 nm / second. And the surface of the core PZT film | membrane 25b was observed using SEM. The results are shown in FIGS. 8A to 8D. FIG. 8A shows an SEM photograph of a sample in which the initial PZT film 25a is formed at 620 ° C. and 0.17 nm / second. FIG. 8B shows an SEM photograph of a sample in which the initial PZT film 25a is formed at 620 ° C. and 0.04 nm / second. FIG. 8C shows an SEM photograph of a sample in which the initial PZT film 25a is formed at 600 ° C. and 0.17 nm / second. FIG. 8D shows an SEM photograph of a sample in which the initial PZT film 25a is formed at 600 ° C. and 0.04 nm / second.

  As shown in FIGS. 8A to 8D, surface irregularities were suppressed in the sample in which the initial PZT film 25a was formed at a rate of 0.04 nm / second (FIGS. 8B and 8D). Moreover, if the formation speed was the same, the unevenness | corrugation was suppressed in the sample with high formation temperature. The presence of such irregularities may lead to a decrease in switching charge amount, for example.

Further, the average roughness Ra at three points in the silicon substrate 1 was measured for two samples on which the initial PZT film 25a was formed at 620 ° C. using an atomic force microscope (AFM). As a result, in the sample formed at 0.17 nm / second, the average roughness Ra was 8.5 nm and the number of protrusions was about 20 / μm ² . In contrast, in the sample formed at 0.04 nm / second, the average roughness Ra was 4.5 nm and the number of protrusions was about 5 / μm ² . That is, an excellent result was obtained in the sample formed at 0.04 nm / second.

  From the result of the fourth experiment, it is considered that the formation rate of the initial PZT film 25a is particularly preferably 0.10 nm / second or less.

(Fifth experiment)
In the fifth experiment, the thickness of the initial PZT film 25a was investigated. In the fifth experiment, the initial PZT film 25a and the core PZT film 25b having various thicknesses were formed under the same conditions as in the fourth experiment. In consideration of the result of the fourth experiment, the formation rate was set to 0.04 nm / second. The total thickness of the initial PZT film 25a and the core PZT film 25b was 100 nm, and the thickness of the initial PZT film 25a was 1.0 nm, 2.5 nm, and 5.0 nm. And the surface of the core PZT film | membrane 25b was observed using SEM. The results are shown in FIGS. 9A to 9C. FIG. 9A shows an SEM photograph of a sample in which the initial PZT film 25a has a thickness of 5.0 nm. FIG. 9B shows an SEM photograph of a sample in which the initial PZT film 25a has a thickness of 2.5 nm. FIG. 9C shows an SEM photograph of a sample in which the initial PZT film 25a has a thickness of 1.0 nm.

  As shown in FIGS. 9A to 9C, particularly good results were obtained when the thickness was 2.5 nm or 5.0 nm. On the other hand, when the thickness was 1.0 nm, a slightly inferior result was obtained as compared with the thickness of 2.5 nm or 5.0 nm. This is considered to be because the initial PZT film 25a is thin and the uniformity of itself is lowered.

  From the result of the fifth experiment, it is considered that the thickness of the initial PZT film 25a is particularly preferably 2.5 nm or more. As described above, when the thickness of the initial PZT film 25a exceeds 10 nm, the influence of oxygen deficiency or the like increases, and it may be difficult to secure a sufficient switching charge amount. Therefore, the thickness of the initial PZT film 25a is preferably 2.5 nm to 10 nm.

(Sixth experiment)
In the sixth experiment, the change of the Ir oxide film 24 was investigated. In the fourth experiment, an Ir oxide film 24 having a thickness of 30 nm is formed by using an Ar gas flow rate of 186 sccm, an O ₂ gas flow rate of 14 sccm (O ₂ ratio: 7%), a sputter power of 0.5 kW, and a formation rate: The film was formed on the Ir film 23 in the same manner as in the first embodiment under the conditions of 1.6 nm / second and formation temperature: 60 ° C. And X-ray diffraction analysis of this sample was performed. Thereafter, the sample was heated to 620 ° C. in a chamber supplied with O ₂ in the same manner as in the first embodiment. Note that the subsequent supply of the raw material of the PZT film was not performed. Then, X-ray diffraction analysis of this sample was performed again. These results are shown in FIG. The lower side in FIG. 10 shows the analysis result before heating, and the upper side shows the analysis result after heating.

As shown in FIG. 10, before heating, the Ir oxide film 24 is an amorphous film or a film made of fine crystals. Therefore, only the peak of the material constituting the lower electrode appears, and the peak of Ir oxide appears. There wasn't. In contrast, IrO ₂ peaks (110) and (101) appeared after heating. This means that columnar crystals are generated in the Ir oxide film 24.

Also, X-ray diffraction analysis was performed on a sample in which the initial PZT film 25a and the core PZT film 25b were formed after heating in a chamber to which O ₂ was supplied. The result is shown in FIG.

As shown in FIG. 11, the peaks (110) and (101) of IrO ₂ that appeared on the upper side of FIG. 10 disappeared. The Ir (111) peak became prominent. This means that the Ir oxide film 24 is changed to the Ir film 23 by reduction.

  Furthermore, BF-STEM (Bright-field Scanning Transmission Electron Microscopy) observation and energy dispersive X-ray spectroscopy (EDX) analysis are performed on the sample on which the initial PZT film 25a and the core PZT film 25b are formed. went. These results are shown in FIGS. Note that the three analysis results in FIG. 13 are the analysis results at points 1, 2, and 3 in FIG. 12, respectively.

  As shown in FIG. 12, two Ir films were present on the lower electrode. The crystal grains were large in the lower Ir film. The average grain size of the crystals in the upper Ir film was 11 nm. The lower Ir film corresponds to the Ir film 23, and the upper Ir film corresponds to the Ir film 24a.

  As shown in FIG. 13, Pb, Zr, Ti and O are detected at point 1 (in the core PZT film 25b), and Pb, Zr, Ti, Ir and at point 2 (in the initial PZT film 25a). O was detected, and at point 3 (in the Ir film 24a), Ir was detected. That is, Ir was not detected in the core PZT film 25b, but Ir was detected in the initial PZT film 25a. This means that Ir diffused up to the initial PZT film 25a but did not diffuse up to the core PZT film 25b. In addition, since O is not detected at point 3, it is also clear that the Ir oxide film 24 is changed to the Ir film 24a.

  Furthermore, as a result of measuring Pb and Ir of the sample by EDX mapping, it was confirmed that a different film exists between the Ir film 24a and the core PZT film 25b. In this film, the amount of Pb was less than that of the core PZT film 25b. Therefore, it can be said that this film corresponds to the initial PZT film 25a. Ir was detected from this film, but Ir was not detected from the core PZT film 25b. From this, it is clear that Ir diffused up to the initial PZT film 25a but did not diffuse up to the core PZT film 25b.

  In addition, secondary ion mass spectrometry (SIMS) was performed. The result is shown in FIG. FIG. 14 shows only the results of O and Ir.

  As shown in FIG. 14, the atomic density of O did not increase even on the PZT film side of the Ir film. This means that the Ir oxide film 24 is reduced to the Ir film 24a. In addition, the atomic density of Ir increased on the Ir film side of the PZT film. This means that Ir has diffused here. Therefore, it agrees with the above result.

  From these results, it was confirmed that the Ir oxide film 24 was changed to the Ir film 24a by reduction according to the formation conditions of the initial PZT film 25a.

(Seventh experiment)
In the seventh experiment, the orientation of the core PZT film 25b was investigated. In the seventh experiment, an Ir oxide film 24 having a thickness of 30 nm was formed by using an Ar gas flow rate of 186 sccm, an O ₂ gas flow rate of 14 sccm (O ₂ ratio: 7%), a sputter power of 0.5 kW, and a formation rate: The film was formed on the Ir film 23 in the same manner as in the first embodiment under the conditions of 1.6 nm / second and formation temperature: 60 ° C. Thereafter, the initial PZT film 25a is formed by MOCVD under the conditions of the formation temperature: 620 ° C. and the formation rate: 0.04 nm / second, and the core PZT film 25b is formed at the formation temperature: 620 ° C., the formation rate: 0. The film was formed under the condition of 17 nm / second. Twenty-five such samples were produced. Then, the crystal structure of the core PZT film 25b was analyzed by the X-ray diffraction method. This analysis was performed at two locations, the upper end portion and the right end portion when the orientation flat of the disc-shaped silicon substrate 1 was positioned at the lower end. The results are shown in FIGS. 15A and 15B. FIG. 15A shows the integrated intensity of orientation to the (111) plane, and FIG. 15B shows the orientation ratio of the (222) plane.

  As shown in FIG. 15A and FIG. 15B, the orientation to the (111) plane was high and the orientation ratio of the (222) plane was high in both the central portion and the right end portion. Furthermore, the variation in orientation was extremely small.

  From the result of the seventh experiment, it can be said that the orientation of the core PZT film 25b is very good.

(Eighth experiment)
In the eighth experiment, regarding the second embodiment, the ratio of O ₂ gas in the atmospheric gas when forming the Ir oxide film 24 was investigated. In the eighth experiment, an Ir oxide film 24 having a thickness of 30 nm was formed in various atmospheres under the conditions of sputtering power: 0.5 kW, formation rate: 1.6 nm / second, and formation temperature: 60 ° C. The film was formed on the Ir film 23 in the same manner as in the first embodiment (time: 19 seconds). The proportion of O ₂ gas was 5%, 6%, and 7%. Thereafter, an initial PZT film 25a having a thickness of 5 nm was formed at a rate of 0.04 nm / second and a core PZT film 25b having a thickness of 95 nm was formed at a rate of 0.17 nm / second by MOCVD. Further, a reference sample in which the initial PZT film 25a and the core PZT film 25b were directly formed on the Ir film 23 without forming the Ir oxide film 24 was also produced. In addition, two types of samples having different sizes and arrangements of the ferroelectric capacitors were prepared for each of the above four types of conditions. In one sample (discrete), the planar shape was a square having a side length of 50 μm, and 50 ferroelectric capacitors were isolated from each other. In the other sample (cell array), the planar shape was a square having a side length of 0.7 μm, and 50 regions where 5152 ferroelectric capacitors were densely formed were prepared. Then, these switching charge amounts (applied voltage: 1.8 V) were measured. The result is shown in FIG.

  As shown in FIG. 16, in the sample in which the Ir oxide film 24 was formed, a high switching charge amount was obtained. This is because almost the entire core PZT film 25b is oriented in the (111) plane. Particularly high switching charge was obtained when the O2 ratio was 6% and 7%.

  On the other hand, in the sample in which the Ir oxide film 24 was not formed, the switching charge amount was extremely low. This is because the orientation to the (111) plane is insufficient.

(Ninth experiment)
In the ninth experiment, the relationship between the applied voltage and the switching charge amount was investigated using the sample of the cell array fabricated in the eighth experiment. The results are shown in FIGS. 17A and 17B. FIG. 17A shows the result of discrete, and FIG. 17B shows the result of cell array.

As shown in FIG. 17A and FIG. 17B, in the sample in which the Ir oxide film 24 was formed, a very large switching charge amount was obtained compared to the sample in which the Ir oxide film 24 was not formed. Further, as shown in FIG. 17B, in the cell array, a particularly high switching charge amount was obtained when the O ₂ ratio was 6% and 7%.

Further, the maximum slope of the curve was large in the sample in which the Ir oxide film 24 was formed, particularly in the samples having the O ₂ ratio of 6% and 7%. Therefore, low voltage operation is also possible.

From these results, it is considered that the ratio of O ₂ is preferably 6% to 7% in consideration of application to a ferroelectric memory.

(Tenth experiment)
In the tenth experiment, the leakage current density was investigated using the sample of the cell array fabricated in the eighth experiment. The result is shown in FIG.

  As shown in FIG. 18, the leakage current of the sample in which the Ir oxide film 24 was formed was almost the same as that of the sample in which the Ir oxide film 24 was not formed. That is, there was no problem that the leakage current increased as compared with the conventional one.

It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 1st Embodiment of this invention. FIG. 1B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1A. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1B. FIG. 2C is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1C. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1D. FIG. 2E is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1E. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1F. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1G. 1H is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1H. FIG. 11 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1I; FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1J. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1K. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1L. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1M. 1N is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1N; FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 10. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1P. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1Q. FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1R; It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 2nd Embodiment of this invention. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 2A. FIG. 2B is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2B. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 3rd Embodiment of this invention. FIG. 3B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 3A. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 4th Embodiment of this invention. FIG. 4B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4A. FIG. 4B is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 4B. It is a graph which shows the integrated intensity | strength of the orientation to the (100) plane in 1st experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (101) plane in a 1st experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in a 1st experiment. It is a graph which shows the orientation rate of the (222) plane in a 1st experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (100) plane in 2nd experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (101) plane in 2nd experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in 2nd experiment. It is a graph which shows the orientation rate of the (222) plane in 2nd experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (100) plane in 3rd experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (101) plane in 3rd experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in 3rd experiment. It is a graph which shows the orientation rate of the (222) plane in 3rd experiment. It is a figure which shows the SEM photograph of the sample which formed the initial stage PZT film | membrane 25a in 620 degreeC and 0.17 nm / sec in 4th experiment. It is a figure which shows the SEM photograph of the sample which formed the initial stage PZT film | membrane 25a in 620 degreeC and 0.04 nm / sec in 4th experiment. It is a figure which shows the SEM photograph of the sample which formed the initial stage PZT film | membrane 25a in 600 degreeC and 0.17 nm / sec in 4th experiment. It is a figure which shows the SEM photograph of the sample which formed the initial stage PZT film | membrane 25a in 600 degreeC and 0.04 nm / sec in 4th experiment. It is a figure which shows the SEM photograph of the SEM photograph of the sample which made thickness of the initial stage PZT film | membrane 25a 5.0 nm in 5th experiment. It is a figure which shows the SEM photograph of the SEM photograph of the sample which made thickness of the initial stage PZT film | membrane 25a 2.5 nm in 5th experiment. It is a figure which shows the SEM photograph of the SEM photograph of the sample which made thickness of the initial stage PZT film | membrane 25a 1.0 nm in 5th experiment. It is a graph which shows the result (before formation of a PZT film | membrane) of the X-ray-diffraction analysis in 6th experiment. It is a graph which shows the result (after formation of a PZT film | membrane) of the X-ray diffraction analysis in 6th experiment. It is a figure which shows the result of BF-STEM in 6th experiment. It is a graph which shows the result of the EDX analysis in 6th experiment. It is a graph which shows the result of SIMS analysis in the 6th experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in a 7th experiment. It is a graph which shows the orientation rate of the (222) plane in 7th experiment. It is a graph which shows the relationship between the ratio of the oxygen gas in 8th experiment, and the amount of switching charges. It is a graph which shows the relationship (discrete) between the applied voltage and switching charge amount in 9th experiment. It is a graph which shows the relationship (cell array) of the applied voltage and switching charge amount in 9th experiment. It is a graph which shows the measurement result of the leakage current in a 10th experiment. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in the center part of a wafer regarding the conventional manufacturing method. It is a graph which shows the integrated intensity | strength of the orientation to the (111) plane in the peripheral part of a wafer regarding the conventional manufacturing method. It is a graph which shows the orientation rate of the (222) plane in the center part of a wafer regarding the conventional manufacturing method. It is a graph which shows the orientation rate of the (222) plane in the peripheral part of a wafer regarding the conventional manufacturing method. It is a figure which shows the SEM photograph of the sample manufactured by the conventional method. It is a figure which shows the SEM photograph of the sample manufactured by the conventional method.

Explanation of symbols

23: Ir film 24: Ir oxide film 24a: Ir film 25: PZT film 25a: Initial PZT film 25b: Core PZT film 25c: Cap PZT film

Claims (6)

Forming a lower electrode above the substrate;
Forming an oxide dielectric film on the lower electrode;
Forming an upper electrode on the oxide dielectric film;
Have
The step of forming the lower electrode includes:
Forming a first noble metal film;
Forming a noble metal oxide film on the first noble metal film;
Have
The step of forming the oxide dielectric film includes
Forming a lower layer film on the noble metal oxide film by metal organic chemical vapor deposition and reducing the noble metal oxide film into a second noble metal film;
Forming a core film on the lower layer film at a deposition rate higher than the deposition rate of the lower layer film, thicker than the lower layer film and having a higher degree of oxidation than the lower layer film;
Have
A method of manufacturing a semiconductor device, wherein crystal grains constituting the second noble metal film are smaller than crystal grains constituting the first noble metal film .   The method for manufacturing a semiconductor device according to claim 1, wherein a formation speed of the lower layer film is set to 0.10 nm / second or less.   The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the lower layer film is set to 2.5 nm to 10 nm.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the noble metal oxide film has a thickness of 25 nm to 50 nm.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the noble metal oxide film is formed with a film in which oxygen is less than a stoichiometric composition. 6. A lower electrode formed above the substrate;
An oxide dielectric film formed on the lower electrode;
An upper electrode formed on the oxide dielectric film;
Have
The lower electrode is
A first noble metal film;
A second noble metal film in contact with the upper surface of the first noble metal film and the lower surface of the oxide dielectric film and having a crystal grain size smaller than that of the first noble metal film;
Have
The oxide dielectric film is
A lower layer film in contact with the upper surface of the second noble metal film;
A core film in contact with the upper surface of the lower layer film, thicker than the lower layer film and having a higher degree of oxidation than the lower layer film;
A semiconductor device comprising:

Images