JP4971740B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device suitable for a ferroelectric memory.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, with respect to semiconductor memory devices, for example, in order to realize high integration of DRAM, as a capacitor insulating film of a capacitor element constituting the DRAM, a ferroelectric material or a high material is used instead of conventional silicon oxide or silicon nitride. Technologies using dielectric materials have been widely researched and developed.

  In addition, in order to realize a nonvolatile RAM that can perform a write operation and a read operation at a lower voltage and at a higher speed, a technique using a ferroelectric film having spontaneous polarization characteristics as a capacitor insulating film has been actively researched and developed. Yes. Such a semiconductor memory device is called a ferroelectric memory (FeRAM).

  A ferroelectric memory stores information using the hysteresis characteristics of a ferroelectric. A ferroelectric memory is provided with a ferroelectric capacitor, and the ferroelectric capacitor is configured such that a ferroelectric film is sandwiched between a pair of electrodes as a capacitive dielectric film. The ferroelectric film generates polarization according to the applied voltage between the electrodes, and has spontaneous polarization even when the applied voltage is removed. Further, if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read by detecting this spontaneous polarization. A ferroelectric memory operates at a lower voltage than a flash memory, and can be written at high speed with low power consumption. Then, use of a logic embedded chip (SoC: System on Chip) having a ferroelectric memory for an IC card or the like is being studied.

As the ferroelectric film, a PZT-based material film, a Bi layered structure compound film, or the like is used. Examples of the PZT-based material include lead zirconate titanate (PZT) itself and those obtained by doping a PZT film with La, Ca, Sr and / or Si. Examples of the Bi layer structure compound include SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ), and the like. The ferroelectric film is formed on the lower electrode film in an amorphous state or a microcrystalline state by a sol-gel method or a sputtering method, and then crystallized by heat treatment. Further, it may be formed in a crystallized state on the lower electrode by MOCVD (Metal Organic Chemical Vapor Deposition).

  In order to fabricate a ferroelectric memory with good electrical characteristics and high product yield, it is important to improve the orientation of the crystals constituting the ferroelectric film. The orientation of the ferroelectric film is greatly influenced by the orientation of the lower electrode film. In other words, the orientation of the ferroelectric film can be improved by adjusting the orientation of the lower electrode film.

Here, the lower electrode film is mainly configured by combining two or more of a TiN film, a TiAlN film, an Ir film, an IrO ₂ film, a Pt film, and an SRO (SrRuO ₃ ) film. Note that when the ferroelectric film is formed by employing the MOCVD method, the Ir film or the Ti film is positioned on the outermost surface. In a ferroelectric capacitor having a stack structure, the film located below the lower electrode may be called a barrier metal film.

  As described above, there are various methods for forming a ferroelectric film, but the MOCVD method is preferable for improving the degree of integration in recent years. When the ferroelectric film is formed by MOCVD, the semiconductor substrate on which the lower electrode film is formed is inserted into the MOCVD chamber and heated to 600 ° C. or higher in an argon atmosphere.

  However, when a PZT film is formed by such a method, the surface is strongly oriented to the (100) plane or the (101) plane, and the preferred orientation to the (111) plane is weak. For this reason, it cannot be said that the switching charge amount of the ferroelectric capacitor is sufficient.

JP 2005-159165 A JP 2003-197874 A JP 2001-237392 A JP 2002-151656 A

  An object of this invention is to provide the manufacturing method of the semiconductor device which can control the orientation of a ferroelectric film to a preferable direction.

If the orientation of the PZT film is merely controlled, the temperature rise in the argon atmosphere may be changed to the temperature rise in the oxygen atmosphere. However, when the temperature is raised in an oxygen atmosphere, the orientation of the surface of the PZT film to the (111) plane varies greatly and the surface tends to be rough. In particular, very large convex portions are generated around the periphery of the semiconductor substrate, and surface roughness is likely to occur. The reason for this is considered that the outermost surface of the lower electrode film, for example, the surface of the Ir film is abnormally oxidized during the temperature rise. When Ir is abnormally oxidized, IrO _x is produced, and the MOCVD solvent THF (Tetra Hydro Furan: C ₄ H ₈ O) or butyl acetate reduces IrO _x . Then, a heterogeneous phase is generated during the reduction, and the crystallinity of the PZT film formed immediately after that is reduced.

  Therefore, in the present invention, the formation of the ferroelectric film itself is not devised, but the intention is to concentrate on the formation of the lower electrode film positioned immediately below as follows.

In the method of manufacturing a semiconductor device according to the present invention, after a noble metal film is formed above a semiconductor substrate, a crystallized noble metal oxide film is formed on the noble metal film by a sputtering method. Next, the noble metal oxide film is reduced. Then, a ferroelectric film is formed on the noble metal oxide film while being reduced. Thereafter, an electrode is formed on the ferroelectric film. One film selected from the group consisting of an Ir oxide film, a Rh oxide film, a Pd oxide film and a Ru oxide film is formed as the noble metal oxide film, and an Ir film, a Rh film, a Pd film and a Ru film are formed as the noble metal film. One film selected from the group consisting of films is formed.

  According to the present invention, since the crystallized noble metal oxide film constituting the lower electrode film is reduced and the ferroelectric film is formed as it is, abnormal oxidation of the lower electrode film can be avoided. Therefore, a ferroelectric film having excellent crystallinity can be obtained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. However, here, for convenience, the cross-sectional structure of each memory cell of the ferroelectric memory will be described together with its manufacturing method.

(First embodiment)
First, a first embodiment of the present invention will be described. 1A to 1Q are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps.

  In the first embodiment, first, as shown in FIG. 1A, a trench for STI (Shallow Trench Isolation) that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon substrate 1. An element isolation insulating film 2 is formed by embedding an insulating film such as silicon oxide therein. Note that an element isolation insulating film may be formed by a LOCOS (Local Oxidation of Silicon) method.

  Next, a p-type impurity is introduced into the active region to form a p-well 3. Next, the gate insulating film 4 is formed by thermally oxidizing the surface of the active region. Subsequently, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1 and patterned by a photolithography technique to form the gate electrode 5. At this time, two gate electrodes 5 are arranged in parallel with each other on the p-well 3. These gate electrodes 5 function as part of the word lines of the memory.

  Next, the extension layer 6 is formed on both sides of the gate electrode 5 by introducing n-type impurities (ion implantation) using the gate electrode 5 as a mask. Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 and etched back to form insulating sidewalls 8 beside the gate electrode 5. As the insulating film, for example, a silicon oxide film is formed by a CVD method.

  Subsequently, impurity diffusion layers 7 are formed on both sides of the gate electrode 5 by introducing n-type impurities (ion implantation) using the sidewall 8 and the gate electrode 5 as a mask. The two sets of extension layer 6 and impurity diffusion layer 7 constitute the source and drain of the MOS transistor.

  Next, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate 1 by sputtering, and the refractory metal layer is heated to react with silicon. As a result, a refractory metal silicide layer 9 is formed on the gate electrode 5, and a refractory metal silicide layer 10 is formed on the impurity diffusion layer 7. Then, the unreacted refractory metal layer on the element isolation insulating film 2 and the like is removed by wet etching.

  Next, for example, a silicon oxynitride film 11 having a thickness of about 200 nm is formed on the entire upper surface of the silicon substrate 1 by plasma CVD. Next, a silicon oxide film 12 having a thickness of about 1000 nm is formed on the silicon oxynitride film 11 by, for example, a plasma CVD method using TEOS gas as a source gas. Thereafter, the upper surface of the silicon oxide film 12 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. In this planarization, the thickness of the silicon oxide film 12 is set to about 700 nm from the upper surface of the silicon substrate 1.

  Next, a contact hole exposing the silicide layer 10 is formed by patterning the silicon oxide film 12 and the silicon oxynitride film 11 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film (adhesion film) 13 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 14 is formed in the contact hole and on the silicon oxide film 12. The thickness of the W film 14 is about 300 nm from the upper surface of the silicon oxide film 12. Subsequently, by performing CMP, the glue film 13 and the W film 14 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 13 and the W film 14 on the silicon oxide film 12 are completely removed.

  Next, for example, a silicon oxynitride film 15 having a thickness of about 130 nm is formed as an antioxidant film on the silicon oxide film 12 and the contact plug by plasma CVD. Further, a silicon oxide film 16 having a thickness of about 300 nm is formed on the silicon oxynitride film 15 by, for example, a plasma CVD method using TEOS gas as a source gas. A silicon nitride film or an aluminum oxide film may be formed as an antioxidant film instead of the silicon oxynitride film 15.

  Next, as shown in FIG. 1B, a contact hole exposing the silicide layer 10 is formed by patterning the silicon oxide film 16 and the silicon oxynitride film 15 by photolithography. The diameter of the contact hole is, for example, 0.25 μm. Next, a glue film 17 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. Thereafter, a tungsten film (W film) 18 is formed in the contact hole and on the silicon oxide film 16. The thickness of the W film 18 is about 300 nm from the upper surface of the silicon oxide film 16. Subsequently, by performing CMP, the glue film 17 and the W film 18 are left only in the contact holes. From these, a contact plug is formed. In this CMP, the glue film 17 and the W film 18 on the silicon oxide film 16 are completely removed by overpolishing.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 16 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 16. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the silicon substrate 1 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the silicon substrate 1 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the silicon substrate 1 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

Next, a Ti film having a thickness of about 20 nm is formed on the silicon oxide film 16 and the contact plug. In the formation of the Ti film, for example, a sputtering apparatus in which a target is provided at a position separated from the silicon substrate 1 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 5 seconds in a state where the set temperature of the silicon substrate 1 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. In the present embodiment, since the surface of the silicon oxide film 16 is subjected to NH ₃ plasma treatment before the Ti film is formed, Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film 16 The surface of the can be moved freely. As a result, the Ti film is self-organized and its surface is strongly oriented in the (002) plane. Thereafter, by performing RTA (Rapid Thermal Annealing) at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film is changed to a TiN film 21 whose surface is strongly oriented to the (111) plane as shown in FIG. 1C. .

Subsequently, a TiAlN film 22 having a thickness of about 100 nm is formed as an oxygen diffusion barrier film on the TiN film 21 by, for example, reactive sputtering. At this time, for example, a target obtained by alloying Ti and Al is used. The set temperature of the silicon substrate 1 is 400 ° C., the pressure in the chamber is 253.3 Pa, Ar is supplied at a flow rate of 40 sccm, and N ₂ is supplied at a flow rate of 10 sccm. The sputter power is, for example, 1.0 kW.

  Next, an Ir film 23 having a thickness of 60 nm to 100 nm is formed as a noble metal conductive film on the TiAlN 22 by sputtering, for example. At this time, the set temperature of the silicon substrate 1 is 500 ° C., the pressure in the chamber is 0.2 Pa, and the atmosphere in the chamber is an Ar atmosphere. The sputter power is, for example, 0.3 kW. As the noble metal conductive film, a ruthenium film, a rhodium film, or a palladium film may be formed instead of the Ir film 23.

Next, as shown in FIG. 1D, an IrO _x film 24 having a thickness of 5 nm to 50 nm is formed as a noble metal oxide film on the Ir film 23 by, eg, sputtering. At this time, the set temperature of the silicon substrate 1 is set to 100 ° C. to 400 ° C., the pressure in the chamber is set to 0.11 Pa, and the atmosphere in the chamber is a mixed atmosphere of Ar and O ₂ . The sputter power is, for example, 1 kW.

In the present embodiment, a crystallized film is formed as the IrO _x film 24. Further, it is preferable that the crystals constituting the IrO _x film 24 are equiaxed crystals (chill crystals).

Next, as shown in FIG. 1E, a two-layer PZT film 25 is formed on the IrO _x film 24, for example.

In the formation of the first layer, for example, the MOCVD method is employed, and the thickness is set to about 100 nm. At this time, Pb (C ₁₁ H ₁₉ O ₂ ) ₂ is used as a raw material for Pb. Pb (C ₁₁ H ₁₉ O ₂ ) ₂ may be expressed as Pb (DPM) ₂ . Further, Zr (C ₉ H ₁₅ O ₂ ) ₄ is used as a Zr raw material. Zr (C ₉ H ₁₅ O ₂ ) ₄ may be expressed as Zr (DMHD) ₄ . Further, Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ is used as a Ti raw material. Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ may be expressed as Ti (O—iOr) ₂ (DPM) ₂ . These are all dissolved in a THF solvent at a concentration of 0.3 mol / liter to obtain three types of liquid raw materials. Then, these liquid raw materials are supplied to the vaporizer of the MOCVD apparatus together with THF solvent at a flow rate of 0.474 ml / min at flow rates of 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min, respectively. Vaporize. In this way, source gases of Pb, Zr and Ti are obtained.

  Further, the pressure in the MOCVD chamber is set to 665 Pa (5 Torr), the set temperature of the silicon substrate 1 is set to 620 ° C., and source gases of Pb, Zr and Ti are supplied into the MOCVD chamber for 620 seconds, for example.

During the formation of the first layer, the IrO _x film 24 is reduced in the MOCVD chamber by the THF solvent and changed to an Ir film 24a as shown in FIG. 1E.

In the formation of the second layer, for example, a sputtering method is employed, and the thickness is set to 1 nm to 30 nm (for example, 20 nm). In this case, the second-layer PZT film is in an amorphous state. The MOCVD method may be adopted. In this case, as in the first layer, Pb (DPM) ₂ is used as the Pb raw material, Zr (DMHD) ₄ is used as the Zr raw material, and Ti raw material is used. Ti (O—iPr) ₂ (DPM) ₂ is used.

Next, as shown in FIG. 1F, an IrO _Y film 26 having a thickness of 50 nm is formed on the PZT film 25 by, eg, sputtering. A crystallized film is formed as the IrO _Y film 26. At this time, the set temperature of the silicon substrate 1 is set to 300 ° C., and both Ar and O ₂ are supplied into the chamber at a flow rate of 100 sccm. Further, the sputter power is, for example, about 1 kW to 2 kW. Next, while supplying O ₂ at a flow rate of 20 sccm into the chamber and performing RTA at 725 ° C. for 60 seconds while supplying Ar at a flow rate of 2000 sccm, the PZT film 25 is completely crystallized. In addition, the plasma damage of the IrO _Y film 26 is recovered by this RTA, and oxygen vacancies in the PZT film 25 are compensated.

Thereafter, an IrO _Z film 27 having a thickness of 100 nm to 200 nm is formed on the IrO _Y film 26 by, eg, sputtering. When the chamber atmosphere is an Ar atmosphere, the chamber pressure is 0.8 Pa, and the sputtering power is 1.0 kW, the IrO _Z film 27 has a thickness of about 200 nm in about 79 seconds. The composition of IrO _Z is preferably a composition close to the stoichiometric composition of IrO ₂ than the composition of _{IrO Y (Y <Z <2} ). This is because such a composition suppresses the catalytic action against hydrogen, suppresses the problem that the PZT film 25 is reduced by hydrogen radicals, and improves the hydrogen resistance of the ferroelectric capacitor. Instead of the IrO _Y film 26 and / or the IrO _Z film 27, a film made of Ir, Ru, Rh, Re, Os, or Pd, or an oxide film thereof may be formed. Further, a conductive oxide such as SrRuO ₃ may be formed. Further, a laminate of these films may be used.

Next, an Ir film 28 having a thickness of 50 nm to 100 nm is formed as a hydrogen barrier film and a conductivity improving film on the IrO _Z film 27 by sputtering, for example. At this time, the atmosphere in the chamber is an Ar atmosphere, the pressure in the chamber is 1 Pa, and the sputtering power is 1.0 kW. Instead of the Ir film 27, a ruthenium film, a rhodium film, or a palladium film may be formed.

  Then, back surface cleaning is performed. Subsequently, as shown in FIG. 1G, a titanium nitride film (TiN film) 31 and a silicon oxide film 32 are sequentially formed on the Ir film 28. The TiN film 31 is formed by sputtering, for example. The silicon oxide film 32 is formed by, for example, a CVD method using TEOS gas.

  Next, as shown in FIG. 1H, the silicon oxide film 32 is patterned into an island shape.

  Next, as shown in FIG. 1I, the TiN film 31 is etched using the silicon oxide film 32 as a mask. As a result, a hard mask composed of the island-like TiN film 31 and the silicon oxide film 32 is formed.

Next, using the TiN film 31 and the silicon oxide film 32 as a mask, plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas is performed using an Ir film 28, an IrO _Z film 27, The process is performed on the IrO _Y film 26, the PZT film 25, the Ir film 24a, and the Ir film 23. As a result, the upper electrode 33 and the lower electrode 34 are formed. That is, a ferroelectric capacitor is formed.

  Subsequently, as shown in FIG. 1J, the silicon oxide film 32 is removed by dry etching or wet etching.

  Next, as shown in FIG. 1K, the TiAlN film 22 and the TiN film 21 are patterned by performing dry etching using the Ir film 28 or the like as a mask.

  Next, as shown in FIG. 1L, a protective film 35 covering the ferroelectric capacitor is formed on the silicon oxide film 16. As the protective film 35, an aluminum oxide film having a thickness of about 20 nm is formed by sputtering, for example.

  Thereafter, as shown in FIG. 1M, recovery annealing is performed in an oxygen-containing atmosphere in order to recover the damage of the dielectric film capacitor. The conditions for this recovery annealing are not particularly limited. For example, the set temperature of the silicon substrate 1 is set to 550 ° C. to 700 ° C. In particular, when the PZT film 25 is formed as a ferroelectric film as in this embodiment, recovery annealing is performed in an oxygen atmosphere at 650 ° C. for 60 minutes.

  Thereafter, as shown in FIG. 1N, a new protective film 36 is formed on the protective film 35. As the protective film 36, an aluminum oxide film having a thickness of about 20 nm is formed by, for example, a CVD method.

  Next, as shown in FIG. 1O, a silicon oxide 37 having a thickness of about 1500 nm is formed as an interlayer insulating film on the protective film 36 by, for example, plasma TEOSCVD. At this time, for example, a mixed gas composed of TEOS gas, oxygen gas, and helium gas is used as the source gas. Thereafter, the surface of the silicon oxide 37 is planarized by, for example, a CMP method. Note that as the interlayer insulating film, for example, an insulating inorganic film or the like may be formed.

Subsequently, heat treatment is performed in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result, the moisture in the silicon oxide 37 is removed, the film quality of the silicon oxide 37 is changed, and the moisture is less likely to enter the silicon oxide 37.

  Thereafter, a protective film (barrier film) 38 is formed on the silicon oxide 37 by, for example, sputtering or CVD. As the protective film 38, for example, an aluminum oxide film having a thickness of 20 nm to 100 nm is formed. Since the protective film 38 is formed on the planarized silicon oxide 37, the protective film 38 also becomes flat.

  Next, a silicon oxide 39 having a thickness of 300 nm to 500 nm is formed as an interlayer insulating film on the protective film 38 by, for example, plasma TEOSCVD. Thereafter, the surface of the silicon oxide 39 is planarized by, for example, a CMP method. Note that a silicon oxynitride film, a silicon nitride film, or the like may be formed as the interlayer insulating film.

  Next, as shown in FIG. 1P, the silicon oxide film 39, the protective film 38, and the silicon oxide film 37 are patterned by photolithography to form a contact hole that exposes the upper electrode 33. Further, by patterning the silicon oxide film 39, the protective film 38, the silicon oxide film 37, the protective film 36, the protective film 35, the silicon oxide film 16 and the silicon oxynitride film 15 by photolithography, the glue film 13 and the W film are formed. A contact hole for exposing the contact plug made of the film 14 is formed. The diameter of the contact hole is, for example, 0.25 μm. Thereafter, heat treatment is performed in an oxygen atmosphere at 550 ° C. to recover oxygen vacancies generated in the PZT film 25 during contact hole formation.

  Next, a glue film (adhesion film) 40 is formed by sequentially forming a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 20 nm on the bottom and sides of the contact hole. At this time, for example, a Ti film is formed by sputtering, and a TiN film is formed thereon by MOCVD. However, when the TiN film is formed by the MOCVD method, a treatment in a plasma of a mixed gas of nitrogen and hydrogen is required to remove carbon from the TiN film. In the present embodiment, since the outermost surface of the upper electrode 33 is the Ir film 28, the upper electrode 33 is not reduced even if this plasma treatment is performed. Further, only the TiN film may be formed as the glue film 40.

  Thereafter, a tungsten film (W film) 41 is formed in the contact hole and on the silicon oxide film 39. The thickness of the W film 41 is about 300 nm from the upper surface of the silicon oxide film 39. Subsequently, by performing CMP, the glue film 40 and the W film 41 are left only in the contact holes. From these, a contact plug is formed. In this CMP, by performing over polishing, the glue film 40 and the W film 41 on the silicon oxide film 39 are completely removed.

  Subsequently, a wiring composed of a Ti film 42, a TiN film 43, an AlCu film 44, a TiN film 45, and a Ti film 46 is formed on the silicon oxide film 39 and the contact plug. In forming the wiring, for example, by sputtering, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are used. Films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

In such a first embodiment, when the silicon substrate 1 is inserted into the MOCVD chamber in order to form the PZT film 25, the crystallized IrO _x film 24 is formed on the outermost surface. Therefore, not to cause abnormal oxidation IrO _X film 24, then, the crystallinity of the PZT film 25 formed on the Ir film 24a having changed from IrO _X film 24 is extremely good. That is, as a result of reduction with the THF solvent used for forming the PZT film 25, the crystallinity of the resulting Ir film 24a remains good, and the crystallinity of the PZT film 25 formed thereon is also good. . Accordingly, stable characteristics can be obtained even within the same wafer or between different wafers. In particular, the characteristics during low-voltage operation are good.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. 2A to 2C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention in the order of steps.

In the second embodiment, first, similarly to the first embodiment, the process up to the NH ₃ plasma process is performed on the surface of the silicon oxide film 16. However, in forming a contact plug composed of the glue film 17 and the W film 18, a recess 50 may be formed on the surface of the contact plug as shown in FIG. 2A. The depth of the recess 50 is, for example, about 20 nm to 50 nm.

When the same processing as in the first embodiment is performed with such a recess 50 present, a recess reflecting the recess 50 is formed on the surface of the TiN film 21 and the like, and the orientation of the PZT film 25 is lowered. End up. Therefore, in the second embodiment, as shown in FIG. 2B, a Ti film 51 having a thickness of about 100 nm is formed on the silicon oxide film 16 and the contact plug. In forming the Ti film 51, for example, a sputtering apparatus in which a target is provided at a position separated from the silicon substrate 1 by about 60 mm is used. Then, 2.6 kW of sputtered DC power is supplied for 35 seconds in a state where the set temperature of the silicon substrate 1 is 20 ° C., the pressure in the chamber is 0.15 Pa, and the atmosphere in the chamber is an Ar atmosphere. Also in this embodiment, since the surface of the silicon oxide film 16 is subjected to NH ₃ plasma treatment before the Ti film 51 is formed, Ti atoms deposited thereon are not captured by oxygen atoms, and the silicon oxide film The surface of 16 can be moved freely. As a result, the Ti film 51 is self-organized and its surface is strongly oriented in the (002) plane.

  Thereafter, the surface of the Ti film 51 is planarized by, eg, CMP. The thickness of the planarized Ti film 51 is, for example, 50 nm to 100 nm from the surface of the silicon oxide film 16. This thickness control is performed by time control, for example.

Subsequently, the surface of the Ti film 51 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 51 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 51. Next, as in the first embodiment, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, as shown in FIG. 2C, the Ti film is TiN whose surface is strongly oriented to the (111) plane. The film 21 is used.

  Thereafter, similarly to the first embodiment, processing after the formation of the TiAlN film 22 is performed.

  According to such a second embodiment, a ferroelectric capacitor having good characteristics can be obtained even when the recess 50 is formed.

(Third embodiment)
Next, a third embodiment of the present invention will be described. 3A and 3B are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the third embodiment of the present invention in the order of steps.

  In the third embodiment, first, similarly to the second embodiment, processing up to the formation of the Ti film 51 is performed. Thereafter, as shown in FIG. 3A, the surface of the Ti film 51 is flattened by, for example, a CMP method until the surface of the silicon oxide film 16 is exposed. That is, unlike the second embodiment, the Ti film 51 on the silicon oxide film 16 is completely removed.

Subsequently, similarly to the second embodiment, the surface of the Ti film 51 is exposed to NH ₃ plasma. The crystal on the surface of the Ti film 51 is distorted by the planarization process, but the distortion is alleviated by this plasma process. For this reason, it is possible to avoid a decrease in crystallinity of the film formed thereon.

  Next, a Ti film having a thickness of about 20 nm is formed on the Ti film 51. Next, as in the first and second embodiments, by performing RTA at 650 ° C. for 60 seconds in a nitrogen atmosphere, the Ti film has a strong (111) surface as shown in FIG. 3B. The TiN film 21 is oriented.

  Thereafter, similarly to the first and second embodiments, the processing after the formation of the TiAlN film 22 is performed.

  According to the third embodiment, the same effect as that of the second embodiment can be obtained.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. 4A to 4C are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) according to the fourth embodiment of the present invention in the order of steps.

  In the fourth embodiment, first, as shown in FIG. 4A, similarly to the first embodiment, the processes up to the formation of the contact plug composed of the glue film 13 and the W film 14 are performed.

Next, NH ₃ plasma treatment is performed on the surface of the silicon oxide film 12 to bond NH groups to oxygen atoms on the surface of the silicon oxide film 12. In this plasma processing, for example, a parallel plate type plasma processing apparatus in which a counter electrode is provided at a position separated from the silicon substrate 1 by about 9 mm (350 mils) is used. Then, ammonia gas is supplied into the chamber at a flow rate of 350 sccm while the set temperature of the silicon substrate 1 is 400 ° C. and the pressure in the chamber is 266 Pa (2 Torr). Further, a high frequency of 13.56 MHz is supplied to the silicon substrate 1 side with 100 W power, and a high frequency of 350 kHz is supplied to the counter electrode with 55 W power, and these are continued for 60 seconds.

  Next, as shown in FIG. 4B, a TiN film 21 is formed on the silicon oxide film 12 and the contact plug. The method for forming the TiN film 21 is the same as that in the first embodiment. Thereafter, processing from the formation of the TiAlN film 22 to the formation of the protective film 36 is performed.

  Thereafter, as shown in FIG. 4C, the silicon oxide film 37 is formed and planarized in the same manner as in the first embodiment. Next, contact holes reaching the silicide layer 10 shared by the two MOS transistors are formed in the silicon oxide film 37, the protective film 36, the protective film 35, the silicon oxide film 12, and the silicon oxynitride film 11. Then, a contact plug composed of the glue film 40 and the W film 41 is formed in the contact hole. Further, a hole exposing the upper electrode 33 is formed in a state where the contact plug is covered with an antioxidant film (not shown) or the like.

  Subsequently, wirings and pads made of the Ti film 42, the TiN film 43, the AlCu film 44, the TiN film 45, and the Ti film 46 are formed on the silicon oxide film 37, on the contact plug, and in the hole. In forming the wiring and pads, for example, a sputtering method is used to form a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a thickness of 70 nm. TiN films are sequentially formed, and these are patterned using a photolithography technique.

  Thereafter, further formation of an interlayer insulating film, formation of contact plugs, formation of wiring from the second layer onward, and the like are performed. Then, for example, a cover film made of a TEOS oxide film and a SiN film is formed to complete a ferroelectric memory having a ferroelectric capacitor.

  According to the fourth embodiment, the ferroelectric capacitor can be completed with fewer steps than the first embodiment.

  Note that the structure of the ferroelectric capacitor may be a planar structure instead of a stack structure.

In addition to the MOCVD method, the ferroelectric film is formed by sputtering, sol-gel method, organometallic decomposition (MOD) method, CSD (Chemical Solution Deposition) method, chemical vapor deposition (CVD) method. And an epitaxial growth method. As the ferroelectric film, for example, a film having a Bi layer structure or a perovskite structure can be formed. Examples of such a film include a film represented by the general formula ABO ₃ such as PZT, SBT, BLT, and Bi-based layered compound doped with a small amount of La, Ca, Sr, and / or Si, in addition to the PZT film. .

Further, instead of the TiN film 21, a Ti film, an Al oxide film, an Al nitride film, a TiAlN film, a Ta oxide film, a Ti oxide film, a Zr oxide film, or the like may be used as the adhesion film. However, when an insulating film is used, the ferroelectric capacitor has a planar structure. Further, instead of the TiAlN film 22, an Ir film, a Ru film, or the like may be used as the oxygen barrier film. Further, instead of the Ir film 23, a rhodium film, a palladium film, a ruthenium film, or the like may be used. In place of the IrO _x film 24, a rhodium oxide film, a palladium oxide film, a ruthenium oxide film, or the like may be used. As the crystallinity improving film, a Pt film, an Ir film, a Re film, a Ru film, a Pd film, an Os film, or the like may be used instead of the Ti film 51, or these oxide films may be used.

  Next, the results of experiments conducted by the inventor will be described.

(First experiment)
In the first experiment, the surface of the PZT film was observed. 5A and 5B are micrographs of the surface of the PZT film formed in accordance with the first embodiment. Here, FIG. 5A is a photomicrograph at the center of the wafer, and FIG. 5B is a photomicrograph at the periphery of the wafer. 6A and 6B are photomicrographs of the surface of the PZT film formed on the Ir film without forming the IrO _x film. Here, FIG. 6A is a photomicrograph at the center of the wafer, and FIG. 6B is a photomicrograph at the periphery of the wafer.

  6A and 6B, after forming an Ir film, the temperature was raised in an MOCVD chamber in an oxygen atmosphere to form a PZT film. For this reason, abnormal oxidation occurred in the uncontrollable Ir film during the temperature rise, and after that, although it was reduced, the crystallinity was lowered and unevenness was generated as shown in FIGS. 6A and 6B. This was particularly noticeable in the periphery. On the other hand, in the case of following the first embodiment, as shown in FIG. 5A and FIG. 5B, no unevenness occurred in either the central portion or the peripheral portion. From this, it is considered that there is almost no decrease in crystallinity.

(Second experiment)
In the second experiment, the relationship between the oxygen partial pressure when forming the IrO _x film and the orientation of the PZT film was investigated. Here, the temperature of the substrate when forming the IrO _x film was set to 300 ° C., and the thickness of the IrO _x film was set to 20 nm. The result is shown in FIG. In addition, the vertical axis | shaft of FIG. 7 has shown the integrated intensity | strength of the (111) plane in the surface of a PZT film | membrane. The gases used for forming the IrO _x film are only Ar and O ₂ .

As shown in FIG. 7, when the oxygen partial pressure was 60%, the integrated intensity of the (111) plane was low. This is presumably because the amount of oxygen in the IrO _x film was large and the reduction of the IrO _x film in the MOCVD chamber was insufficient.

(Third experiment)
In a third experiment, it was investigated the relationship between the crystallinity of the oxygen partial pressure and the IrO _X film for forming the IrO _X film. Again, the substrate temperature when forming the IrO _x film was set to 300 ° C., and the thickness of the IrO _x film was set to 20 nm. These results are shown in FIGS. 8A to 8C.

As shown in FIGS. 8A to 8C, when the oxygen partial pressure was 50% or less, the surface of the IrO _x film was oriented in both the (200) plane and the (110) plane. Moreover, the lower the oxygen partial pressure, the stronger the orientation to the (110) plane and the weaker the orientation to the (200) plane. However, if the oxygen partial pressure is too low, the IrO _x crystal becomes unstable, and abnormal oxidation may occur in the MOCVD chamber. From the results of the second and third experiments, the oxygen partial pressure when forming the IrO _x film is desirably 20% to 50%. Within this range, as shown in FIGS. 8A to 8C, the orientation strength to the (200) plane is not more than 10 times the orientation strength to the (110) plane, and these differences are reduced.

  Although not shown, when the oxygen partial pressure was 60%, only the orientation to the (200) plane was confirmed, and the orientation to the (110) plane could not be confirmed.

(Fourth experiment)
In the fourth experiment, the relationship between the substrate temperature when forming the IrO _x film and the orientation of the PZT film was investigated. Here, the oxygen partial pressure when forming the IrO _x film was 30%, and the thickness of the IrO _x film was 20 nm. The result is shown in FIG.

As shown in FIG. 9, when the substrate temperature was 300 ° C., the orientation strength toward the (111) plane was the strongest. On the other hand, when the substrate temperature was 400 ° C., the orientation strength slightly decreased. This is presumably because the IrO _x film already has some abnormal growth. When the substrate temperature is 50 ° C. or lower, the crystallized IrO _x film cannot be formed and is crystallized in the MOCVD chamber. For this reason, as shown in FIG. 9, abnormal oxidation occurred and the orientation of the PZT film toward the (111) plane was weakened. From this result, it is most desirable that the substrate temperature when forming the IrO _x film is 300 ° C.

(Fifth experiment)
In the fifth experiment, the relationship between the thickness of the IrO _x film and the orientation of the PZT film was investigated. Here, the oxygen partial pressure when forming the IrO _x film was 30%, and the substrate temperature was 300 ° C. The result is shown in FIG. In addition, the center part in FIG. 10 shows the result measured at the center part of the wafer, the upper end part shows the result measured at the upper end part based on the orientation flat, and the right end part is based on the orientation flat. The measurement result at the right end is shown.

As shown in FIG. 10, the thicker the IrO _x film, the weaker the orientation of the PZT film toward the (111) plane. This is presumably because the entire IrO _x film may not be reduced. For this reason, the thickness of the IrO _x film is desirably 40 nm or less. However, it is difficult to form a very thin IrO _x film of 5 nm or less with good reproducibility.

(Sixth experiment)
In the sixth experiment, the reproducibility of the orientation of the PZT film formed according to the first embodiment was investigated. Here, the oxygen partial pressure when forming the IrO _x film was 30%, the substrate temperature was 300 ° C., and the thickness of the IrO _x film was 20 nm. Then, PZT films were formed on 25 wafers. The result is shown in FIG. 11A. FIG. 11B is a graph showing the reproducibility of the orientation of the PZT film formed on the Ir film without forming the IrO _x film.

As shown in FIG. 11A, when the first embodiment was followed, reproducibility was extremely high. On the other hand, when the IrO _x film was not formed, as shown in FIG. 11B, the variation in orientation to the (111) plane became large.

Regarding the lower electrode film, Patent Document 1 discloses a structure in which a Ti film and a Pt film are sequentially formed on a TiN film, a structure in which a Ti film, a Pt film, and an SRO film are sequentially formed on a TiN film, and a TiN film. A structure in which a Ti film, an Ir film, and an IrO ₂ film are sequentially formed thereon is described, and a structure in which a TiAlN film, an Ir film, and IrO ₂ are sequentially formed on the TiN film is described. Patent Document 2 describes a structure in which an IrO _x film, a PtO _x film, and a Pt film are sequentially formed on Ir. Patent Document 3 describes a lower electrode made of an Ir film and / or an iridium oxide film. Patent Document 4 describes a structure in which an IrO ₂ film is formed on an Ir film. However, none of the documents discloses that the uppermost film is crystallized.

Further, in the method described in Patent Document 1, it is described that the thickness of the IrO _x film and the Ir film is set to 30 nm. In this case, however, the IrO _x film is too thin and there is a possibility that peeling occurs. Further, the orientation of the PZT film to the (111) plane is very weak, and the switching charge amount is also low. In the method described in Patent Document 2, the problem of abnormal oxidation remains because the Pt film is directly under the ferroelectric film. Further, when a PZT film is formed as a ferroelectric film by MOCVD, Pt and Pb react to generate PbPt, and the electrical characteristics of the ferroelectric capacitor are greatly deteriorated. In the method described in Patent Document 3 or 4, the film immediately below the ferroelectric film is not crystallized, and the PZT film is difficult to be oriented in the (111) plane. This is also apparent from FIG.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
Forming a noble metal film above the semiconductor substrate;
Forming a crystallized noble metal oxide film on the noble metal film;
Reducing the noble metal oxide film;
Forming a ferroelectric film thereon while reducing the noble metal oxide film;
Forming an electrode on the ferroelectric film;
A method for manufacturing a semiconductor device, comprising:

(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein the noble metal oxide film has a thickness of 40 nm or less.

(Appendix 3)
3. The method of manufacturing a semiconductor device according to appendix 1 or 2, wherein a film selected from the group consisting of an Ir oxide film, an Rh oxide film, a Pd oxide film, and a Ru oxide film is formed as the noble metal oxide film.

(Appendix 4)
4. The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein a film selected from the group consisting of an Ir film, an Rh film, a Pd film, and a Ru film is formed as the noble metal film.

(Appendix 5)
5. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film of an element constituting the noble metal film is formed as the noble metal oxide film.

(Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein a thickness of the noble metal oxide film is made thinner than a thickness of the noble metal film.

(Appendix 7)
Before the step of forming the noble metal film,
Forming a transistor on the semiconductor substrate;
Forming an interlayer insulating film above the semiconductor substrate;
Forming a conductive plug connected to the transistor in the interlayer insulating film;
Have
7. The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the noble metal film is electrically connected to the conductive plug.

(Appendix 8)
8. The method of manufacturing a semiconductor device according to any one of appendices 1 to 7, wherein the ferroelectric film is formed by MOCVD.

(Appendix 9)
9. The method of manufacturing a semiconductor device according to claim 1, wherein an oxygen partial pressure in the chamber is set to 20% to 50% when the noble metal oxide film is formed.

(Appendix 10)
10. The method of manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein when forming the ferroelectric film, the raw material of the ferroelectric film is used by dissolving in a reducing solvent.
(Appendix 11)
11. The semiconductor device according to appendix 10, wherein the noble metal oxide film is reduced using the reducing solvent, and the ferroelectric film is formed while continuing to supply the reducing solvent as it is. Manufacturing method.

(Appendix 12)
A semiconductor substrate;
A noble metal film formed above the semiconductor substrate;
A conductive film formed on the noble metal film and obtained by reducing the crystallized noble metal oxide film;
A ferroelectric film formed on the conductive film;
An electrode formed on the ferroelectric film;
A semiconductor device comprising:

It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 1st Embodiment of this invention. FIG. 1B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1A. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1B. FIG. 2C is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1C. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1D. FIG. 2E is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1E. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1F. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1G. 1H is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1H. FIG. 11 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1I; FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1J. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1K. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1L. FIG. 2C is a cross-sectional view illustrating the manufacturing method of the ferroelectric memory, following FIG. 1M. 1N is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 1N; FIG. 10 is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 10. FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 1P. It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on the 2nd Embodiment of this invention. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 2A. FIG. 2B is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2B. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 3rd Embodiment of this invention. FIG. 3B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. It is sectional drawing which shows the manufacturing method of the ferroelectric memory based on the 4th Embodiment of this invention. FIG. 4B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 4A. FIG. 4B is a cross-sectional view showing the method for manufacturing the ferroelectric memory, following FIG. 4B. Is a micrograph showing the surface of the PZT film at the center portion of the wafer (with IrO _X film). Is a micrograph showing the surface of the PZT film in the peripheral portion of the wafer (with IrO _X film). Is a micrograph showing the surface of the PZT film at the center portion of the wafer (without IrO _X film). Is a micrograph showing the surface of the PZT film in the peripheral portion of the wafer (without IrO _X film). Is a graph showing the relationship between the orientation of the oxygen partial pressure and the PZT film when forming the IrO _X film. The oxygen partial pressure is a graph showing the crystallinity of IrO _X film when 50%. The oxygen partial pressure is a graph showing the crystallinity of IrO _X film when 30%. The oxygen partial pressure is a graph showing the crystallinity of IrO _X film at 20%. Is a graph showing the relationship between the orientation of the substrate temperature and the PZT film when forming the IrO _X film. It is a graph showing the relationship between the orientation of the thickness and the PZT film of IrO _X film. It is a graph showing the repeatability of the orientation of the PZT film (with IrO _X film). It is a graph showing the repeatability of the orientation of the PZT film (without IrO _X film).

Explanation of symbols

23: Ir film 24: IrO _x film 24a: Ir film 25: PZT film 33: Upper electrode 34: Lower electrode

Claims (10)

Forming a noble metal film above the semiconductor substrate;
Forming a crystallized noble metal oxide film on the noble metal film by sputtering;
Reducing the noble metal oxide film;
Forming a ferroelectric film thereon while reducing the noble metal oxide film;
Forming an electrode on the ferroelectric film;
I have a,
Forming one film selected from the group consisting of an Ir oxide film, an Rh oxide film, a Pd oxide film, and a Ru oxide film as the noble metal oxide film;
A method of manufacturing a semiconductor device, wherein one film selected from the group consisting of an Ir film, an Rh film, a Pd film, and a Ru film is formed as the noble metal film .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the noble metal oxide film has a thickness of 40 nm or less. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film of an element constituting the noble metal film is formed as the noble metal oxide film. Manufacturing method of the thickness of the noble metal oxide film, a semiconductor device according to any one of claims 1 to 3, characterized in that thinner than the thickness of the noble metal film. Before the step of forming the noble metal film,
Forming a transistor on the semiconductor substrate;
Forming an interlayer insulating film above the semiconductor substrate;
Forming a conductive plug connected to the transistor in the interlayer insulating film;
Have
The method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that connecting the noble metal film electrically to the conductive plug. The method of manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that formed by the MOCVD method the ferroelectric film. Wherein in forming the noble metal oxide layer, a method of manufacturing a semiconductor device according to any one of claims 1 to 6, characterized in that the oxygen partial pressure in the chamber and 20% to 50%. When forming the ferroelectric film, a method of manufacturing a semiconductor device according to any one of claims 1 to 7, characterized by using melt the material of the ferroelectric film in a reducing solvent . 9. The semiconductor according to claim 8 , wherein the noble metal oxide film is reduced by using the reducing solvent, and the ferroelectric film is formed while continuing to supply the reducing solvent as it is. Device manufacturing method. The method of manufacturing a semiconductor device according to any one of claims 1 to 9, characterized in that the 5nm~50nm the thickness of the noble metal oxide layer.

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