JP2005116619A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the deficiency of a Pb atom is prevented, the falloff of the amount of remanent polarization due to the iteration of polarization inversion is restrained, and the reliability over a long period of time is superior; and to provide its manufacturing method. <P>SOLUTION: In the semiconductor device, a substrate 11 is installed, and a silicon oxide film 12, a lower electrode layer 13, a ferroelectric oxide layer 14, a diffusion prevention layer 15, and an upper electrode layer 16, are laminated in order on the substrate 11. The diffusion prevention layer 15 is formed between the ferroelectric oxide layer 14 and the upper electrode layer 16, so that diffusion of Pb atoms of the ferroelectric oxide layer 14 to the upper electrode layer 16 is prevented, and the formation of Pb atom deficiency in the ferroelectric oxide layer 14 is inhibited. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same, and more particularly to a nonvolatile memory with high long-term reliability that suppresses a decrease in the amount of residual polarization of a ferroelectric capacitor.

  In recent years, as an auxiliary storage device such as a PC (personal computer), a non-volatile memory that is electrically rewritable and does not require power to hold information is often used. Nonvolatile memory includes flash memory, MRAM (magnetic random access memory), FeRAM (ferroelectric random access memory), and the like. Among non-volatile memories, FeRAM has attracted attention because of its high integration, high-speed drive, and low power consumption characteristics, with the ferroelectric dielectric film in the ferroelectric capacitor holding information in the form of remanent polarization. .

As a ferroelectric dielectric film, there are a PZT (Pb (Zr, Ti) O ₃ ) film, a PLZT ((Pb, La) (Zr, Ti) O ₃ ) film, an SBT (SrBi ₂ Ta ₂ O ₉ ) film, and the like. Since it has a large amount of remanent polarization, it has been actively studied. The FeRAM updates information by rewriting the dielectric polarization direction according to the direction of the voltage applied to these dielectric films, and stores the two polarization directions as information units. Therefore, it is required to be able to be rewritten repeatedly with the amount of remanent polarization. Since FeRAM is used in portable auxiliary storage devices such as IC cards and smart cards, it is important to have long-term reliability. Proposed characteristics such as 10 years of memory retention and 10 ¹⁵ times of rewriting have been proposed.
JP-A-5-251351

  By the way, the ferroelectric capacitor is configured by sequentially laminating, for example, a lower electrode layer, a PZT film, and an upper electrode layer. When heat treatment is performed to promote crystallization of the PZT film after forming the upper electrode layer, Pb atoms are diffused from the PZT film to the lower electrode layer and the upper electrode layer, and Pb atoms are lost in the PZT film (so-called Pb holes) occur, and the characteristics of the ferroelectric capacitor are significantly deteriorated. In particular, when a ferroelectric capacitor is used for a nonvolatile memory, there is a problem of so-called fatigue characteristics in which the amount of remanent polarization is remarkably reduced by repeated polarization inversion.

  Further, when Pb vacancies are formed in the PZT film, defect levels are formed, which causes an increase in leakage current in the PZT film due to the Pool-Frenkel type mechanism. In addition, Pb vacancies form a barrier at the interface between the PZT film and the lower electrode or the upper electrode by a Schottky barrier type mechanism and participate in phenomena such as leakage current and Pb diffusion, resulting in deterioration of fatigue characteristics and This will increase the leakage current. An increase in leakage current leads to an increase in power consumption during operation of the FeRAM.

  In order to solve these problems, the deterioration of the residual polarization quantity is reduced by introducing a dopant material into the PZT film. However, the introduction of the dopant material reduces the initial residual polarization quantity of the PZT film. There is a problem of end.

  Further, after forming the PZT film by heating the substrate by CVD method or the like, when cooling to room temperature, Pb atoms are dissociated from the surface of the PZT film, and Pb vacancies are formed in the PZT film. This causes a problem of increased leakage current.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to prevent the loss of Pb atoms, reduce the leakage current, and suppress the decrease in the amount of residual polarization due to repeated polarization inversion. Another object is to provide a semiconductor device having excellent long-term reliability and a method for manufacturing the same.

  According to one aspect of the present invention, there is provided a semiconductor device having a ferroelectric oxide layer, and a ferroelectric capacitor including a first electrode layer and a second electrode layer sandwiching the ferroelectric oxide layer. The ferroelectric oxide layer is made of an oxide containing Pb, and is formed between the first electrode layer and the ferroelectric oxide layer, and between the ferroelectric oxide layer and the second electrode layer. A semiconductor device having a diffusion preventing layer for preventing diffusion of Pb in the ferroelectric oxide layer is provided between at least one of the layers.

  According to the present invention, there is a strong force between at least one of the first electrode layer and the ferroelectric oxide layer and between the ferroelectric oxide layer and the second electrode layer. A diffusion preventing layer for preventing diffusion of Pb atoms in the dielectric oxide layer is provided. Pb atoms diffuse from the ferroelectric oxide layer to the first or second electrode layer by the heat treatment after the formation of the diffusion preventing layer, so that Pb atoms are lost in the ferroelectric oxide layer, so-called Pb vacancies. Can be prevented from being formed. As a result, it is possible to reduce the leakage current, suppress the decrease in the residual polarization amount due to repeated polarization inversion, and realize a semiconductor device with excellent long-term reliability.

  According to another aspect of the present invention, a ferroelectric capacitor comprising a ferroelectric oxide layer and a first electrode layer and a second electrode layer sandwiching the ferroelectric oxide layer is provided on a semiconductor substrate. A first step of forming the first electrode layer; a second step of forming the ferroelectric oxide layer; and a third step of forming the second electrode layer. Including at least one of the first step and the second step, and between the second step and the third step, the Pb is transferred to the first or second electrode layer. Forming a diffusion preventing layer for preventing diffusion; in the second step, the semiconductor substrate is heated in a vacuum vessel to deposit a ferroelectric oxide layer; Pb vapor is supplied to the pipe, and cooling is performed while controlling the Pb vapor pressure to a predetermined vapor pressure. The method of manufacturing a semiconductor device is provided.

  According to the present invention, after the ferroelectric oxide layer is deposited, the atmosphere to which the ferroelectric oxide layer is exposed has a predetermined vapor pressure until the semiconductor substrate is cooled from the temperature during deposition to room temperature. Since it is filled with Pb vapor, it is possible to prevent substantial dissociation of Pb atoms from the ferroelectric oxide layer and to prevent formation of Pb vacancies in the PZT film. As a result, it is possible to reduce the leakage current, suppress the decrease in the residual polarization amount due to repeated polarization inversion, and realize a semiconductor device with excellent long-term reliability.

  According to the present invention, by providing a diffusion prevention layer between the ferroelectric oxide layer and the first electrode layer or the second electrode layer, loss of Pb atoms in the ferroelectric oxide layer is prevented. Thus, it is possible to reduce the leakage current, suppress the decrease of the residual polarization amount due to repeated polarization inversion, and realize a semiconductor device with excellent long-term reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a principal part of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, a semiconductor device 10 according to the first embodiment includes a substrate 11, a silicon oxide film 12, a lower electrode layer 13, a ferroelectric oxide layer 14, and a diffusion prevention layer 15 on the substrate 11. The upper electrode layer 16 is sequentially laminated. A voltage is applied between the lower electrode layer 13 and the upper electrode layer 16, and an electric field is applied to the ferroelectric oxide layer 14 to polarize it, and “0” or “1” is set depending on the polarization direction of the residual polarization. Record information. In the ferroelectric capacitor used in the semiconductor device of the present embodiment, the diffusion preventing layer 15 is provided between the ferroelectric oxide layer 14 and the upper electrode layer 16, so that the Pb atoms of the ferroelectric oxide layer 14 are reduced. Diffusion to the upper electrode layer 16 can be prevented, and defect formation of Pb atoms in the ferroelectric oxide layer 14 can be prevented.

  As the substrate 11, for example, a silicon single crystal substrate can be used, and the main surface is set to the (001) plane. The substrate may be a gallium arsenide (GaAs) single crystal substrate.

  The silicon oxide film 12 is formed by a sputtering method, a CVD method, or the like, and has a thickness of, for example, 50 nm to 300 nm. If the substrate 11 is a silicon single crystal substrate, a thermal oxide film whose surface is thermally oxidized may be used.

  The lower electrode layer 13 is formed on the silicon oxide film 12 by a sputtering method, a vacuum deposition method, or the like. For example, a layer made of a platinum group element having a thickness of 50 nm to 200 nm or an alloy containing a platinum group element (hereinafter referred to as “platinum”). Or a conductive oxide layer having a rutile structure or a spinel structure (hereinafter abbreviated as “rutile-type oxide layer”). Platinum group elements are Ru, Rh, Pd, Os, Ir, and Pt. Of these, Ir and Pt are particularly preferable because excellent crystal orientation with a crystal growth surface of (111) can be obtained.

Further, as the conductive oxide having a rutile structure, for example _{RuO 2, IrO 2, OsO 2} , RhO 2, ReO 2, MoO 2, CrO 2, WO 2, SnO 2-x and the like. Examples of the conductive oxide having a spinel structure include LiTi ₂ O ₄ , LiV ₂ O ₄ , and Fe ₃ O ₄ .

A Ti film or a TiO ₂ film having a thickness of about 10 nm may be formed between the silicon oxide film 12 and the lower electrode layer 13. Adhesion between the silicon oxide film 12 and the lower electrode layer 13 can be improved.

The ferroelectric oxide layer 14 is made of a conductive oxide having a thickness of 10 nm to 500 nm, containing Pb atoms, and having a perovskite structure. Specifically, the ferroelectric oxide layer 14 may have a perovskite structure, for example, PZT represented by a general formula of Pb (Zr _1−x Ti _x ) O ₃ (0 ≦ x ≦ 1). . Further, PbNi _1/3 Nb _2/3 O ₃ represented by the general formula of Pb (B ′ _1/3 B ″ _2/3 ) O ₃ (B ′: divalent metal, B ″: pentavalent metal) PbCo _1/3 Nb _2/3 O ₃ , PbMg _1/3 Nb _2/3 O ₃ , PbZn _1/3 Nb _2/3 O ₃ , PbMn _1/3 Nb _2/3 O ₃ , PbNi _1/3 Ta _2/3 O ₃ , PbCo _1/3 Ta _2/3 O ₃ , PbMg _1/3 Ta _2/3 O ₃ , PbZn _1/3 Ta _2/3 O ₃ , PbMn _1/3 Ta _2/3 O ₃ PbFe _1/2 Nb _1/2 O ₃ represented by the general formula of Pb (B ′ _1/2 B ″ _1/2 ) O ₃ (B ′: trivalent metal, B ″: pentavalent metal), PbSc _1/2 Nb _1/2 O ₃ , PbSc _1/2 Ta _1/2 O ₃ , Pb (B ′ _1/2 B ″ _1/2 ) O ₃ (B ′: divalent metal, B ″: hexavalent example and PbMg _1/2 W _1/2 O ₃ represented by the general formula of the metal), the additive element was further added to the _{PZT, (Pb 1-y La} y) (Zr 1-x Ti x) O 3 0 ≦ x, PLZT represented by the general formula of y ≦ 1), Pb (B '1/3 B "2/3) x Ti y Zr 1-xy O 3 (0 ≦ x, y ≦ 1, B': Divalent metal, B ″: pentavalent metal), Pb (B ′ _1/2 B ″ _1/2 ) _x Ti _y Zr _1-xy O ₃ (0 ≦ x, y ≦ 1, B ′: trivalent B ″: pentavalent metal) or Pb (B ′ _1/2 B ″ _1/2 ) _x Ti _y Zr _1-xy O ₃ (0 ≦ x, y ≦ 1, B ′: divalent A material represented by a general formula of metal (B ″: hexavalent metal) can be used. For example, multi-component crystals such as 0.65PbMg _1/3 Nb _2/3 O ₃ -0.35PbTiO ₃ and 0.5PbNi _1/3 Nb _2/3 O ₃ -0.35PbTiO ₃ -0.15PbZrO ₃ But you can.

  The ferroelectric oxide layer 14 may be formed by using a CVD method (particularly, a metal organic chemical vapor deposition (MOCVD) method), a sputtering method, a CSD (Chemical Solution Deposition) method, a PLD (Pulse Laser Deposition) method, or the like. it can. Although it is not limited as long as it is a method applicable to a large-area substrate, the CSD method is preferable in that it can be easily formed on a relatively large-area substrate.

The diffusion prevention layer 15 is formed by a CVD method, a sputtering method, a CSD method, a PLD method, or the like, and is made of, for example, a conductive oxide material. Of the conductive oxide materials, an oxide having a perovskite structure is preferable. Since the ferroelectric oxide layer 14 has a perovskite structure, it can be epitaxially grown, so that the crystallinity is improved. Since the crystallinity is good, the specific resistance value is reduced. In a conductive oxide having a perovskite structure, it is preferable that ions such as Sr ²⁺ , La ³⁺ , Ca ²⁺ and Bi ³⁺ whose ionic radius is smaller than Pb ²⁺ occupy the A site of the perovskite structure. Such oxides include SrRuO ₃ , SrPbO ₃ , SrVO ₃ , SrCrO ₃ , SrMoO ₃ , (La, Sr) CoO ₃ , (La 1-x Sr x) VO ₃ (0.23 <x <1), LaNiO ₃ , LaCrO ₃ , LaCuO ₃ , CaRuO ₃ , CaVO ₃ , CaCrO ₃ , and the like.

Further, it is preferable that ions having an ion radius of 0.60 nm or more and less than 0.80 nm occupy the B site having a perovskite structure. As such ions, Fe ³⁺ (0.63 nm), Al ³⁺ (0.67 nm), Co ³⁺ (0.67 nm), V ⁵⁺ (0.68 nm), Mn ⁴⁺ (0.68 nm). , Ni ³⁺ (0.70 nm), Mn ³⁺ (0.72 nm), Ti ⁴⁺ (0.75 nm), Ga ³⁺ (0.76 nm), Cr ³⁺ (0.76 nm), Nb ⁵⁺ ( 0.78 nm), Ta ⁵⁺ (0.78 nm), Mo ³⁺ (0.79 nm) (the parentheses indicate ionic radii).

Further, Pb ⁴⁺ may occupy the B site of the perovskite structure. It is considered that the ferroelectric oxide layer 14 has a function of preventing Pb atom diffusion and supplying Pb atoms to the Pb vacancies of the ferroelectric oxide layer 14. Examples of such an oxide include BaPbO ₃ and (Ba, Sr) PbO ₃ .

  The diffusion preventing layer 15 is set to a thickness in the range of 1 nm to 100 nm, preferably 5 nm to 100 nm. If it is thinner than 1 nm, the effect of preventing the diffusion of Pb atoms is not sufficient, and if it exceeds 100 nm, the resistance value becomes excessively large.

Furthermore, the specific resistance of the diffusion preventing layer 15 is preferably 2 × 10 ⁻⁶ Ω · cm to 2 × 10 ⁻³ Ω · cm. By reducing the specific resistance, the thickness of the diffusion preventing layer 15 can be sufficiently secured.

  The upper electrode layer 16 is formed in the same manner as the lower electrode layer 13, and has a thickness of, for example, 5 nm to 200 nm. Similar to the lower electrode layer 13, the upper electrode layer may be the platinum group alloy layer or the rutile oxide layer described above, or may be a laminate in which a rutile oxide layer and a platinum group alloy layer are sequentially laminated.

According to the present embodiment, the diffusion prevention layer 15 is provided to prevent the diffusion of Pb atoms in the ferroelectric oxide layer 14 and to prevent the formation of Pb vacancies in the ferroelectric oxide layer 14. Can do. According to the study of the inventor of the present application, when IrO ₂ or RuO ₂ is used as the upper electrode layer 16 in the rutile type oxide layer, the upper electrode is formed from the ferroelectric oxide layer 14 by providing the diffusion preventing layer 15. It has been found that the effect of preventing the diffusion of Pb atoms into the layer 16 is particularly great. This is presumably due to the fact that the conductive oxide of the upper electrode layer 16 has a particulate structure and that it is difficult for Pb atoms to enter the A site of the diffusion prevention layer 15 in terms of ionic radius.

  The diffusion prevention layer 15 may be provided between the lower electrode layer 13 and the ferroelectric oxide layer 14, and between the lower electrode layer 13 and the ferroelectric oxide layer 14, It may be provided both between the physical layer 14 and the upper electrode layer 16. By providing both, diffusion of Pb atoms can be further prevented. Hereinafter, examples according to the present embodiment will be described.

[Example 1]
A Si single crystal substrate having a main surface of 6 inches (100) was used, and a silicon oxide film having a thickness of 100 nm was formed on the surface of the Si single crystal substrate by thermal oxidation. Next, an Ir film having a thickness of 150 nm was formed thereon as a lower electrode layer by sputtering.

A PZT film was formed on the surface of such a structure. Specifically, a metal organic chemical vapor deposition (MOCVD) method is used, and Pb (THD) ₂ (lead bis (tetramethylheptanedione)) is used as the Pb source and Zr (DMHD) _{4 is} used as the Zr source. (Zirconium tetrakis (dimethylheptadionate)) and Ti (iPrO) ₂ (THD) ₂ (titanium (diisoproxy) (tetramethylheptanedione)) were used as a Ti source. A liquid obtained by dissolving these materials at a concentration of 0.3 mol / L using tetrahydrofuran (THF) as a solvent was used as a starting material. The flow rate of the starting material is controlled by a liquid mass flow controller so that the Pb / (Zr + Ti) flow rate ratio is adjusted to 0.78, the Zr / (Zr + Ti) flow rate ratio is adjusted to 0.46, and only the THF solvent is added to the THF / ( Pb + Zr + Ti) was flowed at a flow rate ratio of 1.33 and was introduced into a vaporizer maintained at 260 ° C. for gasification.

N ₂ gas was used as a carrier gas, the flow rate was 300 sccm, and the starting material was introduced into the vaporizer at the same time. The gasified organometallic material and carrier gas were mixed with oxygen gas set at a flow rate of 2500 sccm in a gas mixing chamber at the top of the reaction chamber.

  The Si single crystal substrate on which the above structure was formed was placed on the susceptor above the heating heater, heated for 240 seconds so that the substrate temperature was uniform at 600 ° C., and the CVD reaction chamber was adjusted to a total pressure of 670 Pa. . Next, the gas mixed in the gas mixing chamber was introduced into the CVD reaction chamber through a shower head. After the substrate is heated, the valve connecting the exhaust line from the vaporizer is closed, and at the same time, the valve of the piping from the vaporizer to the gas mixing chamber is opened and introduced into the mixing chamber together with the carrier gas. Meanwhile, oxygen gas was also introduced into the mixing chamber and mixed with the raw material gas. The gas mixed in the gas mixing chamber was sent through a shower head to a deposition chamber maintained at 670 Pa, and a PZT film was formed on the Ir film until the film thickness became 120 nm.

After cooling to room temperature, an SrRuO ₃ film was formed as a diffusion prevention layer on the PZT film by sputtering. After evacuating the chamber to 5 × 10 ⁻⁴ Pa or less with a rotary pump and a cryopump, Ar gas is introduced at 50 sccm, the pressure in the chamber is adjusted to 1 Pa, and a SrRuO ₃ sintered body is used as a sputtering target at a direct current of 300 W. It was discharged to form a 5 nm thick SrRuO ₃ film.

Next, an upper electrode layer of an IrO ₂ film having a thickness of 50 nm was formed on the SrRuO ₃ film by sputtering. Thus, a ferroelectric capacitor composed of IrO ₂ film / SrRuO ₃ film / PZT film / Ir film was formed.

Next, the ferroelectric capacitor was processed into a size of 50 μm × 50 μm by IrO ₂ film / SrRuO ₃ film by photolithography and etching, and the electrical characteristics of the ferroelectric capacitor were evaluated. A voltage of 3 V was applied between the Ir film and the IrO ₂ film with the polarities reversed alternately to repeat the polarization inversion of the PZT film.

FIG. 2 is a diagram illustrating the relationship between the normalized polarization amount and the number of polarization inversions. In the figure, the vertical axis is shown normalized by the initial polarization amount. Referring to FIG. 2, it can be seen that even if the polarization inversion is repeated, it does not decrease as compared with the initial polarization, and the polarization amount is about 10 ¹⁰ times as large as the initial polarization amount. Therefore, by providing the diffusion preventing layer of the SrRuO ₃ film, it was possible to prevent the diffusion of Pb atoms from the PZT film and improve the fatigue characteristics.

[Examples 2 to 6]
In Examples 2 to 6, ferroelectric capacitors were formed in the same manner as in Example 1 except that the following conductive material was used instead of the SrRuO ₃ film of the diffusion prevention layer of Example 1. . Among Examples 2 to 6, in any example, the polarization inversion was repeated in the same manner as in Example 1, and no decrease in the amount of polarization was observed even 10 ¹⁰ times.

Example 2: SrPbO ₃ film Example 3: (La, Sr) CoO ₃ film Example 4: LaNiO ₃ film Example 5: SrVO ₃ film Example 6: LaCrO ₃ film (second embodiment)
FIG. 3 is a fragmentary cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

  Referring to FIG. 3, the semiconductor device 20 according to the second embodiment includes a substrate 11, a silicon oxide film 12, a lower electrode layer 13, a diffusion prevention layer 21, and a ferroelectric oxide layer 14 on the substrate 11. The upper electrode layer 16 is sequentially laminated. In the semiconductor device 20 of the present embodiment, the diffusion preventing layer 21 is provided between the lower electrode layer 13 and the ferroelectric oxide layer 14, so that the lower electrode layer 13 of Pb atoms in the ferroelectric oxide layer 14. Diffusion into the ferroelectric oxide layer 14 can be prevented, and formation of Pb atom deficiency can be prevented.

  The diffusion prevention layer 21 is formed on the lower electrode layer 13 by a CVD method, a sputtering method, a CSD method, a PLD method, or the like, and is formed of the same material as the diffusion prevention layer 15 described in the first embodiment. The diffusion prevention layer 21 is preferably made of an oxide having a perovskite structure. Since the epitaxial growth is performed in the (111) direction with respect to the crystal plane of the lower electrode layer 13, the crystallinity is good. As a result, the crystallinity of the ferroelectric oxide layer 14 formed on the diffusion preventing layer 21 can be improved.

  The manufacturing method of the semiconductor device according to the present embodiment is the same as that of the first embodiment by changing the order of forming the ferroelectric oxide layer 14 and the diffusion prevention layer 15 in the first embodiment. Can be done. Further, the following manufacturing method may be used in the step of forming the ferroelectric oxide layer 14.

  A silicon oxide film 12, a lower electrode layer 13, and a diffusion prevention layer 21 are sequentially formed on the substrate 11 by a method similar to the method described in the first embodiment.

Next, a ferroelectric oxide layer 14 made of a PZT (Pb (Zr, Ti) O ₃ ) film is formed on the diffusion prevention layer 21 by, eg, MOCVD. The substrate temperature is set to 600 ° C. As described in Example 1 of the first embodiment, the organic metal material, the carrier gas, and the oxygen gas are mixed and vaporized, introduced into the CVD reaction chamber, and a PZT film having a predetermined thickness on the diffusion prevention layer 21. Is formed.

  Simultaneously with the completion of the formation of the PZT film having a predetermined thickness, the Pb vapor generated using the Pb vapor deposition source is supplied to the vacuum chamber of the CVD reaction chamber in which the substrate 11 formed up to the PZT film is installed. By filling the vacuum vessel with Pb vapor, it is possible to prevent the Pb atoms from the PZT film from being substantially dissociated. In particular, since the temperature is high immediately after the formation of the PZT film, the Pb atoms are easily dissociated, and by using this method, the loss of Pb atoms in the PZT film can be suppressed. Note that the substrate 11 may be transferred from the CVD reaction chamber to a dedicated apparatus by a transfer tube to perform such processing.

  FIG. 4 is a conceptual diagram showing a state of processing when the substrate on which the PZT film is formed is cooled in the vacuum vessel. Referring to FIG. 4, the vacuum container 30 includes a heater 30a for heating the entire vacuum container 30, a Pb evaporation source 32 including a Pb material 31 and a Pb evaporation source heater 32a, and a substrate heater 33a. 11 and a heater 30a that heats the entire vacuum container 30, and the heaters 30a, 32a, and 33a are provided with temperature sensors 30b, 32b, and 33b that detect temperature. . Further, the heaters 30a, 32a, 33a and the temperature sensors 30b, 32b, 33b are connected to the temperature control device 34, and the temperature control device 34 controls the temperatures of the Pb evaporation source 32, the substrate holder 33, and the vacuum vessel 30, respectively. It has a configuration. Further, the vacuum container 30 is provided with a gas supply system 36 including a gas cylinder 36a and a mass flow controller 36b, and a gas exhaust system 38 including a rotary pump 38a and a cryopump 38b, and the inside of the vacuum container 30 can be regulated. .

  The heating temperature of the Pb evaporation source 32 is set so that a Pb vapor pressure that is larger than the Pb partial pressure of the PZT film determined by the temperature of the substrate 11 (hereinafter referred to as “substrate temperature”) is formed. Here, the PbT partial pressure of the PZT film is the vapor pressure of Pb among the components dissociated from the surface and gasified when the PZT film is kept at a certain temperature. The Pb partial pressure can be obtained, for example, by placing a PZT film in a sealed container, heating the entire container including the PZT film, and measuring the number of Pb atoms generated. Specifically, the relationship between the substrate temperature and the heating temperature of the Pb evaporation source is set as follows.

  FIG. 5 is a schematic diagram showing a Pb partial pressure curve and a Pb vapor pressure curve of the PZT film. The Pb partial pressure is obtained from the temperature characteristic of the Pb partial pressure of the PZT film with respect to the substrate temperature Tw, the temperature Tp at which the vapor pressure of Pb is equal to the Pb partial pressure is obtained from the Pb vapor pressure curve, and the heating temperature of the Pb evaporation source The temperature of Ts is set higher than Tp. By setting such a temperature relationship, the Pb vapor pressure in the atmosphere of the vacuum vessel 30 shown in FIG. 4 becomes higher than the Pb partial pressure, so that the number of Pb atoms supplied from the atmosphere is large. It is possible to prevent substantial dissociation of atoms and prevent formation of Pb vacancies in the PZT film.

  The temperature of the vacuum container 30 itself is preferably set to the heating temperature Ts of the Pb evaporation source 32 by heating with the heater 30a provided in the vacuum container 30. It can suppress that Pb vapor | steam in the vacuum vessel 30 adheres to an inner wall, and Pb vapor pressure falls.

  Next, the substrate temperature Tw is gradually lowered, and the heating temperature Ts of the Pb evaporation source 32 is lowered while maintaining the above temperature relationship accordingly. The temperature decreasing rate is preferably set to 0.1 ° C./min to 10 ° C./min. Temperature control can be facilitated.

  The ratio of Pb vapor pressure to Pb partial pressure (Pb vapor pressure / Pb partial pressure) is preferably greater than 1 and less than 1000. When the Pb vapor pressure becomes excessively large, the Pb vapor is easily solidified on the surface of the PZT film, and a problem of forming a conductive film occurs. When the Pb vapor pressure is excessive, an inert gas such as Ar gas is supplied by the gas supply system 36 and the gas exhaust system 38 to exhaust the atmospheric gas containing Pb vapor.

  In addition, when performing the said process, it is preferable to grind the surface of the Pb material 31 of the Pb evaporation source 32 by dry etching in a high vacuum in advance. PbO is easily formed on the surface of the Pb material in the atmosphere, and a desired Pb vapor pressure can be obtained by grinding the PbO.

  Returning to FIG. 3, the upper electrode layer 16 is then formed on the PZT film in the same manner as in the first embodiment. Thus, the semiconductor device 20 according to the present embodiment is formed.

  According to the present embodiment, after the PZT film as the ferroelectric oxide layer is deposited, the atmosphere in which the PZT film is exposed until the substrate is cooled from the temperature during deposition to room temperature is the Pb of the PZT film. Since it is filled with the Pb vapor pressure larger than the partial pressure, it is possible to prevent the dissociation of Pb atoms from the PZT film and to prevent the formation of Pb vacancies in the PZT film. Therefore, leakage current can be reduced, power consumption can be reduced, and fatigue characteristics can be improved.

(Third embodiment)
FIG. 6 is a circuit diagram of an FeRAM according to the third embodiment of the present invention, and FIG. 7 is a cross-sectional view of the FeRAM according to the third embodiment of the present invention.

Referring to FIG. 6, FeRAM employs a 2T2C memory cell system that uses two selection transistors T _A and T _C and two ferroelectric capacitors C _A and C _C to store 1-bit information. ing. Figure 7 is a sectional view taken across the memory cell 41, 42 adjacent connected to the bit line BL shown in FIG. 6, the selection transistor T _A of the memory cell 41, T _B and the ferroelectric capacitor C _A and C _B are shown.

Referring to FIG. 7, FeRAM50 of this embodiment, the word line WL1 as shown in FIG. 6, WL2 selection transistor T _A, the gate electrode 54A of the T _B, are formed as 54B. Selection transistors T _A, T _B of the diffusion regions 56A, 56B are ferroelectric capacitor C _A having a ferroelectric capacitor film 63, electrically connected to the lower electrode layer 61 of C _B via the contact plugs 60A, 60B Has been. The ferroelectric capacitors C _A and C _B have the same configuration as that described in the first embodiment, and the lower electrode layer 61, the ferroelectric oxide layer 62, the diffusion prevention layer 63, and the upper electrode layer. It has a planar stack type ferroelectric capacitor structure in which 64 are sequentially stacked. Further, the ferroelectric capacitors C _A and C _B have the upper electrode layer 64 covered with the silicon oxide film 65, and the first layer wiring through the contact holes 66A and 66B formed in the silicon oxide film 65. It is connected to certain plate lines 74A and 74B (PL1 and PL2 shown in FIG. 6). Further, the diffusion region 56C is connected to the bit line 84 formed above the ferroelectric capacitors C _A and C _B via contact plugs 70, 74C and 80.

  Next, the manufacturing process of the FeRAM of this embodiment will be described. FIG. 8A to FIG. 10B are diagrams showing the manufacturing process of the FeRAM of this embodiment.

In the step of FIG. 8A, an element isolation region 52 and an element region 53 are formed on a substrate 51 by STI (Shallow Trench Isolation) by a CMOS process, and a silicon insulating film or the like is formed on the element region 53. the gate insulating film 57 is formed, thereon the gate electrode 54A, 54B is formed to form a selection transistor T _a, T _B. The gate electrodes 54A and 54B are provided so as to extend perpendicular to the paper surface.

8A, a SiN insulating film 55 is formed on the selection transistors T _A and T _B and the upper surface of the substrate 51, and an interlayer insulating film 58 made of a silicon oxide film is further formed. Contact holes are formed on the upper surfaces of the diffusion regions 56A and 56B of the element region 53 by photolithography and RIE (anisotropic etching) of the resist film, and the TiN adhesion film 59-1 and tungsten 59-2 are filled. Thus, contact plugs 60A and 60B for connecting the diffusion regions 56A and 56B and ferroelectric capacitors C _A and C _B described later are formed. Next, the upper surfaces of the interlayer insulating film 58 and the contact plugs 60A and 60B are polished by a CMP (Chemical and Mechanical Polishing) method.

  Next, in the step of FIG. 8B, a Ti adhesion film 61 and a lower electrode layer 62 are sequentially formed on the upper surfaces of the interlayer insulating film 58 and the contact plugs 60A and 60B. Here, the Ti adhesion film 61 has a thickness of 100 nm and the lower electrode layer 62 has a thickness of 50 nm, for example, and is made of a platinum group element or an alloy thereof.

  In the step of FIG. 8B, a ferroelectric oxide layer 62 made of a PZT film is further formed on the lower electrode layer 61. The ferroelectric oxide layer 62 is formed by RF sputtering, CSD method, CVD method or the like. Here, using an RF sputtering method, an Ar gas pressure of 1.1 Pa and an RF power of 1.0 kW were set, and a thickness of 200 nm was formed.

In the step of FIG. 8B, a diffusion preventing layer 63 made of a conductive oxide having a thickness of 20 nm is further formed on the ferroelectric oxide layer 62 by using a CVD method, a sputtering method, or the like. As the conductive oxide, those described in the first embodiment can be used. Here, a (La, Sr) CoO ₃ film was used.

In the step of FIG. 8B, an upper electrode layer 64 is further formed on the diffusion prevention layer 63. The upper electrode layer 64 has, for example, a thickness of 200 nm, and a conductive oxide such as a platinum group alloy layer, a conductive oxide such as IrO ₂ , RuO ₂ , SrRuO ₂ , or a stacked body thereof, and the ferroelectric capacitor film 63 side is conductively oxidized. For example, a laminated body in which an IrO ₂ film and an Ir film are sequentially deposited is used. For example, when forming Pt, the upper electrode layer 64 may be formed by RF sputtering in an Ar atmosphere having a concentration of oxygen of 5% or less. Here, an IrO ₂ film was formed.

  In the step of FIG. 8B, the ferroelectric oxide layer 62 is further crystallized by rapid thermal processing (RTA) for 90 seconds at about 600 ° C.

Next, in the step of FIG. 8C, the lower electrode layer 61, the ferroelectric oxide layer 62, the diffusion prevention layer 63, and the upper electrode layer 64 on the contact plugs 60A and 60B are left by photolithography and RIE. Thus, the ferroelectric capacitors C _A and C _B are formed.

  Next, in the step of FIG. 9A, a silicon oxide film 65 covering the structure of FIG. 8C is deposited by CVD, and an interlayer insulating film 66 is further deposited. Next, the upper surface of the deposited interlayer insulating film 66 is polished and planarized by the CMP method.

  9A, the diffusion region 56C is exposed through the stacked body of the SiN insulating film 55 / interlayer insulating film 58 / silicon oxide film 65 / interlayer insulating film 66 by photolithography and RIE. A contact hole to be formed is formed, and a TiN adhesion film 68 and tungsten 69 are filled to form a contact plug 70.

In the process of FIG. 9A, the silicon oxide film 65 and the interlayer insulating film 66 deposited on the upper electrode layer 64 of the ferroelectric capacitors C _A and C _B are further applied to the photolithography method and the RIE method. Contact holes 66A and 66B that expose the upper electrode layer 64 are formed.

Next, in the process of FIG. 9B, a TiN adhesion film 71, an Al metal first layer 72, and a TiN adhesion film 73 are typically sequentially deposited to a thickness of 20 nm on the structure of FIG. 9A. . Next, the TiN adhesion film 71 \ Al metal first layer 72 \ TiN adhesion film 73 is etched by photolithography and RIE to form a wiring pattern extending perpendicularly to the paper surface, and the ferroelectric capacitors C _A , wiring pattern 74A as a plate line connected to the upper electrode layer 64 of C _B, 74B, and to form an electrode pattern 74C which connects to the contact plug 70.

  Next, in the step of FIG. 10A, an interlayer insulating film 76 is deposited on the structure of FIG. 9B by the CVD method, and the surface of the interlayer insulating film 76 is polished and planarized by the CMP method. Next, a contact hole exposing the electrode pattern 74C is formed in the interlayer insulating film 76, and a contact plug 80 is formed by filling a TiN adhesion film 78 and a tungsten plug 79 filling the contact hole.

  Next, in the process of FIG. 10B, a TiN adhesion film 81, an Al metal second layer 82, and a TiN adhesion film 83 are sequentially formed on the structure of FIG. A bit line pattern 84 as a bit line extending in the horizontal direction is formed on these laminates by photolithography and RIE. Thereby, the bit line pattern 84 and the diffusion region 56C are electrically connected. Next, a silicon oxide film 85 covering the bit line pattern 84 and the interlayer insulating film 76 is formed by CVD, and a passivation film 86 is further formed. Thus, the FeRAM of the present embodiment shown in FIG. 7 is formed.

  FIG. 11 is a diagram showing a composition profile in the depth direction from the upper electrode layer 64 of the FeRAM ferroelectric capacitor according to the present embodiment. In the figure, the horizontal axis represents the Ar etching time and corresponds to the depth ground by Ar etching.

  Referring to FIG. 11, although the ferroelectric capacitor has undergone the heat treatment, the profile of the Pb element rapidly decreases at the position of the diffusion preventing layer, and diffusion from the PZT film to the upper electrode layer is prevented. I understand that

  On the other hand, FIG. 12 is a diagram showing a composition profile in the depth direction from the upper electrode layer of a ferroelectric capacitor of a comparative example not according to the present invention. The ferroelectric capacitor of this comparative example is the same as the FeRAM ferroelectric capacitor according to the present embodiment except that no diffusion prevention layer is provided. Referring to FIG. 12, the strength of the Pb element has a base from the interface between the PZT film and the upper electrode layer to the upper electrode side. That is, since the upper electrode layer does not originally contain Pb, it can be seen that Pb atoms are diffused into the upper electrode layer.

According to the present embodiment, since the ferroelectric oxide layer 62 of the ferroelectric capacitors C _A and C _B is covered with the diffusion preventing layer 63, the ferroelectric oxide layer 62 is transferred to the upper electrode layer 64. Pb atoms are prevented from diffusing and formation of Pb vacancies in the ferroelectric oxide layer 62 is prevented. Therefore, leakage current can be reduced, the fatigue characteristics of FeRAM can be improved, and long-term reliability can be improved.

It should be noted that the ferroelectric capacitors C _A and C _B of this embodiment may be combined with the treatment with Pb vapor when forming the ferroelectric oxide layer described in the second embodiment. Also, the ferroelectric capacitor C _A of the present embodiment, the ferroelectric capacitor of the second embodiment may be applied instead of C _B. Furthermore, the configurations of the ferroelectric capacitors C _A and C _B of the first and second embodiments may be combined.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed.

  For example, the PZT film described above exhibits excellent piezoelectricity and is also used as an actuator. Therefore, the present invention can be applied to such an actuator and has an excellent Pb diffusion preventing effect. Therefore, the displacement with respect to the applied voltage does not deteriorate over a long period of time and has long-term reliability. Further, the present invention is not limited to the PZT film, and the present invention can be applied to an actuator using an oxide layer that exhibits piezoelectricity and has a perovskite structure containing Pb.

In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1) A semiconductor device having a ferroelectric capacitor comprising a ferroelectric oxide layer, and a first electrode layer and a second electrode layer sandwiching the ferroelectric oxide layer,
The ferroelectric oxide layer is made of an oxide containing Pb;
A ferroelectric oxide layer is provided between at least one of the first electrode layer and the ferroelectric oxide layer and between the ferroelectric oxide layer and the second electrode layer. A semiconductor device comprising a diffusion preventing layer for preventing diffusion of Pb therein.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the diffusion preventing layer is a conductive oxide layer, and the conductive oxide layer is made of a material having a perovskite structure.
(Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the material having a perovskite structure has an ion radius smaller than an ion radius of a Pb ²⁺ ion in an ion occupying the A site of the crystal structure.
(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the ions occupying the A site include at least one of Sr ²⁺ , La ³⁺ , Ca ²⁺ and Bi ³⁺ .
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 2 to ⁴ , wherein the material having the perovskite structure has Pb ⁴⁺ ions occupying a B site of the crystal structure.
(Additional remark 6) The said diffusion prevention layer is set to 1 nm-100 nm in thickness, The semiconductor device as described in any one of Additional remarks 1-5 characterized by the above-mentioned.
(Supplementary note 7) The semiconductor according to any one of Supplementary notes 1 to 6, wherein the first electrode layer or the second electrode layer is a conductive oxide layer having a rutile structure or a spinel structure. apparatus.
(Supplementary Note 8) The rutile structure or an electrically conductive oxide layer having a spinel structure, IrO _2, RuO _2, and of the appended 1 to 7, characterized in that any one of a group of SrRuO _2, The semiconductor device according to any one of claims.
(Additional remark 9) Manufacturing method of semiconductor device which has ferroelectric capacitor which consists of a ferroelectric oxide layer and the 1st electrode layer which pinches | interposes this ferroelectric oxide layer, and a 2nd electrode layer in a semiconductor substrate Because
A first step of forming the first electrode layer;
A second step of forming the ferroelectric oxide layer;
A third step of forming the second electrode layer,
In the second step,
Heating the semiconductor substrate in a vacuum container to deposit a ferroelectric oxide layer;
Next, a method of manufacturing a semiconductor device, wherein Pb vapor is supplied into the vacuum container and cooling is performed while controlling the Pb vapor pressure to a predetermined vapor pressure.
(Additional remark 10) Manufacturing method of semiconductor device which has ferroelectric capacitor which consists of a ferroelectric oxide layer and the 1st electrode layer which pinches | interposes this ferroelectric oxide layer, and a 2nd electrode layer in a semiconductor substrate Because
A first step of forming the first electrode layer;
A second step of forming the ferroelectric oxide layer;
A third step of forming the second electrode layer,
Preventing Pb from diffusing into the first or second electrode layer between at least one of the first step and the second step and between the second step and the third step. Further comprising the step of forming a diffusion barrier layer
In the second step,
Heating the semiconductor substrate in a vacuum container to deposit a ferroelectric oxide layer;
Next, a method of manufacturing a semiconductor device, wherein Pb vapor is supplied into the vacuum container and cooling is performed while controlling the Pb vapor pressure to a predetermined vapor pressure.
(Additional remark 11) The said Pb vapor pressure is made higher than Pb partial pressure of the surface of a ferroelectric oxide layer, The manufacturing method of the semiconductor device of Additional remark 11 characterized by the above-mentioned.
(Additional remark 12) The manufacturing temperature of the semiconductor device as described in any one of additional remarks 9-11 which control Pb vapor pressure by controlling the heating temperature of the Pb evaporation source provided in the said vacuum vessel. .
(Supplementary note 13) The semiconductor according to any one of supplementary notes 9 to 12, wherein a gas containing excess Pb vapor pressure in the vacuum vessel is replaced with an inert gas to control Pb vapor pressure. Device manufacturing method.
(Supplementary note 14) The method for manufacturing a semiconductor device according to any one of supplementary notes 9 to 13, further comprising a heating step of crystallizing the ferroelectric oxide layer after the third step. .

1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the relationship between the normalization amount of polarization of the ferroelectric capacitor used for the semiconductor device which concerns on Example 1 of this invention, and the frequency | count of polarization inversion. It is principal part sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram which shows the mode of the process at the time of cooling the board | substrate in which the PZT film | membrane was formed. It is a schematic diagram which shows the relationship between the Pb partial pressure curve of a PZT film | membrane, and the vapor pressure curve of Pb. It is a circuit diagram of FeRAM which concerns on the 3rd Embodiment of this invention. It is sectional drawing of FeRAM which concerns on 3rd Embodiment. (A)-(C) are figures which show the manufacturing process (the 1) of FeRAM which concerns on 3rd Embodiment. (A) And (B) is a figure which shows the manufacturing process (the 2) of FeRAM which concerns on 3rd Embodiment. (A) And (B) is a figure which shows the manufacturing process (the 3) of FeRAM which concerns on 3rd Embodiment. It is a figure which shows the composition profile of the depth direction from the upper-electrode layer of the ferroelectric capacitor of FeRAM which concerns on this Embodiment. It is a figure which shows the composition profile of the ferroelectric capacitor of the comparative example which is not based on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 20 Semiconductor device 11 Substrate 12 Silicon oxide film 13, 61 Lower electrode layer 14, 62 Ferroelectric oxide layer 15, 21, 63 Diffusion prevention layer 16, 64 Upper electrode layer 50 FeRAM
C _A and C _B ferroelectric capacitors

Claims (5)

A semiconductor device having a ferroelectric capacitor comprising a ferroelectric oxide layer, and a first electrode layer and a second electrode layer sandwiching the ferroelectric oxide layer,
The ferroelectric oxide layer is made of an oxide containing Pb;
A ferroelectric oxide layer is provided between at least one of the first electrode layer and the ferroelectric oxide layer and between the ferroelectric oxide layer and the second electrode layer. A semiconductor device comprising a diffusion preventing layer for preventing diffusion of Pb therein.   2. The semiconductor device according to claim 1, wherein the diffusion preventing layer is a conductive oxide layer, and the conductive oxide layer is made of a material having a perovskite structure. 3. The semiconductor device according to claim 2, wherein the material having the perovskite structure has an ion radius smaller than an ion radius of a Pb ²⁺ ion. A method of manufacturing a semiconductor device having a ferroelectric capacitor comprising a ferroelectric oxide layer and a first electrode layer and a second electrode layer sandwiching the ferroelectric oxide layer on a semiconductor substrate,
A first step of forming the first electrode layer;
A second step of forming the ferroelectric oxide layer;
A third step of forming the second electrode layer,
Preventing Pb from diffusing into the first or second electrode layer between at least one of the first step and the second step and between the second step and the third step. Further comprising the step of forming a diffusion barrier layer
In the second step,
Heating the semiconductor substrate in a vacuum container to deposit a ferroelectric oxide layer;
Next, a method of manufacturing a semiconductor device, wherein Pb vapor is supplied into the vacuum container and cooling is performed while controlling the Pb vapor pressure to a predetermined vapor pressure. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the Pb vapor pressure is made higher than the Pb partial pressure of the surface of the ferroelectric oxide layer.

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