JP5412754B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same, and more particularly to a semiconductor device including a ferroelectric capacitor and a memory cell transistor and a method for manufacturing the same.

In recent years, with the advancement of digital technology, high-capacity data has been processed and stored at high speed, and high integration and high performance of semiconductor devices used in electronic devices are required. Has been. For example, in a semiconductor memory device which is an example of a semiconductor device, a DRAM (
Dynamic Random Access Memory) is being highly integrated. Such DRA
As the capacitor insulating film of the capacitor used for M, a ferroelectric material or a high dielectric constant material is used instead of the conventional silicon oxide or silicon nitride. Further, a ferroelectric film having spontaneous polarization characteristics is used as a capacitor insulating film in order to realize a nonvolatile RAM capable of writing and reading at a lower voltage and higher speed. Such a semiconductor memory device is generally called a ferroelectric memory (FeRAM).

The FeRAM has a ferroelectric capacitor in which a ferroelectric film is disposed as a capacitor dielectric between a pair of electrodes, and stores information using the hysteresis characteristics of the ferroelectric film. The ferroelectric film has the property of causing polarization according to the applied voltage between the electrodes and having spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed, so that information can be read if the spontaneous polarization is detected. Such FeRAM has features such as high-speed operation, low power consumption, and excellent write / read durability, and further development is expected in the future.

However, the characteristics of the conventional ferroelectric capacitor are easily changed by hydrogen gas or moisture. In the case of a standard ferroelectric capacitor, for example, a lower electrode made of a Pt film, a ferroelectric film made of a PZT film (PbZr _1-X TiXO ₃ film), and an upper electrode made of a Pt film are provided. It has a structure in which the layers are sequentially stacked. Such a standard ferroelectric capacitor is known to lose the ferroelectricity of the PZT film when heated to about 200 ° C. in an atmosphere having a hydrogen partial pressure of about 40 Pa.

In addition, if heat treatment is performed in a state where moisture is adsorbed on the ferroelectric capacitor or in the vicinity of the ferroelectric capacitor, the ferroelectricity of the ferroelectric film of the ferroelectric capacitor is significantly deteriorated. It is known that.

For this reason, as a process after forming the ferroelectric film in the manufacturing process of the conventional FeRAM, the generation of moisture is as small as possible and a low temperature process is selected. The process for forming the interlayer insulating film includes, for example, CVD using a source gas that generates a relatively small amount of hydrogen (
Chemical Vapor Deposition) method has been selected.

Furthermore, as a technique for preventing the deterioration of the ferroelectric film due to hydrogen or moisture, a technique for forming an aluminum oxide film so as to cover the ferroelectric capacitor, or an oxidation on the interlayer insulating film formed on the ferroelectric capacitor. A technique for forming an aluminum film has been proposed. The aluminum oxide film has a function of preventing diffusion of hydrogen and moisture. For this reason, the formation of the aluminum oxide film prevents hydrogen and moisture from reaching the ferroelectric film, thereby preventing deterioration of the ferroelectric film due to hydrogen and moisture. In the ferroelectric memory, an aluminum oxide film that directly covers the ferroelectric capacitor is formed as a hydrogen diffusion preventing film to prevent hydrogen diffusion into the ferroelectric capacitor.

On the other hand, when forming the upper electrode of the ferroelectric capacitor or forming the ferroelectric capacitor, the ferroelectric film is mainly physically damaged by high-energy sputtered particles. If a part of the crystal structure of the ferroelectric film is destroyed due to such physical damage, the characteristics of the ferroelectric capacitor deteriorate.

Therefore, conventionally, various processes as described below have been performed in order to restore such deterioration of the characteristics of the ferroelectric capacitor to its original state.

For example, after patterning the upper electrode film, heat treatment is performed in an oxygen atmosphere, and after that, after patterning the ferroelectric film, the heat treatment is performed again in an oxygen atmosphere. Further, heat treatment is performed in an oxygen atmosphere even after the lower electrode is patterned. Thereafter, a hydrogen diffusion preventing film such as aluminum oxide, titanium oxide, PLZT, or PZT is formed. Such a prior art is disclosed in, for example, Patent Document 1. In addition, it is known to perform heat treatment in an oxygen atmosphere after patterning the upper electrode film and the ferroelectric film, or after forming a ferroelectric capacitor by patterning. In these treatments, the crystallinity of the ferroelectric film is restored by oxygen.

It is also known to form aluminum oxide as a hydrogen barrier film on the upper and side surfaces of the capacitor. More specifically, after processing the dielectric film, aluminum oxide is formed on the entire surface of the dielectric film. Further, after the aluminum oxide and the lower electrode are etched, aluminum oxide is formed on the entire surface to protect the capacitor. Such conventional techniques are disclosed in, for example, Patent Document 2, Patent Document 3, and Patent Document 4.

In order to prevent the ferroelectric film from reacting with hydrogen and being deteriorated when heat-treated in a hydrogen atmosphere, an interlayer film is deposited after forming a pattern on the capacitor, and a TiN film is formed thereon as a hydrogen barrier film. It is known that an interlayer film is further deposited after the formation. Such a prior art is disclosed in Patent Document 5, for example.

In order to prevent the hydrogen barrier film on the side wall portion of the dielectric capacitor from being thin and the barrier performance from being lowered or the film from being peeled off, Ta ₂ O ₅ , Y ₂ is formed after the dielectric capacitor is formed.
It is known to coat with an insulating film of O ₃ , CeO ₂ or HfO ₂ . In this case, it is also known that an Al ₂ O ₃ film is further formed thereon to cover it. Such a conventional technique is disclosed in, for example, Patent Document 6.

In order to prevent the dielectric capacitor from being deteriorated by hydrogen or contaminants, it is known to form a silicon nitride film after forming a protective film of aluminum oxide after forming the dielectric capacitor. Such a conventional technique is disclosed in, for example, Patent Document 7. However, in this method, when the inclination of the side wall of the dielectric capacitor is low, the degree of integration is reduced. When the inclination is high, the hydrogen barrier film on the side wall becomes thin, so that the hydrogen barrier performance is deteriorated.

Further, after forming a ferroelectric capacitor for the purpose of recovering the deterioration of the ferroelectric film with high efficiency, a recovery annealing is performed after forming an aluminum oxide protective film,
A method of forming an aluminum oxide protective film of a layer has been studied. Such a conventional technique is disclosed in, for example, Patent Document 8.

As a prior art for realizing the same object, there is also known a method in which a PZT ferroelectric capacitor is double covered with aluminum oxide having different carbon contents. Such a prior art is disclosed in, for example, Patent Document 9.

In the integrated circuit element, the exposed portion of the capacitor dielectric film including the lower electrode, the dielectric film, and the upper electrode has a metal oxide film having a first density and a second density higher than the first density. A configuration in which a second metal oxide film is provided is known. In such an integrated circuit device manufacturing process, after forming a capacitor, atomic layer deposition is performed using an aluminum precursor gas and an inert gas reactive with oxygen as a pulsing gas and a purge gas, respectively. Thereby, only aluminum oxide is formed on the side surface of the dielectric film. This aluminum oxide becomes a hydrogen barrier film. Thereafter, when the heat treatment is performed to recover the deterioration of the ferroelectric film, the capsule film aluminum oxide is formed on the capacitor and the hydrogen barrier film. Such a conventional technique is disclosed in, for example, Patent Document 10.

In the semiconductor device, the first interlayer insulating film is formed so as to cover the capacitor formed on the lower hydrogen barrier film and to expose the lower hydrogen barrier film at the peripheral edge of the capacitor, and the exposed portion of the lower hydrogen barrier film. There is known a configuration in which is covered with an upper hydrogen barrier film. The upper hydrogen barrier film is formed so as to be in contact with the lower hydrogen barrier film, and the side surface of the upper hydrogen barrier film is disposed so as to form an obtuse angle with the upper surface of the lower hydrogen barrier film. For such prior art,
For example, it is disclosed in Patent Document 11 and Patent Document 12.

Further, as a conventional technique for preventing the deterioration of the ferroelectric film, it is known that a diffusion barrier film is formed on the ferroelectric capacitor and further covered with the diffusion barrier film. The hydrogen barrier film includes at least one of Al oxide, Al nitride, Al nitride oxide, Ta oxide, Ta oxynitride, Ti oxide, and Zr oxide. used. Such a prior art is disclosed in, for example, Patent Document 13.

As a conventional technique for preventing deterioration of a capacitor dielectric due to impurity diffusion, it is known that a blocking film and a capacitor protective film are laminated on the entire surface of the capacitor. The capacitor protection film prevents hydrogen from diffusing into the capacitor dielectric film. The blocking film is formed under the capacitor protection film to prevent the material film formed under the blocking film and the capacitor protection film from reacting with each other and / or volatilization of the capacitor dielectric film. For example, an aluminum oxide film formed by the ALD (Atomic Layer Deposition) method has very good coverage, but damages the ferroelectric film of the capacitor during the film formation or reacts with the dielectric film to cause the capacitor May degrade performance. In order to prevent this, a blocking film has been formed directly on the capacitor. Such a conventional technique is disclosed in, for example, Patent Document 14.

In addition, it is known to employ a high temperature batch etching method for the etching process.
Such conventional techniques are disclosed in, for example, Patent Document 15 and Cited Document 16.

Further, after etching a difficult-to-etch material such as a noble metal electrode, a non-volatile reaction product reattached to the sidewall of the etching mask layer can be removed by using an organic material film or a hard mask TiN on the Ir layer. It is known that layers are sequentially stacked and this stacked film is dry-etched using a photoresist film as a mask. In this case, dry etching of the Ir layer is performed using a gas containing oxygen. Since the organic material film is side-etched during the etching, the side wall reattachment layer made of the reaction product does not occur on the side wall of the organic material film layer. After this, if an ashing process is performed, only the organic material film layer is etched and T serving as a mask is obtained.
The iN layer is easily removed, leaving only the patterned material to be etched. Such a conventional technique is disclosed in, for example, Patent Document 17.

Al and Ti are somewhat oxidized on the surface of the hard mask and in the vicinity thereof, and AlO _x
(For example, Al ₂ O ₃ ) and TiO _x (for example, TiO ₂ ) are formed, but are known to be removed by annealing at 450 ° C. in O ₂ . Such a conventional technique is disclosed in, for example, Patent Document 18.

Further, the protective film of the capacitor is made of Al ₂ O ₃ , ZrO ₂ , HfO ₂ , TiO _x , TaO _x ,
It is known to produce a material selected from the group consisting of SiN and AlN, and to cover the side walls of the lower electrode and the ferroelectric layer and the lower part of the side wall of the upper electrode with the protective film. Such a conventional technique is disclosed in, for example, Patent Document 19.

Then, the first hydrogen barrier film, the lower electrode film, the ferroelectric film, the upper electrode film, and the second hydrogen barrier film are sequentially deposited on the silicon substrate via the insulating film to suppress deterioration due to the hydrogen reduction action. Has been tried. When patterning the upper electrode, the hydrogen barrier film and the upper electrode film are sequentially etched using a mask. Further, a third hydrogen barrier film covering the exposed ferroelectric film is deposited, and the ferroelectric film and the lower electrode film are sequentially etched using the mask formed thereon. As a result, the pattern of the ferroelectric film and the lower electrode self-aligned with the ferroelectric film is formed. For such conventional technology, for example, Patent Documents 20, 21, 2
2, 23, 24, 25, and 26.
JP 2003-332536 A JP-A-2005-116756 JP 2004-349474 A JP 200495861 A JP-A-9-293868 JP 2003-115545 A JP 2001-210798 A JP 2005-183843 A JP 2003-273332 A JP 2002-93797 A Japanese Patent Laid-Open No. 2004-282041 JP 2005-129875 A JP 2002-176149 A JP 2001-111007 A Japanese Patent Laid-Open No. 9-16211 JP 2002-94016 A JP 2001-313282 A JP 2000-133633 A JP 2004-186518 A JP 2001-36026 A JP 2001-168290 A JP 2001-358309 A JP 2002-43540 A JP 2002-280528 A JP 2003-324157 A Japanese Patent No. 3276351

In a semiconductor device provided with a ferroelectric capacitor, the various structures or processes described above are employed in order to suppress the characteristic deterioration of the ferroelectric capacitor, but it is necessary to further prevent the specific deterioration.

The present invention has been made in view of such circumstances, and a main object of the present invention is to enable efficient manufacture of a highly reliable semiconductor device.

According to an aspect of the present application, a semiconductor substrate, a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode sequentially stacked on the semiconductor substrate via an insulating film, and the ferroelectric capacitor A region including a first protective film provided above the upper electrode in the stacking direction and having a portion having a different oxygen concentration distribution in the film thickness direction, the first protective film, and a side wall of the ferroelectric capacitor a second protective film for reducing element diffusion prevention provided, said first penetrates the protective film and the second protective layer, a semiconductor device which comprises a conductive plug reaching the upper electrode Provided .

According to another aspect of the present invention, a step of laminating a lower conductive film, a ferroelectric film, and an upper conductive film above a semiconductor substrate, and a step of forming a first protective film on the upper conductive film And patterning the first protective film and the upper conductive film to form an upper electrode of a capacitor from the conductive film, and heating the ferroelectric film and the first protective film in an oxygen atmosphere. Accordingly, a heat treatment step of forming a portion having a different oxygen concentration in the film thickness direction in the first protective film, and patterning the ferroelectric film and the lower conductive film, from the lower conductive film to the capacitor Forming a lower electrode; forming a second protective film for preventing diffusion of a reducing element covering the first protective film and the capacitor; penetrating the first protective film and the second protective film; Upper electrode The method of manufacturing a semiconductor device which comprises forming a conductive plug is reached, is provided.

According to still another aspect of the present invention, a lower conductive film, a ferroelectric film, and an upper conductive film are sequentially stacked on a semiconductor substrate, and a first hard mask and a first hard mask are formed on the upper conductive film. And forming the second hard mask in sequence, and patterning the lower conductive film, the ferroelectric film, and the upper conductive film using the first and second hard masks to have an upper electrode Forming a ferroelectric capacitor; removing the second hard mask while leaving the first hard mask after the ferroelectric capacitor is formed; and the ferroelectric capacitor and the first the hard mask is heated in an oxygen atmosphere at a heat treatment step of the distribution of the oxygen concentration to oxidize the at least partially the thickness direction of the first mask to form a first protective layer having a different portion, the first 1 Forming a second protective film for preventing reduction element diffusion covering the protective film and the ferroelectric capacitor; and a conductive plug penetrating the first protective film and the second protective film and reaching the upper electrode And a step of forming the semiconductor device.

According to the present invention, since the first protective film having a portion having a different oxygen concentration in the film thickness direction is provided on the capacitor upper electrode, the first protective film allows the reducing substance to permeate into the ferroelectric capacitor. It is possible to prevent the deterioration of the performance of the ferroelectric capacitor.

Further, after patterning the upper electrode of the ferroelectric capacitor using the first protective film as a mask, the first protective film is left as a film for preventing the permeation of the reducing substance without removing the first protective film. Since it did in this way, the process of removing a mask like the past becomes unnecessary, and generation | occurrence | production of a micro foreign material can be prevented. As a result, process deterioration can be prevented and the yield of the semiconductor device can be improved.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to the drawings.

1A to 1L are cross-sectional views of the semiconductor device according to the first embodiment of the present invention during manufacture.

  The semiconductor device is a planar type FeRAM and is manufactured as follows.

  First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.

First, an element isolation insulating film 2 that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon substrate 1 that is a semiconductor substrate. In this embodiment, shallow trench isolation (STI) is formed as the element isolation insulating layer 2. The STI is formed by forming a groove in the element isolation region of the silicon substrate 1 and embedding an insulating film such as silicon oxide therein. Note that the element isolation insulating layer 2 is not limited to the STI, and the LOCOS (Local Oxidat
An insulating film formed by an ion of silicon method may be used.

Next, a p-type impurity such as boron is introduced into the transistor active region in the memory cell region A of the silicon substrate 1 to form the p-well 3. In addition, an n-type impurity is selectively introduced into a predetermined active region in the peripheral circuit region B to form an n-well 4. Thereafter, a gate insulating film 5 is formed on the surface of the active region. The gate insulating film 5 is a silicon oxide film formed by thermal oxidation and has a thickness of about 6 to 7 nm.

Further, an amorphous silicon film and a tungsten silicide film are sequentially formed on the entire surface of the silicon substrate 1 and patterned by using a photolithography technique to form gate electrodes 6A and 6B.
, 6C. Gate electrodes 6A and 6B are formed in memory cell region A. The gate electrode 6C is formed in the peripheral circuit region B. For example, the amorphous silicon film has a thickness of about 50 nm, and the tungsten silicide film has a thickness of about 150 nm. Note that a polysilicon film may be formed instead of the amorphous silicon film.

Two gate electrodes 6A and 6B are formed in parallel with each other on the p-well 3, each of which constitutes a part of a word line. Further, by ion implantation using the gate electrodes 6A and 6B as a mask, an n-type impurity such as phosphorus is introduced into the surface layer of the silicon substrate 1 on both sides of the gate electrodes 6A and 6B, and the first and second source / drain extensions 8A, 8B is formed.

At the same time, in the p well 4 in the peripheral circuit region B, p-type impurities are introduced into the silicon substrate 1 on both sides of the gate electrode 6C to form source / drain extensions 9. The n-type impurity and the p-type impurity are separated using a resist pattern.

Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 including the gate electrodes 6A to 6C,
The insulating film is etched back to form the insulating sidewall 10 while leaving only the both side portions of the gate electrodes 6A to 6C. For the insulating film, for example, a silicon oxide film formed by a CVD method is used.

Subsequently, n-type impurities such as arsenic are ion-implanted again into the surface layer of the silicon substrate 1 using the insulating sidewall 10 and the gate electrodes 6A and 6B as a mask, and the silicon substrate 1 beside the gate electrodes 6A and 6B is implanted. First and second source / drain regions 11A and 11B are formed.

Similarly, in the peripheral circuit region B, first and second source / drain regions 13A and 13B are formed in the silicon substrate 1 on the side of the gate electrode 6C by ion implantation.

Further, a metal film is formed on the entire upper surface of the silicon substrate 1 including the gate electrodes 6A to 6C by sputtering. The metal film is preferably a high melting point metal such as a cobalt film, but may be a metal having a relatively low melting point. Then, the metal film is heated to react with silicon, whereby the upper surfaces of the gate electrodes 6A to 6C and the first and second source / drain regions 11A, 1
A metal silicide layer 12 such as a cobalt silicide layer is formed on the silicon substrate 1 in 1B, 13A, and 13B. By this heat treatment, each source / drain region 11A
, 11B, 13A, 13B are activated to reduce the resistance.

Thereafter, the unreacted refractory metal film on the element isolation insulating film 2 and the like is removed by wet etching.

Up to this step, the gate insulating film 5 and the gate electrodes 6A, 6 are formed in the active region of the silicon substrate 1.
B, MOS transistors T1 and T2 constituted by the first and second source / drain regions 11A and 11B are formed. A transistor T3 is also formed in the peripheral circuit region B.

Next, the oxidation-preventing insulating film 15 is formed on the entire upper surface of the silicon substrate 1 including the gate electrodes 6A to 6C.
As a (cover film), a silicon oxynitride (SiON) film with a thickness of about 200 nm is formed by plasma CVD.
To form. Further, a silicon oxide (SiO ₂ ) film having a thickness of about 1000 nm is formed as the first interlayer insulating film 16 on the antioxidant insulating film 15 by plasma CVD using TEOS (tetra ethoxy silane) gas. Note that a SiO 2 film formed by plasma CVD using TEOS is hereinafter referred to as a TEOS film.

Then, the surface of the first interlayer insulating film 16 is polished and planarized by a CMP (Chemical Mechanical Polishing) method, and the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 16 is increased. It is adjusted to a predetermined value, for example, about 785 nm.

  Next, steps required until a sectional structure shown in FIG.

First, the antioxidant insulating film 15 and the first interlayer insulating film 16 are patterned by photolithography to form first contact holes 17A, 17B, and 17C. The depth of the first contact holes 17A to 17C is set to reach the refractory metal silicide layer 11 of each of the first source / drain regions 10A to 10D, and the diameter thereof is, for example, 0.25 μm.

Then, the first source / drain region 11 is formed using the first contact holes 17A to 17C.
Conductive plugs 18A to 18E electrically connected to A, 11B, 13A, and 13B are formed. Specifically, a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are sequentially formed on the inner surfaces of the first contact holes 17A to 17C by a sputtering method or the like, and has a two-layer stacked structure. A film (glue film) 19A is produced. Further, tungsten (
W) The film 19B is grown by the CVD method. This film thickness is set to, for example, 300 nm on the first interlayer insulating film 16, and the W film 19B fills the gaps of the first contact holes 17A to 17C.
Excess W film 19B grown on the upper surface of first interlayer insulating film 16 is removed by CMP. As a result, conductive plugs 18A to 18C are formed in the contact holes 17A to 17C, respectively.

The first contact holes 17D and 17E are similarly formed in the peripheral circuit region B,
Conductive plugs 18D and 18E are formed respectively.

Next, in order to prevent the conductive plugs 18A to 18E from being oxidized during the thermal annealing in the subsequent process,
A second interlayer insulating film 20 is formed on the first interlayer insulating film 16 and the conductive plugs 18A to 18E. The second interlayer insulating film 20 has a configuration in which, for example, a SiON film is formed to a thickness of about 100 nm, and a TEOS film is deposited to a thickness of about 130 nm. After the second interlayer insulating film 20 is formed, the second interlayer insulating film 20 is degassed by annealing in a nitrogen atmosphere at a temperature of about 650 ° C. for about 30 minutes.

  Next, steps required until a sectional structure shown in FIG.

First, on the second interlayer insulating film 20, an aluminum oxide (Al
_{A 2} O ₃ ) film is formed by sputtering to a thickness of about 20 nm. Then, rapid heat treatment (RT
According to A), the lower electrode adhesion film 21 is oxidized in an oxygen atmosphere at 650 ° C.

Next, a first conductive film 22 (lower conductive film) to be a lower electrode is formed on the lower electrode adhesion film 21. For example, a platinum film formed by a sputtering method is used for the first conductive film 22, and the thickness thereof is about 150 nm. The first conductive film 22 may be a single-layer film of any one of an iridium film, a ruthenium film, a ruthenium oxide (RuO ₂ ) film, and a SrRuO ₃ film, or a laminated film thereof, instead of the platinum film. Since the lower electrode adhesion film 21 is formed before the first conductive film 22 is formed, the adhesion between the first conductive film 22 and the second interlayer insulating film 20 is enhanced.

Next, a first ferroelectric film 23 is formed on the first conductive film 22. As the first ferroelectric film 23, for example, a PZT (Pb (Zr _x , Ti _1-x ) O ₃ (0 ≦ x ≦ 1)) film is used, and an RF (Radio Frequency) sputtering method using a PZT target is used. A thickness of about 90 nm is formed.

The first ferroelectric film 23 is not limited to PZT. PZT with Ca, Sr, La, Nb
, Ta, Ir, or W may be used to form the first ferroelectric film 23.
Further, (Bi _1-x Rx) Ti ₃ O ₁₂ (R is a rare earth element, 0 <x <1), SrBi ₂
The first ferroelectric film 23 may be formed from a Bi layered compound such as Ta ₂ O ₉ (SBT) or SrBi ₄ Ti ₄ O ₁₅ . Further, the film formation method of the first ferroelectric film 23 is not limited to the sputtering method, but a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD (Metal Organic C).
VD) method may be adopted.

By the way, it is known that when the first ferroelectric film 23 is formed by the sputtering method, the film quality becomes amorphous, and the ferroelectric characteristics are inferior to those of crystalline. Therefore, crystallization annealing is performed after film formation to crystallize the first ferroelectric film 23.

The crystallization annealing is performed by RTA (Rapid Thermal Anneal) in an oxygen-containing atmosphere, for example, an oxygen + argon atmosphere adjusted so that the oxygen concentration becomes 1.25 flow%. The substrate temperature is 600 ° C., for example, and the processing time is 90 seconds. Thus, the first ferroelectric film 23
Is crystallized to form a large number of PZT crystal grains in the film. When the MOCVD method is employed, the first ferroelectric film 23 is crystallized at the time of film formation, so that crystallization annealing is not necessary.

Next, an amorphous PZT film is formed on the first ferroelectric film 23 as the second ferroelectric film 24 by RF.
For example, a thickness of 10 nm to 30 nm is formed by sputtering. The second ferroelectric film 24 is made of P.
The second ferroelectric film 24 may be formed from a material obtained by adding any of Ca, Sr, La, Nb, Ta, Ir, and W to PZT. Furthermore, (Bi _1-x Rx) Ti
₃ O ₁₂ (R is a rare earth element 0 <x <1), SrBi ₂ Ta ₂ O ₉ (SBT), SrB
The second ferroelectric film 24 may be formed of a Bi layered compound such as i ₄ Ti ₄ O ₁₅ . Note that the second ferroelectric film 24 is preferably formed of the same material as the first ferroelectric film 23.

Next, a first iridium oxide film 25A is formed as a second conductive film 25 (upper conductive film) on the second ferroelectric film 24 by sputtering, for example, to a thickness of about 50 nm. Thereafter, crystallization annealing is performed on the second ferroelectric film 24 in an oxygen-containing atmosphere to perform amorphous second
The ferroelectric film 24 is crystallized, and the crystallinity of the first ferroelectric film 23 under the second ferroelectric film 24 is further enhanced. The annealing conditions are, for example, a substrate temperature of 710 ° C. and a processing time of 12
0 seconds. As the oxygen-containing atmosphere for annealing, a mixed atmosphere of oxygen gas and argon gas whose oxygen concentration is adjusted to 1 flow% is used.

By crystallizing the second ferroelectric film 24 after forming the first iridium oxide film 25 </ b> A, it is possible to prevent iridium oxide constituting the film from entering the crystal grain boundary of the second ferroelectric film 24. As a result, the formation of a leak path in the second ferroelectric film 24 due to iridium oxide can be suppressed. This annealing also has an advantage that oxygen is supplied to the second ferroelectric film 24 through the first iridium oxide film 25A and oxygen deficiency in the second ferroelectric film 24 is compensated.

In order to obtain such advantages, the thickness of the first iridium oxide film 25A is thin so that oxygen can easily pass through, and is preferably 10 nm to 100 nm, for example. However, if the thin second conductive film 25 is formed on the second ferroelectric film 24 in this way, damage that cannot be absorbed by the second conductive film 25 in the subsequent etching process or the like will be reduced to the first and second strong films. Dielectric films 23, 2
4 may be affected.

Therefore, as a conductive protective film for protecting the first and second ferroelectric films 23 and 24 in the next step, the second iridium oxide film 25B is formed on the first iridium oxide film 25A by sputtering. Form about 200 nm. The second conductive film 25 is formed by the second iridium oxide film 25B and the first iridium oxide film 25A.

After the back surface of the silicon substrate 1 is cleaned, a first protective film 27 that functions as a diffusion preventing film for preventing permeation of a reducing substance such as hydrogen or water is formed on the second iridium oxide film 25B. As the first protective film 27, for example, a TiN film is used, and 30 to 100 nm is formed by sputtering.
The film thickness is formed. The TiN film has a substrate temperature of 200 ° C., Ar of 50 sccm and N ₂ of 9
Film formation is performed using a Ti target in a mixed gas atmosphere of 0 sccm.

The first protective film 27 is also used as a hard mask (first mask) when the second conductive film 25 is etched to form the upper electrode. In this embodiment, the thickness of the TIN film is 50 nm.
It was. The first protective film 27 is not limited to the TiN film, and Ti, TiN, Ta, TaN,
TiAl, TaAl, TiAlN, TaAlN, TiSiN, TaSiN, TiSi, T
You may form from either of aSi.

Next, after applying a resist to the entire surface of the first protective film 27, exposure and development are performed. Thereby, as shown in FIG. 1D, the photoresist film 38 as the second mask is patterned into a predetermined planar shape, that is, a planar shape of the upper electrode of the ferroelectric capacitor. Then, the second conductive film 25 and the first protective film 27 are etched using the pattern of the photoresist film 38. At this time, the first protective film 27 also functions as a hard mask (first hard mask), and the second conductive film 25 and the first protective film 27 are reliably etched. Note that etching may be performed by forming a second hard mask instead of the photoresist film 38.

As a result, the upper electrode 28 made of the second conductive film 25 is formed as shown in FIG. 1E.
After the etching, the photoresist film 38 is removed. On the other hand, the first protective film 27 used as a hard mask is left without being removed.

Since the side portion of the first protective layer 27 which also functions as a hard mask is etched to some extent, the cross-sectional area parallel to the stacking direction of the upper area is smaller than the cross-sectional area of the lower area. That is, the first protective film 27 has an upper surface area narrower than the lower surface.

Further, heat-treated silicon substrate 1 on which the photoresist film 38 is removed in an oxygen containing atmosphere. The temperature of the heat treatment is 600 to 700 ° C. In this embodiment, as an example, heat treatment is performed at 650 ° C. for 40 minutes. This heat treatment recovers damage received by the ferroelectric films 23 and 24 during the process, and such annealing is also called recovery annealing.

At this time, the first protective film 27 is also oxidized from the surface and side surfaces, and TiN in the surface layer (upper region and side region) of the first protective film 27 is almost oxidized. The degree of oxidation of TiN gradually decreases in the film thickness direction and in the substrate direction. On the other hand, the oxygen in the second iridium oxide film 25A is directly above the first.
It diffuses into TiN in the lower region of the protective film 27. That is, the first protective film 27 is oxidized from each of the vertical direction and the lateral direction, and oxygen diffuses to the center of the film. Thereby, the oxidation degree of each of the upper region, the lower region, and the side region of the oxidized TiN film becomes higher than the center.

That is, as shown in an enlarged cross-sectional view in FIG. 2A, the first protective film 27 includes an upper region 27A and a lower region 27B having a high oxygen content, and an upper region 27A and a lower region 27B in the stacking direction.
Between the two regions 27A and 27B, the film central region 2 having a relatively lower oxygen concentration than the two regions 27A and 27B.
7C is formed. That is, the first protective film 27 has a portion where the oxygen concentration is different in the film thickness direction (stacking direction). For example, as shown in FIG. 2B, the oxygen concentration profile in the film thickness direction is highest on the upper side, then higher on the lower side, and lowest in the central portion.

Note that the side region, which is the outer peripheral surface region of the first protective film 27, is formed integrally with the upper region 27A and has substantially the same oxygen concentration. That is, in the first protective film 27, the oxygen concentration in the film center region 27C is lower than the oxygen concentration in each of the upper region 27A, the lower region 27B, and the side region 27D. For example, when the thickness of the first protective film 27 is about 50 nm, the thickness of the upper region 27A is about 30 nm, the width of the side region 27D is about 30 nm, and the thickness of the lower region 27B is 5 to 10 n.
m. In particular, by making the upper region 27A thickest, it becomes possible to efficiently prevent the permeation of the reducing substance.

Here, the oxidation degree of TiN constituting the first protective film 27 can be adjusted by the oxygen content in the heat treatment atmosphere. Further, when the surface of the first protective film 27 is a noble metal film, the oxidation degree when the first protective film 27 is oxidized from the surface side, that is, the composition ratio of oxygen gradually increases from the upper region 27A toward the lower region 27B. It becomes low. Therefore, by this heat treatment, the first protective film 27 has a layer structure of TiO _x , TiOON, TiO _y (x> y) in order from the bottom (or in order from the top), or TiO _x ,
It has a layer structure of TiO _y and TiON (x> y) or a layer structure of TiO _x , TiON and TiO _x . In general, it is known that TiO is less permeable to moisture and hydrogen than TiN. By adopting such a configuration, it is possible to reliably prevent the transmission of moisture and the like, and the ferroelectric film. Reduction of 23 and 24 is prevented.

The first protective film 27 after the oxidation treatment is not limited to TiO or TiON, but TaN, TaO
_{x, TaON, TiAlO x, TaAlO} x, TiAlON, TaAlON, TiSiO
N, TaSiON, TiSiO _x , TaSiO _x , AlO _x , ZrO _{x and the} like may be used.

  Next, steps required until a sectional structure shown in FIG.

First, a photoresist film (not shown) is formed on the entire surface of the first protective film 27 and the second ferroelectric film 24 by, for example, a spin coat method, and the photoresist film is formed by a photolithography method. Patterned into a planar shape. Subsequently, the ferroelectric films 23 and 24 are etched using the patterned photoresist mask. after that,
The photoresist film is removed. Next, heat treatment is performed in an oxygen atmosphere at, for example, 300 ° C. to 400 ° C. for 30 minutes to 120 minutes. The ferroelectric films 23 and 24 have a rectangular planar shape that passes under the plurality of upper electrodes 28.

Thereafter, the first protective film 27, the upper electrode 28, the ferroelectric films 23 and 24, and the first conductive film 22 are formed.
A second protective film 30 is formed thereon by, for example, sputtering, CVD, or ALD. As the second protective film 30, for example, an aluminum oxide film having a thickness of 20 nm to 50 nm is used. After the formation of the second protective film 30, heat treatment is performed in an oxygen atmosphere. The heat treatment conditions are, for example, 400 ° C. to 600 ° C. and 30 minutes to 120 minutes.

The second protective film 30 is a diffusion preventing film that prevents hydrogen or water from diffusing into the ferroelectric capacitor 31, although the constituent material is different from that of the first protective film 27. In addition, the second protective film 30 is not limited to the aluminum oxide film, but may be TiO _x , TaO _x , AlO _x.
, ZrO _x , HfO _x , NbO _x , VO _x , ZnO _x film, or a film formed from a material selected from the group consisting of PZT.

  Further, steps required until a sectional structure shown in FIG.

A photoresist film is formed on the entire surface of the second protective film 30 by, eg, spin coating.
The photoresist film is patterned into a predetermined planar shape, that is, the planar shape of the lower electrode of the ferroelectric capacitor by photolithography. Subsequently, the second is performed using the photoresist film as a mask.
The protective film 30, the first conductive film 22, and the lower electrode adhesion film 21 are etched to form the lower electrode 29 made of the first conductive film 22. The planar shape of the lower electrode 29 is a substantially rectangular shape including a plurality of upper electrodes 28, and the end portions thereof are sized to protrude from the dielectric films 23 and 24.

The upper electrode 28, the ferroelectric films 23 and 24, and the lower electrode 29 thus patterned constitute a ferroelectric capacitor 31.

The second protective film 30 remains so as to cover the second conductive film 25 that is the upper electrode film and the ferroelectric films 23 and 24. When the etching is completed, the remaining photoresist film (not shown) is removed. Next, for example, heat treatment is performed for 30 minutes to 120 minutes in an oxygen atmosphere of 300 ° C. to 400 ° C.

A third protective film 32 is formed on the upper surfaces of the ferroelectric capacitor 31 and the second interlayer insulating film 20 by, for example, sputtering, CVD, or ALD. The third protective film 32 is made of, for example, an aluminum oxide film having a thickness of 20 nm.

After the third protective film 32 is formed, heat treatment is performed for 30 minutes to 120 minutes in an oxygen atmosphere of 500 ° C. to 700 ° C., for example. As a result, oxygen is supplied to the ferroelectric films 23 and 24, and the electrical characteristics of the ferroelectric capacitor 31 are restored .
Next, steps required until a sectional structure shown in FIG.

As a third interlayer insulating film 33, a silicon oxide film having a thickness of 1400 nm is formed on the entire surface of the third protective film 32 by, for example, a plasma CVD method using TEOS. After this, for example, CMP
The surface of the third interlayer insulating film 33 is planarized by the method.

Next, in a plasma atmosphere generated using N ₂ O gas or N ₂ gas, for example, 35
Heat treatment is performed at 0 ° C. for 2 minutes. As a result of the heat treatment, moisture in the third interlayer insulating film 33 is removed, and the film quality of the third interlayer insulating film 33 changes to make it difficult for moisture to enter the film. By this heat treatment, the surface of the third interlayer insulating film 33 is nitrided to form a SiON film.

Further, a fourth protective film 34 is formed on the entire surface of the third interlayer insulating film 33. The fourth protective film 34 is made of, for example, an aluminum oxide film having a thickness of 20 nm to 50 nm formed by sputtering or CVD. Further, a silicon oxide having a thickness of, for example, 300 nm is formed as a fourth interlayer insulating film 35 on the entire surface of the fourth protective film 34 by a plasma CVD method using TEOS.

  Next, steps required until a sectional structure shown in FIG.

First, a photoresist film (not shown) is formed on the upper surface of the fourth interlayer insulating film 35, and etching is performed using the photoresist film as a mask, so that a fourth protective film 34, a third interlayer insulating film 33, a third protective film are formed. A second contact hole 41 that reaches the upper electrode 28 of the ferroelectric capacitor 31 through 32 is formed.

In this embodiment, since the first protective film 27 does not have conductivity, the second contact hole 4
Reference numeral 1 denotes a depth reaching the upper electrode 28 through the first protective film 27. However, the first
When the protective film 27 is formed of a conductive material and can be electrically connected to the upper electrode 28 through the first protective film 27, the second contact hole 41 has a depth reaching the first protective film 27. Just do it.

Similarly, etching is performed using a photoresist film formed on the fourth interlayer insulating film 35 to form a second contact hole 42 reaching the lower electrode 29 of the ferroelectric capacitor 31.

Next, for example, heat treatment is performed for 30 minutes to 120 minutes in an oxygen atmosphere of 400 ° C. to 600 ° C. As a result, oxygen is supplied to the ferroelectric films 23 and 24, and the electrical characteristics of the ferroelectric capacitor 31 are restored. Note that this heat treatment may be performed not in an oxygen atmosphere but in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, the electric characteristics of the ferroelectric capacitor 31 are restored by supplying oxygen to the ferroelectric films 23 and 24.

Next, via holes 43A to 43 that penetrate through the third and fourth interlayer insulating films 33 and 34, the third protective film 32, and the first and second interlayer insulating films 16 and 20 and reach the conductive plugs 18A to 18E.
E is formed by photolithography and etching.

  Next, steps required until a sectional structure shown in FIG.

For example, a Ti film having a thickness of 20 nm and a T film having a thickness of 50 nm are formed in the second contact hole 41.
The iN film and the iN film are sequentially formed by, for example, sputtering. An adhesion film 44A is formed in the second contact hole 41 by these Ti film and TiN film. Further, W on the adhesion film 44A.
The film 44B is grown by the CVD method, and the gaps between the second contact holes 41 and 42 and the via holes 43A to 43E are filled with the W film 44B to form conductive plugs 45A to 44G. Excess adhesive film 44A and W film 44B formed on fourth interlayer insulating film 35 are removed by CMP. As a result, the conductive plugs 45C to 45G become conductive plugs 18A to 18E below the conductive plugs 45C to 45G.
Are electrically connected to the source / drain regions 11A, 11B, 13A, 13B.

Next, plasma cleaning is performed to remove the natural oxide film and the like on the surfaces of the conductive plugs 45A to 45G. For the plasma cleaning, for example, argon gas is used.

Then, a conductor film 46 is formed on the upper surfaces of the conductive plug 45 and the fourth interlayer insulating film 34.
For example, the conductor film 46 is formed by sequentially stacking a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm. The

As shown in FIG. 1K, the conductor film 46 is patterned by photolithography and dry etching to form a first metal wiring layer. Thereby, the wiring 47A electrically connected to the upper electrode 28 via the conductor plug 45A, and the wiring 47B electrically connected to the lower electrode 29 via the conductor plug 45B and the conductor plugs 18A to 18E. , 45C ~ 4
A wiring 47C electrically connected to the source / drain regions 11A, 11B, 13A, 13B through 5G is formed.

Although illustration is omitted, if three-layer wiring or five-layer wiring is performed by a film formation method or patterning method substantially the same as the formation of the first metal wiring layer, the semiconductor device according to this embodiment will be described. The basic structure is completed.

As described above, in the first protective film 27 in this embodiment, the oxygen concentration in the upper region 27A and the lower region 27B is higher than that in the film center region 27C by the recovery annealing of the ferroelectric capacitor 31. It has a structure. The first protective film 27 serves as a metal mask for patterning the upper electrode 28 and has a function of preventing the reduction element from permeating. That is, after patterning the ferroelectric capacitor 31, is left on the upper electrode 28 without being removed, which functions as a reducing element barrier film for preventing the reduction element is transmitted to the ferroelectric capacitor 31. Since the first protective film 27 when patterning the upper electrode 28 is in the state of a metal film before oxidation, the etching rate is higher than that of the oxide film, and the time required for the etching process can be shortened.

Conventionally, an upper electrode is formed using a hard mask, and the hard mask formed on the upper electrode is removed after patterning. There are two methods of removing the hard mask: wet and dry etching. When the wet method is removed, film peeling tends to occur around the silicon substrate and the bevel, and the peeled film is reattached to the silicon substrate. As a result, contact failure was caused.

On the other hand, in the dry etching method, the hard mask can be removed well, but at the same time as the dry etching, minute foreign matters (0.2 μm or less) are left on the surface of the upper electrode. When the second protective film 30 is formed with the minute foreign matter remaining on the upper electrode 28, the second protective film 30 and the upper electrode 29 in which the minute foreign matter is interposed, as illustrated in a portion surrounded by a broken line in FIG. The adhesion of the film deteriorated or the film had defects. Thereby, when forming the conductive plug 45A, tungsten, fluorine, and hydrogen constituting the reactive gas containing WF ₆ enter the capacitor through the defect of the second protective film 30, and the ferroelectric films 23 and 24 are formed. May deteriorate.

In this embodiment, it is not necessary to remove the first protective film 27 after the patterning of the ferroelectric capacitor 31, so that no minute foreign matter is generated as in the prior art. Therefore,
Film peeling and deterioration of the ferroelectric film can be prevented, and a high-quality semiconductor device can be obtained. In addition, the first
Since the removal process of the protective film 27 becomes unnecessary, the process can be simplified and the working efficiency can be improved.

  Here, a modified example of this embodiment will be described.

As shown in FIG. 3 (a), first protective layer 27, the intermediate region from the upper side of the upper region 27A in the film thickness direction, gradually oxygen concentration in the order of the lower region 27 B may be configured to decrease. That is, as an example of an oxygen concentration profile in the thickness direction in FIG. 3 (b), the upper area 27 A toward the lower region 27B oxygen concentration similar effect even gradual as to decrease construction Is obtained. In this case as well, the oxygen concentration in the side portions is increased by oxidation.

As shown in FIG. 4A, the second protective film 30 may have a two-layer structure in which the first layer 30A and the second layer 30B are sequentially stacked. As a material constituting the second protective film 30, for example, TiO _x ,
Examples include TaO _x , AlO _x , ZrO _x , HfO _x , NbO _x , VO _x , ZnO _x , and PZT. The first layer 30A and the second layer 30B may be composed of the same component or different components. In any case, it functions as a diffusion preventing film for preventing hydrogen and water from diffusing into the ferroelectric capacitor 31. And since it has a two-layer laminated structure, diffusion of hydrogen or the like can be prevented more reliably. Further, by making the first layer 30A thinner than the second layer 30B, if recovery annealing is performed after the first layer 30A is formed, oxygen addition to the ferroelectric films 23 and 24 is facilitated.

As shown in FIG. 4B, the first protective film 51 has a two-layer structure in the stacking direction, and includes a lower protective film 51A serving as a lower region in contact with the upper electrode 28 and an upper protective film 51B serving as an upper region. . The upper protective film 51B has a substantially uniform oxygen content and is higher than the lower protective film 51A. Lower protective film 5
In 1A, the distribution of oxygen content in the film differs in the stacking direction, and more specifically, the oxygen content gradually decreases from the upper part to the lower part. Even with such a first protective film 51, the same effect as described above can be obtained. The upper protective film 51B is formed as a metal oxide film during film formation. The oxygen concentration of the side portion of the lower protective film 51A can also be increased by oxidation. Further, the first protective film 51 is set to 1
The lower protective film 51A and the upper protective film 51B may be formed by forming a layer structure and oxidizing by heat treatment after film formation.

Further, as shown in FIG. 5, a first protective film 52 having a function of preventing permeation of the reducing substance has a three-layer structure on the upper electrode 28. Specifically, the first protective film 52 includes a lower protective film 52A, an intermediate protective film 52B, and an upper protective film 52C that are sequentially stacked in the stacking direction. The lower protective film 52A corresponds to the lower region, and the intermediate protective film 52B corresponds to the film central region. The upper protective film 52C corresponds to the upper region. Further, the second protective film 53 is replaced with the first protective film 5.
2 and the side surface of the ferroelectric capacitor 31 including the upper electrode 27 is provided.

The lower protective film 52A and the upper protective film 52C are made of the same material as the first protective film 27, for example, Ti.
O _{x and, TiON, TaO x, TaON,} TiAlO x, TaAlO x, TiAlON,
TaAlON, TiSiON, TaSiON, TiSiO _x , TaSiO _x , AlO _x ,
It is made of ZrO _x or the like. The protective film 52A and the upper protective film 52C may be made of the same material. The intermediate protective film 52B is, for example, TiON, TaON, TiAlON, TaA.
1ON, TiSiON, TaSiON or the like. The intermediate protective film 52B has a lower oxygen content than the lower protective film 52A immediately below it and the upper protective film 52C directly above it. When the first protective film 52 is formed, the lower protective film 52A, the intermediate protective film 52B, and the upper protective film 52C are formed in this order. The reason why the amount of oxygen in the intermediate protective film 52B is relatively small is that as the amount of oxygen decreases, the etching rate during patterning can be increased.

By adopting a laminated structure of protective film products having different film qualities as described above, resistance to hydrogen is further improved. The first protective film 52 having a laminated structure may be four or more layers. Even in such a case, it is preferable that the oxygen content of the intermediate protective film is lower than the protective film in the lower region and the protective film in the upper region.
(Second Embodiment)
A second embodiment of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component as 1st Embodiment, and the overlapping description is abbreviate | omitted.

The semiconductor device according to the present embodiment is a semiconductor memory device (ferroelectric memory) having a stack structure.

  The steps required until a sectional structure shown in FIG. 7A is obtained will be described.

First, the active regions in the memory region A, that is, the p-wells 3 are partitioned on the surface of the silicon substrate 1 by the element isolation insulating film 2 to form transistors T1 and T2. Further, conductive plugs 18A to 18C using contact holes 17A to 17E are formed in the first interlayer insulating film 16 corresponding to the positions of the source / drain regions 11A and 11B. The details of the steps so far are the same as those in the first embodiment.

Next, the first antioxidant film 6 is formed on the entire surface of the first interlayer insulating film 16 including the conductive plugs 18 to 18C.
First, a SiON film is formed to a thickness of 130 nm by, for example, a plasma CVD method. Furthermore, a silicon oxide film is formed on the first antioxidant film 61 as a second interlayer insulating film 62, for example, T
It is formed with a film thickness of 300 nm by plasma CVD using EOS as a raw material. Si
A SiN film or an AlO film may be formed instead of the ON film.

A resist pattern is formed on the second interlayer insulating film 62. The resist pattern is p-well 3
Openings are formed on the conductive plugs 18A and 18C near both sides. Then, using the resist pattern as a mask, the second interlayer insulating film 62 and the first antioxidant film 61 are dry-etched to form via holes 63 reaching the second source / drain regions 11A and 11B. Conductive plugs 64 </ b> A and 64 </ b> B are embedded in the via hole 63. Conductive plugs 64A, 6
4B is formed of an adhesion layer 65A and a W layer 65B manufactured by the same process as in the first embodiment.

The excess adhesion layer 65A and W layer 65B formed on the second interlayer insulating film 62 are removed by polishing by the CMP method. In the CMP method, it is possible to use a slurry in which the polishing rate of the adhesion layer 65A and the W layer 65B to be polished is faster than that of the underlying first insulating film, for example, SSW2000 manufactured by Cabot Microelectronics. In order not to leave a polishing residue on the first interlayer insulating film 16, the polishing amount of this CMP is determined by the adhesion layer 65A and the W layer 65B.
It is set to be thicker than the total film thickness. That is, the CMP polishing here is over polishing.

As a result, the upper surface height of the conductive plugs 64A and 64B is lower than the upper surface of the second interlayer insulating film 62, and a recess is generated. The depth of the recess is 20 to 50 nm, typically about 50 nm.

In order to eliminate this recess, the surface of the second interlayer insulating film 62 is treated with NH ₃ plasma to bond NH groups to oxygen atoms on the surface. Thus, the second interlayer insulating film 62
Even if Ti atoms are further deposited thereon, Ti atoms are not trapped by oxygen atoms,
The surface of the second interlayer insulating film 62 can be freely moved. Thus, the flatness of the upper surface of the Ti film self-organized in the (002) orientation on the second interlayer insulating film 62 is improved.

The ammonia plasma treatment is about 9 mm (350 m) with respect to the silicon substrate 1, for example.
Ils) This is carried out using a parallel plate type plasma processing apparatus having a counter electrode at a spaced position. The processing conditions are, for example, that ammonia gas is supplied at a flow rate of 350 sccm into a processing vessel held at a substrate temperature of 400 ° C. under a pressure of 266 Pa (2 Torr), and the silicon substrate 1
This is carried out by supplying a high frequency of 13.56 MHz to the side with a power of 100 W and a high frequency of 350 kHz to the counter electrode with a power of 55 W for 60 seconds.

  Next, steps required until a sectional structure shown in FIG.

For example, a sputtering DC power of 2.6 kW is supplied for 35 seconds at a substrate temperature of 20 ° C. in an Ar atmosphere of 0.15 Pa in a sputtering apparatus in which the distance between the silicon substrate 1 and the target is set to 60 mm. As a result, a strong (002) -oriented Ti film is formed to a thickness of about 100 nm.

Further, RTA was performed for 60 seconds at a substrate temperature of 650 ° C. in a nitrogen atmosphere, and (111
) A base conductive film 70 made of an oriented TiN film is formed. The thickness of the underlying conductive film 70 is 10
It is 0 nm to 300 nm, more preferably about 100 nm. The base conductive film 70 is not limited to the titanium nitride film, and any one of a tungsten film, a silicon film, and a copper film is used as the base conductive film 70.
You may form as. However, in order to improve crystallinity, it is preferable that the underlying conductive film 70 is a TiN film produced by treating the Ti film with ammonia plasma.

A recess is formed on the upper surface of the underlying conductive film 70 due to the influence of the recess of the conductive plugs 64A and 64B. Therefore, the recess is removed by polishing and planarizing the upper surface of the underlying conductive film 70 by CMP. . The slurry used in CMP is not particularly limited. For example, SSW2000 manufactured by Cabot Microelectronics can be used. By the way, the thickness of the underlying conductive film 70 after CMP varies within the surface of the silicon substrate 1 or between the plurality of silicon substrates 1 due to polishing errors. If polishing time is controlled in consideration of such variations, CM
The target value of the thickness of the underlying conductive film 70 after P is 50 nm to 100 nm, more preferably 50 nm.
To.

By the way, after the CMP is performed on the base conductive film 70, the crystals near the upper surface of the base conductive film 70 are distorted by polishing. When the lower electrode of the capacitor is formed above the underlying conductive film 70 having a crystal distortion as described above, the distortion affects the lower electrode and the crystallinity of the lower electrode is deteriorated. The ferroelectric characteristics of the dielectric film may be deteriorated.

In order to avoid such an inconvenience, the upper surface of the underlying conductive film 70 is exposed to the NH ₃ plasma described above, so that the distortion of the crystal of the underlying conductive film 70 is eliminated and the films deposited thereafter are not affected. Like that.

Then, a Ti film having a thickness of about 20 nm is formed as a crystalline conductive adhesive film 71 on the underlying conductive film 70 which has been subjected to NH ₃ plasma treatment to eliminate crystal distortion, by sputtering. After the crystalline conductive adhesion film 71 is formed, RTA is performed in a nitrogen atmosphere at 650 ° C. for 60 seconds to form a (111) -oriented TiN film. The crystalline conductive adhesion film 71 has a function as an adhesion film in addition to the function of increasing the orientation of a film deposited later on the crystalline conductive adhesion film 71 by the action of its own orientation.

The crystalline conductive adhesive film 71 is not limited to TiN. For example, a thin (preferably 20 nm) noble metal Ir or Pt may be used.

Next, a TiAlN film is formed on the crystalline conductive adhesion film 71 as the conductive oxygen barrier film 72A.

The conductive oxygen barrier film 72A is formed to a thickness of 100 nm by reactive sputtering using a target obtained by alloying Ti and Al. The film forming conditions are, for example, a pressure of 253.3 Pa, 4 in a mixed atmosphere in which Ar is supplied at a flow rate of 40 SCCM and nitrogen is 10 SCCM.
A substrate temperature of 00 ° C. and a sputtering power of 1.0 kW are set.

Further, the lower electrode film 72B on the conductive oxygen barrier film 72A and the Ir film in an Ar atmosphere,
100 nm at a substrate temperature of 500 ° C. and a sputtering power of 0.5 kW under a pressure of 0.11 Pa.
The thickness is formed.

The lower electrode film 72B is made of a platinum group metal such as Pt, or Pt instead of the Ir film.
Conductive oxides such as O, IrO _x , and SrRuO ₃ can also be used. Furthermore, a laminated film of these metals or metal oxides may be used.

Next, a PZT film is formed as the first ferroelectric film 74 by the MOCVD method. More specifically, Pb (DPM) ₂ , Zr (dmhd) ₄ and Ti (O—iOr) ₂ (DPM) ₂
Are dissolved in a THF solvent at a concentration of 0.3 mol / l to form Pb, Zr and Ti liquid raw materials. Furthermore, these liquid raw materials are supplied to the vaporizer of the MOCVD apparatus together with THF solvent at a flow rate of 0.474 ml / min, respectively 0.326 ml / min and 0.200 ml.
At a flow rate of 0.200 ml / min.

By vaporizing such a liquid, raw material gases of Pb, Zr and Ti are formed. Further, in a MOCVD apparatus, P is applied at a substrate temperature of 620 ° C. under a pressure of 665 Pa (5 Torr).
b, Zr and Ti source gases are supplied to the MOCVD apparatus for 620 seconds. As a result, the second
A desired PZT film is formed to a thickness of, for example, 100 nm on the lower electrode film 72B.

  Next, steps required until a sectional structure shown in FIG.

First, an amorphous second ferroelectric film 75 is formed on the entire surface of the first ferroelectric film 74 by, for example, sputtering. The second ferroelectric film 75 has a film thickness of, for example, 1 nm to 30 nm (more preferably 20 nm). In the case of forming a film by MOCVD, as an organic source for supplying lead (Pb), Pb (DPM) ₂ (Pb (C ₁₁ H ₁₉ O ₂ ) ₂ ) is THF (tetrahydrofu).
ran: C ₄ H ₈ O) A material dissolved in a liquid is used. As an organic source for supplying zirconium (Zr), a material in which Zr (DMHD) ₄ (Zr ((C ₉ H ₁₅ O ₂ ) ₄ ) is dissolved in a THF solution is used. As an organic source, Ti (O-i
A material in which Pr) ₂ (DPM) ₂ (Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is dissolved in a THF solution is used.

Next, a first upper electrode film 76 </ b> A is formed on the second ferroelectric film 75. First upper electrode film 7
In forming 6A, first, an IrO _x film having a thickness of 50 nm and crystallized at the time of film formation is formed on the second ferroelectric film 75 by sputtering. For example, the film formation temperature at this time is 3
00 ° C., Ar and O ₂ were used as film forming gases, and these flow rates were both 100 scc.
m. Further, the sputtering power is, for example, about 1 kW to 2 kW.

Next, heat treatment is performed for 60 seconds in an atmosphere supplied with 725 ° C., 20 sccm of oxygen and 2000 sccm of Ar by the RTA method. By this heat treatment, the second ferroelectric film 75 is completely crystallized, and the plasma damage of the first upper electrode film 76A is recovered, so that the first ferroelectric film 7
4 is compensated for oxygen deficiency.

Further, as the second upper electrode film 76B having a film thickness of 100 nm to 300 nm, an IrO _Y film is formed to 200 nm, for example. For example, the IrO _Y film is deposited in an Ar atmosphere and under a pressure of 0.8 Pa with a sputtering power of 1.0 kW for 79 seconds.

At this time, if the iridium oxide film is made to have a composition close to the stoichiometric composition of IrO _{2 in} order to suppress the process deterioration, the second ferroelectric film 75 is reduced by hydrogen radicals without causing a catalytic action against hydrogen. Problem is suppressed, and the hydrogen resistance of the capacitor is improved.

The material of the second upper electrode 76B is Ir, Ru, Rh, Re instead of IrO _2.
, Os, Pd, oxides thereof, conductive oxides such as SrRuO ₃ , or a stacked structure thereof may be used.

  Next, steps required until a sectional structure shown in FIG.

First, as a hydrogen barrier film 77 on the second upper electrode film 76, an Ir film is sputtered to form A
In an r atmosphere, the film is deposited to a thickness of 100 nm with a sputtering power of 1.0 kW under a pressure of 1 Pa. The hydrogen barrier film 77 is not limited to the Ir film, and a Pt film or a SrRuO ₃ film may be used.

After the back surface of the silicon substrate 1 is cleaned, the first and second upper electrode films 76A and 76B, the first and second ferroelectric films 74 and 75, the first and second lower electrode films 72A and 72B, etc. A first protective film 78 and a mask material layer 79 which are used as a hard mask when patterning are sequentially formed.

The first protective film 78 is formed on the hydrogen barrier film 77 and formed by sputtering.
It consists of iN. The first protective film 78 may be a TiAlN, TaAlN, TaN film, or a laminated film thereof.

The mask material layer 79 is formed on the first protective film 78 and is made of, for example, a silicon oxide film formed by a CVD method using a TEOS gas.

Thereafter, a photoresist is applied on the mask material layer 79, and then the photoresist is exposed and developed to form a resist pattern having a capacitor planar shape.

Next, as shown in FIG. 7E, in etching, the mask material layer 79 is first patterned into an island shape using the resist pattern as a mask, and the first protective film 78 is used using the mask material layer 79 as a mask. Etch. As a result, a hard mask including the mask material layer 79 (second mask) and the first protective film 78 (first mask) is formed in an island shape in the capacitor formation region. Thereafter, the resist pattern on the mask material layer 79 is removed.

  Next, steps required until a sectional structure shown in FIG.

By plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ as an etching gas, portions of the first and second upper electrode films 76A and 76B that are not covered with the hard mask are formed.
The first and second ferroelectric films 74 and 75 and the second lower electrode films 72A and 72B are dry-etched.

Thus, the upper electrode films 76A and 76B are patterned to form the capacitor upper electrode 80, and similarly, the lower electrode films 72A and 72B are patterned to form the capacitor lower electrode 73.

A ferroelectric capacitor 81 having an upper electrode 80, ferroelectric films 74 and 75, and a lower electrode 73 is formed.

Next, the portions of the crystalline conductive adhesive film 71 and the underlying conductive film 70 that are not covered with the ferroelectric capacitor 81 are removed by etching, and these films are left in an island shape only under the ferroelectric capacitor 81.

Note that the mask material layer 79 in the hard mask is removed after the etching. On the other hand,
The first protective film 78 is left without being removed.

Etching of the base conductive film 70 and the crystalline conductive adhesive film 71 is performed by, for example, downflow plasma etching. As the condition, 5% CF ₄ in the flow rate ratio in the chamber.
A mixed gas of gas and 95% O ₂ gas is supplied as an etching gas, and high-frequency power with a frequency of 2.45 GHz and a power of 1400 W is supplied to the upper electrode of the chamber to bring the substrate temperature to 200 ° C.

As shown in an enlarged view in FIG. 8, the first protective film 78 is sandwiched between an upper region 78A and a lower region 78B having a high oxygen content, and an upper region 78A and a lower region 78B in the stacking direction. , 78B, a film center region 78C having a relatively lower oxygen concentration is formed.
That is, the first protective film 78 has a portion with a different oxygen concentration in the stacking direction.

The side region 78D, which is the outer peripheral surface region of the first protective film 78, is formed integrally with the upper region 78A and has substantially the same oxygen concentration. That is, the first protective film 78 has a different oxygen concentration in the stacking direction except for the side region 78D. More specifically, except for the side region 78D, the oxygen concentration in the film center region 78C is lower than the oxygen concentration in each of the upper region 78A and the lower region 78B. The ratio of the film thickness in each region is preferably the same as that in the first embodiment.

As a result, the first protective film 78 has a layer structure of TiO _x , TiON, TiO _y (x> y) or a layer structure of TiO _x , TiO _y , TiON (x> y), or TiO _x , TiO in order from the bottom.
It comes to have a layer structure of N, TiO _x .

The first protective film 78 is not limited to the TiN film, and Ti, TiN, Ta, TaN, TiA
l, TaAl, TiAlN, TaAlN, TiSiN, TaSiN, TiSi, TaSi
You may form from either. In other words, the oxidized first protective film 78 is TaN, TiON.
, TiO _x , TaO _x , TaON, TiAlO _x , TaAlO _x , TiAlON, TaA
lON, TiSiON, TaSiON, TiSiO _x , TaSiO _x , AlO _x , ZrO
You may form from materials, such as _x .

Further, since the side portion of the first protective film 78 that also functions as a hard mask is etched to some extent, the area of the upper region in the film thickness direction becomes smaller than the area of the lower region.

  Next, steps required until a sectional structure shown in FIG.

Al ₂ O as a second protective film 82 covering the ferroelectric capacitor 81 and the second interlayer insulating film 62
₃ is formed to a thickness of 20 nm by sputtering. Alternatively, AlO having a thickness of 2 nm to 5 nm is formed by MOCVD or ALD.

Here, recovery annealing is performed in an oxygen-containing atmosphere for the purpose of recovering damage to the ferroelectric films 74 and 75. The conditions for the recovery annealing are not particularly limited. For example, the recovery annealing is performed in a furnace at a substrate temperature of 550 ° C. to 700 ° C. When the ferroelectric films 74 and 75 are PZT, 60
It is preferable to perform annealing for 60 minutes in an oxygen atmosphere at 0 ° C. By this heat treatment, TiN in the first protective film 78 which is a hard mask is oxidized. The oxygen content of the oxidized TiN film is higher in the upper region in the longitudinal direction (stacking direction) of the film than in the lower region.

Next, Al ₂ O ₃ is formed to a thickness of about 38 nm as a third protective film 83 by a CVD method so as to cover the first protective film 78 and the ferroelectric capacitor 81.

The aluminum oxide film constituting the third protective film 83 is excellent in the function of preventing a reducing substance such as hydrogen or moisture from permeating. This prevents the ferroelectric characteristics of the ferroelectric films 74 and 75 from being deteriorated by the reducing substance.

The third protective film 83 is used to prevent the second and third insulating protective films 82 and 83 from peeling off.
Annealing may be performed in a furnace containing oxygen before the formation of. The annealing conditions are, for example, a substrate temperature of 350 ° C. and a processing time of 1 hour. The third protective film 83 is not only aluminum oxide,
A titanium oxide film, a tantalum oxide film, a zirconium oxide film, an aluminum nitride film, a tantalum nitride film, and an aluminum oxynitride film may be used. The second and third protective films 82 and 83 correspond to the second protective film 30 of the first embodiment, and may be formed of the same material.

Next, on the entire surface of the third protective film 83, silicon oxide is formed as a third interlayer insulating film 85 with a film thickness of 1500 nm by, for example, plasma TEOSCVD. When a silicon oxide film is formed as the third interlayer insulating film 85, for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas. As the third interlayer insulating film 85, for example, an insulating inorganic film or the like may be formed. After the third interlayer insulating film 85 is formed, the surface is planarized by, for example, CMP.

Subsequently, a plasma atmosphere generated by using N 2 _O gas or N ₂ gas or the like, to remove the moisture in the third interlayer insulating film 85 by heat treatment. At this time, the film quality of the third interlayer insulating film 85 is improved and it becomes difficult for moisture to enter the film.

  Next, steps required until a sectional structure shown in FIG.

First, the barrier film 86 is formed on the entire surface of the third interlayer insulating film 85 by, for example, sputtering or CVD. As the barrier film 86, for example, an aluminum oxide film having a thickness of 20 nm to 100 nm is used. Since the barrier film 86 is formed on the planarized third interlayer insulating film 85, the surface of the barrier film 86 becomes flat.

Further, a fourth interlayer insulating film 87 is formed on the entire surface of the barrier film 86 by, for example, a plasma TEOSCVD method. As the fourth interlayer insulating film 87, for example, the film thickness is 800 nm to 1000 nm.
The silicon oxide film is used. As the fourth interlayer insulating film 87, a SiON film, a silicon nitride film, or the like may be formed. When the fourth interlayer insulating film 87 is formed, the surface thereof is, for example, C
Flatten with MP.

Subsequently, via holes 88A and 88B are formed in the fourth interlayer insulating film 87 using a resist mask. When forming the via holes 88A and 88B, the hydrogen barrier film 77 covering the upper electrode 80 of the capacitor 81 is exposed, and then heat treatment is performed at 550 ° C. in an oxygen atmosphere.
Thereby, oxygen vacancies generated in the first ferroelectric film 74 when the via holes 88A and 88B are formed are recovered. Thereafter, a via hole 89 is formed on the conductive plug 18B in the center of the p-well 3.

  Next, steps required until a sectional structure shown in FIG.

Conductive plugs 90A, 90B, and 90C are formed in the via holes 88 and 89, respectively. First, it is preferable to form a single layer of TiN film as an adhesion layer on the inner surfaces of the via holes 88 and 89. The adhesion layer may have a laminated structure in which a Ti film is formed by sputtering and a TiN film is formed thereon by MOCVD. In this case, in order to remove carbon from the TiN film, treatment in a mixed gas plasma of nitrogen and hydrogen is required. However, the hydrogen barrier film 7 made of Ir is formed on the upper electrode 80.
7 is formed, so that the reduction of the upper electrode 80 is prevented.

The via holes 88A and 88B are formed through the first protective film 78 to reach the conductive hydrogen barrier film 77. However, when the hydrogen barrier film 77 is formed of an insulating material, the via holes 88A and 88B are formed. 88B is formed to a depth reaching the upper electrode 80.

  Next, steps required until a sectional structure shown in FIG.

A wiring pattern is formed on the fourth interlayer insulating film 87 corresponding to the conductive plugs 90A, 90B, 90C. That is, for example, by sputtering, a Ti film having a film thickness of 60 nm and a film thickness of 30 n
m TiN film, an AlCu alloy film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are sequentially formed. Thereby, a laminated film composed of a Ti film, a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed.

Next, the laminated film is patterned using a photolithography technique. As a result, wirings (first metal wiring layers) 92A and 92B made of a laminated film are formed. Thereby, the upper electrode film 80 of the ferroelectric capacitor 81 and the wiring 92A are electrically connected via the conductive plugs 90A and 90B. Similarly, the first source / drain region 11A and the wiring 92B are electrically connected through the conductive plugs 18B and 90C.

Thereafter, although not shown in the drawing, after forming an interlayer insulating film, a conductive plug is formed and wirings in the second to fifth layers from the bottom are formed. Then, when a cover film made of, for example, a TEOS oxide film and a SiN film is formed, a ferroelectric memory having a ferroelectric capacitor is completed.

As described above, in the first protective film 78 in this embodiment, the oxygen concentration in the upper region 78A and the lower region 78B becomes higher than that in the film center region 78C by the recovery annealing of the ferroelectric capacitor 81. It has a structure. Such a first protective film 78 is formed on the upper electrode 8.
It functions as a metal mask for patterning 0 and has the function of preventing the transmission of reducing substances. That is, after the patterning of the ferroelectric capacitor 81, it remains on the upper electrode 80 without being removed, and functions as a barrier film that prevents the reducing substance from passing through the ferroelectric capacitor 81. As a result, the manufacturing process of the semiconductor device can be simplified and the occurrence of defects is suppressed, thereby improving the production efficiency. Furthermore, the reliability of the ferroelectric memory (semiconductor device) can be improved.

In addition to the sputtering method and the MOCVD method, the ferroelectric films 74 and 75 can be formed by a sol-gel method, an organic metal decomposition (MOD) method, CSD (Chemical Solution Deposition).
) Method, chemical vapor deposition (CVD) method, epitaxial growth method and the like.

In addition, as the ferroelectric films 74 and 75, for example, a film whose crystal structure becomes a Bi layer structure or a perovskite structure can be formed by heat treatment. Such films include PZ
In addition to T film, PZT, SBT, BLT doped with a small amount of La, Ca, Sr and / or Si, etc.
And film can be cited of the general formula ABO _3, such as Bi-based layered compound.

In forming the first upper electrode film 76A, for example, sputtering using a target containing platinum, iridium, ruthenium, rhodium, rhenium, osmium, and / or palladium is performed under conditions in which oxidation of these noble metal elements occurs. Can be done below. In particular,
In the case of forming an Ir oxide film, the film formation temperature is preferably 20 ° C. to 400 ° C., for example, 300 ° C. Further, the partial pressure of the oxygen gas with respect to the pressure of the oxygen gas and the inert gas constituting the sputtering gas is preferably 10% to 60%. The film thickness is preferably 10 nm to 75 nm.

The heat treatment temperature after forming the first upper electrode film 76A is preferably 650 ° C. to 750 ° C., for example 700 ° C., and the heat treatment atmosphere preferably has an oxygen content of 1% to 50%. .

Further, the conductive film formed on the first upper electrode 76A is not limited to the IrO _x film, but is platinum (Pt), iridium (Ir), ruthenium (Ru), rhodium (Rh), rhenium (Re). A metal film containing a noble metal element such as osmium (Os) and / or palladium (Pd) may be formed. Further, these oxide films, for example, SrRuO ₃ films may be formed. Alternatively, a film having a two-layer structure or more may be formed as the conductive film.

The configuration of the first protective film 78 is the same as that of the first embodiment, for example, FIG. 3, FIG. 4A, FIG. 4B.
The structure shown in FIG. 5 may be used.

Hereinafter, embodiments of the present invention will be further described.
(Appendix 1) A semiconductor substrate, a ferroelectric capacitor having a lower electrode, a ferroelectric film, and an upper electrode sequentially stacked on the semiconductor substrate with an insulating film interposed therebetween, and in the stacking direction of the ferroelectric capacitor, provided above the upper electrode, it is provided in a region including a first protective layer having a distribution different portions of the oxygen concentration in the film thickness direction, above the first protective film, and the sidewall of the ferroelectric capacitor first wherein a has 2 and the protective film.
(Additional remark 2) The said 1st protective film has a part with the said oxygen concentration of a lower area | region lower than the upper area | region of a film thickness direction, The semiconductor device of Additional remark 1 characterized by the above-mentioned .
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the first protective film has a portion where the oxygen concentration is lower in a central portion of the film than in an upper region and a lower region in the film thickness direction .
(Supplementary Note 4) The first protective film has a portion in which at least a part of the upper region has the uniform high oxygen concentration in the film thickness direction, and the lower the region, the lower the oxygen concentration is. The semiconductor device according to any one of appendices 1 to 3, wherein the semiconductor device includes:
(Supplementary Note 5) The first protective film has a configuration in which a plurality of films are stacked, and a lower protective film disposed in the lowermost layer in the stacking direction, an upper protective film disposed in the uppermost layer, and these two The semiconductor according to claim 1, further comprising an intermediate protective film sandwiched between two films, wherein the oxygen concentration of the intermediate protective film is lower than the oxygen concentration of each of the upper protective film and the lower protective film apparatus.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the first and second protective films are formed of different materials.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the second protective film is a stacked body of a plurality of films having the same component or different components.
(Supplementary Note 8) The first protective film is made of TiO _x , TiON, TaO _x , TaON, TiAlO _x , TaAlO _x , TiAlON, TaAlON, TiSiON, TaSiON, TiSiO _x , TaSiO _x , AlO _x , ZrO _x film. 6. The semiconductor device according to appendix 5, wherein the semiconductor device is one selected from the group consisting of:
(Additional remark 9) The said intermediate protective film is 1 type selected from the group which consists of TiON, TaON, TiAlON, TaAlON, TiSiON, TaSiON film | membrane, The semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary note 10) The semiconductor device according to any one of supplementary notes 1 to 9, wherein the first protective film has an upper surface having a smaller area than a lower surface.
(Supplementary Note 11) lower conductive film above a semiconductor substrate, a ferroelectric film, and a step of laminating an upper conductive layer, forming a first protective film on the upper electrode, the first protective film and the by patterning the upper conductive layer, and forming an upper electrode of the capacitor from the conducting film, by heating the ferroelectric film and the first protective film in an oxygen atmosphere, the first protective film in a heat treatment step the oxygen concentration to form different portions in the thickness direction, by patterning the ferroelectric film and the lower conductive layer, forming a lower electrode of the capacitor from the lower conductive layer, wherein Forming a second protective film that covers the first protective film and the capacitor , and a method for manufacturing a semiconductor device .
(Supplementary Note 12) lower conductive film above a semiconductor substrate, a ferroelectric film, and an upper conductive film and the step of sequentially stacked in the order of the first hard mask and the second hard mask on the upper conductive film forming, a step of using the first and second hard mask, to form the lower conductive layer, the ferroelectric capacitor by patterning the ferroelectric film, and the upper conductive layer, wherein the strong After forming the dielectric capacitor, removing the second hard mask while leaving the first hard mask ; heating the ferroelectric capacitor and the first hard mask in an oxygen atmosphere; a heat treatment step of the distribution of at least the oxygen concentration in the film thickness direction partially oxidized in the first mask to form a first protective layer having a different portion, the covering the first protective film and the ferroelectric capacitor The method of manufacturing a semiconductor device characterized by having a step of forming a protective film.
(Additional remark 13) The manufacturing method of the semiconductor device of Additional remark 12 characterized by performing the process which performs the said heat processing on 550 degreeC thru | or 700 degreeC temperature conditions.
(Supplementary note 14) The semiconductor device manufacturing method according to supplementary note 12 or supplementary note 13, wherein a film containing a noble metal oxide is formed as the upper conductive film.
(Supplementary note 15) The method for manufacturing a semiconductor device according to Supplementary note 12, wherein the heat treatment includes a step of forming a portion in which the lower region is lower than the upper region in the oxygen concentration in the first hard mask. .
(Supplementary Note 16) The supplementary notes 12 to 12, wherein the heat treatment includes a step of forming a portion where the oxygen concentration in the first hard mask is lower in the center of the film than in the upper region and the lower region. 15. A method for manufacturing a semiconductor device according to claim 15.
(Supplementary note 17) Any one of Supplementary notes 12 to 16, wherein the step of patterning the upper conductive film and the first protective film includes a step of making an upper surface of the first protective film narrower than an area of a lower surface. The manufacturing method of the semiconductor device as described in one.
(Supplementary Note 18) The step of forming the first protective film is a film selected from the group consisting of Ti, TiN, Ta, TaN, TiAl, TaAl, TiAlN, TaAlN, TiSiN, TaSiN, TiSi, and TaSi film. 18. The method of manufacturing a semiconductor device according to any one of appendices 12 to 17, wherein the semiconductor device is formed.
(Supplementary note 19) The step of forming the first protective film includes a lower layer protective film disposed in the lowermost layer in the stacking direction, an intermediate protective film formed on the lower layer protective film, and an upper layer disposed on the uppermost side. And adding the protective film in order, wherein the intermediate protective film is formed so that the oxygen concentration is lower than each of the upper protective film and the lower protective film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

FIG. 1A is a sectional view (No. 1) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1B is a sectional view (No. 2) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1C is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a sectional view (No. 4) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1E is a cross-sectional view (part 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1F is a sectional view (No. 6) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1G is a sectional view (No. 7) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1H is a sectional view (No. 8) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1I is a sectional view (No. 9) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1J is a sectional view (No. 10) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1K is a sectional view (No. 11) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 2A is a cross-sectional view illustrating the configuration of the first protective film, and FIG. 2B is a graph illustrating an example of a change in oxygen concentration in the film thickness direction. FIG. 3A is a cross-sectional view illustrating a modification of the configuration of the first protective film, and FIG. 3B is a graph illustrating an example of a change in oxygen concentration in the film thickness direction. FIG. 4A is a cross-sectional view illustrating a first modification of the configuration of the first protective film on the capacitor in the semiconductor device according to the first embodiment of the present invention. FIG. 4B is a cross-sectional view illustrating a second modification of the configuration of the first protective film on the capacitor in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a third modification of the configuration of the first protective film on the capacitor in the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a capacitor of the semiconductor device according to the reference. FIG. 7A is a sectional view (No. 1) showing a manufacturing step of the semiconductor device according to the second embodiment of the invention. FIG. 7B is a cross-sectional view (part 2) illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 7C is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 7D is a sectional view (No. 4) showing the manufacturing step of the semiconductor device according to the second embodiment of the invention. FIG. 7E is a sectional view (No. 5) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIG. 7F is a sectional view (No. 6) showing a manufacturing step of the semiconductor device according to the second embodiment of the invention. FIG. 7G is a sectional view (No. 7) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIG. 7H is a sectional view (No. 8) showing a manufacturing step of the semiconductor device according to the second embodiment of the invention. FIG. 7I is a sectional view (No. 9) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIG. 7J is a sectional view (No. 10) showing a manufacturing step of the semiconductor device according to the second embodiment of the invention. FIG. 8 is a cross-sectional view illustrating the configuration of the first protective film on the capacitor in the semiconductor device according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 16 1st interlayer insulation film 11A 1st source / drain region 11B 2nd source / drain region 17A, 17B, 17C 1st contact hole 18A, 18B, 18C, 18D, 18E, 44A, 45B, 45C, 45D, 45E
, 64A, 64B, 90A, 90B, 90C Conductive plugs 20, 62 Second interlayer insulating film 22 First conductive film 23, 75 First ferroelectric film 24, 75 Second ferroelectric film 25 Second conductive film
2 7, 51, 52, 78 First protective film (first mask)
27A, 51B, 52C, 78A Upper region 27B, 51A, 52A, 78B Lower region 27C, 52B, 78C Film center region 28, 80 Upper electrode 29, 73 Lower electrode 30 Second protective film 30A First layer 30B Second layer 31 , 81 Ferroelectric capacitor 33, 85 Third interlayer insulating film 35, 87 Fourth interlayer insulating film 38 Photoresist film 41, 42, 43, 88, 89 Contact hole 72A First lower electrode film 72B Second lower electrode film 76A First upper electrode film 76B Second upper electrode film 79 Mask material layer (second mask)

Claims (5)

A semiconductor substrate;
A ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode sequentially stacked on the semiconductor substrate via an insulating film;
A first protective film provided above the upper electrode in the stacking direction of the ferroelectric capacitor and having a portion having a different oxygen concentration distribution in the film thickness direction;
A second protective film for preventing diffusion of a reducing element provided above the first protective film and in a region including a sidewall of the ferroelectric capacitor;
A conductive plug that penetrates the first protective film and the second protective film and reaches the upper electrode;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first protective film has a portion in which the oxygen concentration is lower in a lower region than in an upper region in the film thickness direction.   2. The semiconductor device according to claim 1, wherein the first protective film includes a portion having a lower oxygen concentration in a portion that is a film center than an upper region and a lower region in a film thickness direction. Laminating a lower conductive film, a ferroelectric film, and an upper conductive film over a semiconductor substrate;
Forming a first protective film on the upper conductive film ;
Forming an upper electrode of a capacitor from the upper conductive film by patterning the first protective film and the upper conductive film;
A heat treatment step in which the ferroelectric film and the first protective film are heated in an oxygen atmosphere to form portions in the first protective film having different oxygen concentrations in the film thickness direction;
Forming a lower electrode of the capacitor from the lower conductive film by patterning the ferroelectric film and the lower conductive film;
Forming a second protective film for preventing reduction element diffusion covering the first protective film and the capacitor;
Forming a conductive plug that penetrates the first protective film and the second protective film and reaches the upper electrode;
A method for manufacturing a semiconductor device, comprising: Laminating a lower conductive film, a ferroelectric film, and an upper conductive film in order over the semiconductor substrate;
Sequentially forming a first hard mask and a second hard mask on the upper conductive film;
Patterning the lower conductive film, the ferroelectric film, and the upper conductive film using the first and second hard masks to form a ferroelectric capacitor having an upper electrode ;
After forming the ferroelectric capacitor, removing the second hard mask leaving the first hard mask;
The ferroelectric capacitor and the first hard mask are heated in an oxygen atmosphere to oxidize at least a part of the first hard mask and to have a portion having a different oxygen concentration distribution in the film thickness direction. A heat treatment step for forming a film;
Forming a second protective film for preventing diffusion of a reducing element covering the first protective film and the ferroelectric capacitor;
Forming a conductive plug that penetrates the first protective film and the second protective film and reaches the upper electrode;
A method for manufacturing a semiconductor device, comprising:

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