JP5300120B2 - Thyristor - Google Patents

Thyristor Download PDF

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JP5300120B2
JP5300120B2 JP2007227315A JP2007227315A JP5300120B2 JP 5300120 B2 JP5300120 B2 JP 5300120B2 JP 2007227315 A JP2007227315 A JP 2007227315A JP 2007227315 A JP2007227315 A JP 2007227315A JP 5300120 B2 JP5300120 B2 JP 5300120B2
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cathode
gate
thyristor
anode
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JP2009059978A (en
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律夫 岡
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thyristor having a high gate-cathode breakdown voltage. <P>SOLUTION: On the first major surface of a first conductivity semiconductor substrate, a cathode region of a first conductivity impurity region, an anode region of a second conductivity impurity region surrounding the cathode region, and a mesa trench between the cathode region and the anode region are provided. On the second major surface of the semiconductor substrate, a gate region of a second conductivity impurity region, and a mesa trench having a depth reach the gate region from the first major surface are provided, a cathode metal electrode is provided in the cathode region on the first major surface, an anode metal electrode is provided in the anode region, and a gate metal electrode is provided on the gate region of the second major surface. Since a sufficient distance can be secured between the gate and the cathode in the thyristor, a high gate-cathode breakdown voltage can be ensured. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、パワーエレクトロニクス分野におけるスイッチング素子、特に用途としてゲート・カソード間耐圧が必要なサイリスタに関するものである。   The present invention relates to a switching element in the field of power electronics, and more particularly to a thyristor that requires a gate-cathode breakdown voltage as an application.

従来この種のサイリスタの構造は、カソード電極とゲート電極を同一面に形成する構造を有していた。(特許文献1参照)。   Conventionally, this type of thyristor has a structure in which a cathode electrode and a gate electrode are formed on the same surface. (See Patent Document 1).

しかしながら、このように形成される従来のサイリスタにおいては、ゲート・カソード間耐圧を高く確保するためには、ゲート領域とカソード領域間接合をその間隔幅が少ないために高耐圧接合即ち低不純物濃度化接合及び空乏層幅を確保することが難しくゲート・カソード間耐圧を確保することが困難であった。
特開平8−32049号公報
However, in the conventional thyristor formed in this way, in order to ensure a high gate-cathode breakdown voltage, the junction width between the gate region and the cathode region is small, so that a high breakdown voltage junction, that is, a low impurity concentration is achieved. It was difficult to ensure the junction and depletion layer width, and it was difficult to ensure the gate-cathode breakdown voltage.
JP-A-8-32049

本発明は、従来技術の問題点に注目して、ゲート・カソード間耐圧を、ゲート・カソード間の構造を第1主面と第2主面に分離することで、ゲート・カソード間耐圧を飛躍的に高く確保できるサイリスタ構造を提供することを目的とする。   In the present invention, the gate-cathode breakdown voltage is increased by separating the gate-cathode breakdown structure into a first main surface and a second main surface, focusing on the problems of the prior art. An object of the present invention is to provide a thyristor structure that can be secured at a high level.

本発明によるサイリスタによれば、第1導電型の半導体基板の第1主面には、第1導電型の不純物領域であるカソード領域と、前記カソード領域を取り囲むような第2導電型の不純物領域であるアノード領域と、前記カソード領域と前記アノード領域との間にはメサ溝部とを有し、前記半導体基板の第2主面のすべてには、第2導電型の不純物領域部であるゲート領域を有し前記メサ溝部は、すべて前記第1主面から前記ゲート領域まで達する深さを有し、前記第1主面の前記カソード領域にはカソード金属電極、前記アノード領域にはアノード金属電極を有し、前記第2主面の前記ゲート領域上にはゲート金属電極を有することを特徴とするサイリスタを提供するものである。
According to the thyristor of the present invention, the first main surface of the first conductivity type semiconductor substrate includes the cathode region which is the first conductivity type impurity region and the second conductivity type impurity region surrounding the cathode region. An anode region, and a mesa groove between the cathode region and the anode region, and a gate region that is a second conductivity type impurity region on all of the second main surface of the semiconductor substrate. And all the mesa grooves have a depth reaching from the first main surface to the gate region, the cathode region of the first main surface is a cathode metal electrode, and the anode region is an anode metal electrode And a thyristor having a gate metal electrode on the gate region of the second main surface.

本発明によるサイリスタによれば、半導体基板の第1主面にアノード領域とカソード領域、第2主面にゲート領域を構成することにより、ゲート・カソード間距離を確保し、結果としてゲート・カソード間耐圧を高く確保できる。   According to the thyristor of the present invention, an anode region and a cathode region are formed on the first main surface of the semiconductor substrate, and a gate region is formed on the second main surface, thereby ensuring a gate-cathode distance. High breakdown voltage can be secured.

以下、本発明の実施例に基づいて説明する。図1、図2、図3は、本発明の一実施例の構成を示す図であって、図1はサイリスタの図3におけるA−A’線断面図、図2はサイリスタの上面図、図3は底面図である。図4A−4Pは、図1、図2、3の実施例のサイリスタの製造ステップを示す工程図である。   Hereinafter, description will be made based on examples of the present invention. 1, 2, and 3 are views showing a configuration of an embodiment of the present invention, in which FIG. 1 is a cross-sectional view of the thyristor taken along the line AA ′ in FIG. 3, and FIG. 3 is a bottom view. 4A to 4P are process diagrams showing manufacturing steps of the thyristor of the embodiment of FIGS.

本発明の実施例のサイリスタによれば、第1図及び第2図に示されるように、第1導電型(N−)の半導体基板2の第1主面の中央部には、該半導体基板2より高濃度の第1導電型(N+)のカソード領域4が形成されており、このカソード領域4をメサ溝部6を介して取り囲むように高濃度第2導電型(P+)の不純物領域であるアノード領域3が形成される。また、半導体基板2の第1主面とは反対側には、高濃度第2導電型(P+)のゲート領域5が設けられており、前記メサ溝部6は、前記ゲート領域5にまで到達して形成されている。   According to the thyristor of the embodiment of the present invention, as shown in FIG. 1 and FIG. 2, the semiconductor substrate is disposed at the center of the first main surface of the semiconductor substrate 2 of the first conductivity type (N−). A cathode region 4 of the first conductivity type (N +) having a concentration higher than 2 is formed, and is an impurity region of the second concentration type (P +) of high concentration so as to surround the cathode region 4 via the mesa groove 6. An anode region 3 is formed. Further, a gate region 5 of high concentration second conductivity type (P +) is provided on the opposite side of the semiconductor substrate 2 from the first main surface, and the mesa groove 6 reaches the gate region 5. Is formed.

図1、図2に示すように、第1主面において、カソード領域4及びアノード領域3の表面には、金属蒸着法或いはメッキ法にてカソード金属電極8及びアノード電極9が形成され、第1主面上のカソード金属電極8及びアノード金属電極9以外のメサ溝部6を含む表面には、シリコン酸化膜乃至ガラス保護膜等のパッシべーション膜7が形成される。   As shown in FIGS. 1 and 2, a cathode metal electrode 8 and an anode electrode 9 are formed on the surfaces of the cathode region 4 and the anode region 3 on the first main surface by a metal vapor deposition method or a plating method. A passivation film 7 such as a silicon oxide film or a glass protective film is formed on the surface including the mesa groove 6 other than the cathode metal electrode 8 and the anode metal electrode 9 on the main surface.

図1、図3に示すように、第2主面において、金属蒸着法或いはメッキ法にてゲート金属電極10を形成する。   As shown in FIGS. 1 and 3, the gate metal electrode 10 is formed on the second main surface by a metal vapor deposition method or a plating method.

本発明の図1、図2、図3に示した実施例のサイリスタの製造工程について、図4Aから図4Pに基づいて説明する。
第1導電型(N−)の半導体基板2を用意し(図4A)、第1主面および第2主面に熱酸化法等により酸化膜11を形成する(図4B)。次に、写真工程で、レジスト塗布、露光、現像および酸化膜エッチングを行い、半導体基板2の第1主面のアノード領域部の酸化膜11を除去する(図4C)。ここに、第2導電型不純物のボロン等をデポジションして、第2導電型不純物領域であるアノード領域3を形成する(図4D)。次に、また酸化膜11を形成し(図4E)、写真工程により、カソード領域部の酸化膜11を除去し(図4F)、ここに、第1導電型(N+)不純物のリン等のデポジションを行い、カソード領域4を形成する(図4G)。
A manufacturing process of the thyristor of the embodiment shown in FIGS. 1, 2, and 3 of the present invention will be described with reference to FIGS. 4A to 4P.
A semiconductor substrate 2 of the first conductivity type (N−) is prepared (FIG. 4A), and an oxide film 11 is formed on the first main surface and the second main surface by a thermal oxidation method or the like (FIG. 4B). Next, resist application, exposure, development, and oxide film etching are performed in the photographic process, and the oxide film 11 in the anode region portion of the first main surface of the semiconductor substrate 2 is removed (FIG. 4C). Here, boron or the like of the second conductivity type impurity is deposited to form the anode region 3 as the second conductivity type impurity region (FIG. 4D). Next, an oxide film 11 is formed again (FIG. 4E), and the oxide film 11 in the cathode region is removed by a photographic process (FIG. 4F), where a first conductive type (N +) impurity such as phosphorus is removed. Positioning is performed to form the cathode region 4 (FIG. 4G).

次に、熱拡散工程によって、アノード部およびカソード部の熱拡散処理に兼ねて酸化膜11も形成する(図4H)。写真工程にて第1主面ではアノード部、第2主面では、ゲート部の酸化膜11を除去する(図4I)。ここに、第2導電型不純物のボロン等のデポジションを行い、熱拡散処理を行い、アノード領域部の高濃度オーミック部12およびゲート領域部5を形成する(図4J)。   Next, the oxide film 11 is also formed by the thermal diffusion process in conjunction with the thermal diffusion processing of the anode part and the cathode part (FIG. 4H). In the photographic process, the oxide film 11 is removed from the anode portion on the first main surface and the gate portion on the second main surface (FIG. 4I). Here, deposition of boron or the like of the second conductivity type impurity is performed, and thermal diffusion treatment is performed to form the high-concentration ohmic portion 12 and the gate region portion 5 in the anode region portion (FIG. 4J).

次に、第1主面のメサ溝形成部の酸化膜11を写真工程で除去し(図4K)、シリコンエッチング工程でメサ溝部6を形成する(図4L)。次にガラス等のパッシべーション膜7を第1主面に形成し(図4M)、写真工程で電極コンタクト窓部のパッシべーション膜7および酸化膜11の除去を行い(図4N)、次に第1主面に金属蒸着法等により金属膜が形成され、写真工程によりアノード金属電極部9およびカソード金属電極部8が形成され(図4O)、第2主面にも金属蒸着法等により、ゲート金属電極部10を形成する(図4P)。   Next, the oxide film 11 in the mesa groove forming portion on the first main surface is removed by a photographic process (FIG. 4K), and a mesa groove portion 6 is formed by a silicon etching process (FIG. 4L). Next, a passivation film 7 such as glass is formed on the first main surface (FIG. 4M), and the passivation film 7 and the oxide film 11 in the electrode contact window are removed by a photographic process (FIG. 4N). A metal film is formed on the first main surface by a metal vapor deposition method or the like, an anode metal electrode portion 9 and a cathode metal electrode portion 8 are formed by a photographic process (FIG. 4O), and a metal vapor deposition method or the like is also formed on the second main surface. Then, the gate metal electrode portion 10 is formed (FIG. 4P).

図5A−5Pの工程で形成した図1、図2、図3のサイリスタの実施例によれば、従来構造例に比較し、カソードを第1主面、ゲートを第2主面に配することにより、ゲート・カソード間距離を飛躍的に増加させ、ゲート・カソード間耐圧を高くすることを可能とする。   According to the embodiment of the thyristor of FIGS. 1, 2 and 3 formed in the steps of FIGS. 5A-5P, the cathode is arranged on the first main surface and the gate is arranged on the second main surface as compared with the conventional structure example. As a result, the gate-cathode distance can be dramatically increased and the gate-cathode breakdown voltage can be increased.

本発明の一実施例サイリスタの図3のA−A’線断面図。FIG. 4 is a cross-sectional view taken along line A-A ′ of FIG. 図1の上面図。The top view of FIG. 図1の底面図。The bottom view of FIG. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention. 本発明のサイリスタの製造工程図。The manufacturing process figure of the thyristor of this invention.

符号の説明Explanation of symbols

1 半導体チップ
2 第1導電型の半導体基板
3 アノード領域
4 カソード領域
5 ゲート領域
6 メサ溝部
7 パッシべーション膜
8 カソード金属電極
9 アノード金属電極
10 ゲート金属電極
11 酸化膜
12 アノード領域の高濃度オーミック部
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor substrate of 1st conductivity type 3 Anode area 4 Cathode area 5 Gate area 6 Mesa groove part 7 Passivation film 8 Cathode metal electrode 9 Anode metal electrode 10 Gate metal electrode 11 Oxide film 12 High concentration ohmic of anode area Part

Claims (1)

第1導電型の半導体基板の第1主面には、第1導電型の不純物領域であるカソード領域と、前記カソード領域を取り囲むような第2導電型の不純物領域であるアノード領域と、前記カソード領域と前記アノード領域との間にはメサ溝部とを有し、前記半導体基板の第2主面のすべてには、第2導電型の不純物領域部であるゲート領域を有し前記メサ溝部は、すべて前記第1主面から前記ゲート領域まで達する深さを有し、前記第1主面の前記カソード領域にはカソード金属電極、前記アノード領域にはアノード金属電極を有し、前記第2主面の前記ゲート領域上にはゲート金属電極を有することを特徴とするサイリスタ。 The first main surface of the first conductivity type semiconductor substrate has a cathode region that is an impurity region of the first conductivity type, an anode region that is an impurity region of the second conductivity type surrounding the cathode region, and the cathode There is a mesa groove between the region and the anode region, and all of the second main surface of the semiconductor substrate has a gate region which is a second conductivity type impurity region, and the mesa groove is , All having a depth reaching from the first main surface to the gate region, the cathode region of the first main surface having a cathode metal electrode, the anode region having an anode metal electrode, and the second main surface A thyristor comprising a gate metal electrode on the gate region of a surface.
JP2007227315A 2007-09-03 2007-09-03 Thyristor Active JP5300120B2 (en)

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GB1587540A (en) * 1977-12-20 1981-04-08 Philips Electronic Associated Gate turn-off diodes and arrangements including such diodes
JP5155600B2 (en) * 2007-05-24 2013-03-06 新電元工業株式会社 Electrostatic induction thyristor

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