JP5294278B2 - デュアルメタルゲート構造の形成方法 - Google Patents

デュアルメタルゲート構造の形成方法 Download PDF

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Publication number
JP5294278B2
JP5294278B2 JP2010514910A JP2010514910A JP5294278B2 JP 5294278 B2 JP5294278 B2 JP 5294278B2 JP 2010514910 A JP2010514910 A JP 2010514910A JP 2010514910 A JP2010514910 A JP 2010514910A JP 5294278 B2 JP5294278 B2 JP 5294278B2
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Japan
Prior art keywords
layer
forming
gate electrode
gate
electrode layer
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Expired - Fee Related
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JP2010514910A
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English (en)
Japanese (ja)
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JP2010532579A5 (enExample
JP2010532579A (ja
Inventor
ブイ． カーブ、ガウリ
カパッソ、クリスチアーノ
ビー． サマベダム、スリカンス
ケイ． シェーファー、ジェームズ
ジェイ．ジュニア テイラー、ウィリアム
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2010514910A 2007-06-29 2008-05-20 デュアルメタルゲート構造の形成方法 Expired - Fee Related JP5294278B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/771,690 US7445981B1 (en) 2007-06-29 2007-06-29 Method for forming a dual metal gate structure
US11/771,690 2007-06-29
PCT/US2008/064198 WO2009005904A1 (en) 2007-06-29 2008-05-20 Method for forming a dual metal gate structure

Publications (3)

Publication Number Publication Date
JP2010532579A JP2010532579A (ja) 2010-10-07
JP2010532579A5 JP2010532579A5 (enExample) 2011-06-23
JP5294278B2 true JP5294278B2 (ja) 2013-09-18

Family

ID=39916465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010514910A Expired - Fee Related JP5294278B2 (ja) 2007-06-29 2008-05-20 デュアルメタルゲート構造の形成方法

Country Status (5)

Country Link
US (1) US7445981B1 (enExample)
JP (1) JP5294278B2 (enExample)
CN (1) CN101689508B (enExample)
TW (1) TWI421980B (enExample)
WO (1) WO2009005904A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7666730B2 (en) * 2007-06-29 2010-02-23 Freescale Semiconductor, Inc. Method for forming a dual metal gate structure
US7790553B2 (en) * 2008-07-10 2010-09-07 International Business Machines Corporation Methods for forming high performance gates and structures thereof
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
DE102010028459B4 (de) * 2010-04-30 2018-01-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Reduzierte STI-Topographie in Metallgatetransistoren mit großem ε durch Verwendung einer Maske nach Abscheidung einer Kanalhalbleiterlegierung
EP2472573A1 (en) * 2011-01-04 2012-07-04 Nxp B.V. Vertical transistor manufacturing method and vertical transistor
DE102011079836B4 (de) * 2011-07-26 2017-02-02 Globalfoundries Inc. Reduzieren der Topographie von Isolationsgebieten bei der Herstellung einer Kanalhalbleiterlegierung in Transistoren
US9041116B2 (en) * 2012-05-23 2015-05-26 International Business Machines Corporation Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
KR20190034822A (ko) * 2017-09-25 2019-04-03 삼성전자주식회사 반도체 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100399356B1 (ko) * 2001-04-11 2003-09-26 삼성전자주식회사 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법
US6794252B2 (en) * 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
US6645818B1 (en) * 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
US6972224B2 (en) * 2003-03-27 2005-12-06 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
US6897095B1 (en) 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US20060084220A1 (en) * 2004-10-15 2006-04-20 Freescale Semiconductor, Inc. Differentially nitrided gate dielectrics in CMOS fabrication process
KR100719340B1 (ko) * 2005-01-14 2007-05-17 삼성전자주식회사 듀얼 게이트 전극을 갖는 반도체 소자 및 그 형성 방법
KR100697694B1 (ko) * 2005-08-02 2007-03-20 삼성전자주식회사 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
US7504696B2 (en) * 2006-01-10 2009-03-17 International Business Machines Corporation CMOS with dual metal gate

Also Published As

Publication number Publication date
TWI421980B (zh) 2014-01-01
CN101689508B (zh) 2011-08-17
JP2010532579A (ja) 2010-10-07
TW200903723A (en) 2009-01-16
CN101689508A (zh) 2010-03-31
WO2009005904A1 (en) 2009-01-08
US7445981B1 (en) 2008-11-04

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