JP5277615B2 - Data processing apparatus and data processing program - Google Patents

Description

  The present invention relates to a data processing apparatus and a data processing program.

  Patent Document 1 below describes an image processing apparatus that monitors processing loads of a plurality of processors and dynamically changes the processing share among the plurality of processors.

JP 2004-326307 A

  An object of the present invention is to provide a data processing device and a data processing program that process a plurality of data processes in parallel using a reconfigurable processing device and increase processing efficiency.

  In one aspect of the data processing device of the present invention, a reconfigurable processing device in which a plurality of data processing units that perform data processing by separately inputting data from each other are provided by reconfiguration of logical specifications, and data in the data processing unit Based on the monitoring result of the end of the processing and the monitoring result of the monitoring means, the logical specification of the data processing unit that is processing the data is not reconfigured, and the logic of one or more data processing units that have completed the processing Restructuring means for reconfiguring the specification and providing one or more new data processing units for performing the next data processing.

  In one aspect of the data processing apparatus of the present invention, data specifying information for specifying data to be processed next is added to the data to be processed, and the reconstructing means includes the data specifying information. Based on this, one or more new data processing units for performing the next data processing are provided.

  In one aspect of the data processing apparatus of the present invention, type specifying information for specifying the type of data processing is added to the data to be processed, and the reconstructing means is based on the type specifying information, One or more new data processing units for performing the next data processing are provided.

  In one aspect of the data processing apparatus of the present invention, the reconfiguration unit includes one or more new data processing units that perform the next data processing based on information that specifies the execution priority order of the plurality of data processings. Is provided.

  In one aspect of the data processing apparatus of the present invention, the reconstructing means performs processing when the scale of one or more data processing units that have completed processing is large and a new data processing unit cannot be provided. One or two or more new data processing units that perform the next data processing are provided after the processing of the internal data processing unit is completed.

  In one aspect of the data processing apparatus of the present invention, the data to be processed is image data, and the data processing apparatus further includes output means for performing image display output or image print output based on the data processing result. Prepare

  In one aspect of the data processing program of the present invention, a computer including a reconfigurable processing device in which a plurality of data processing units that perform data processing by separately inputting data from each other is provided by reconfiguring a logical specification. Monitoring means for monitoring the end of data processing in the processing section, and one or more data for which processing has been completed without reconfiguring the logical specifications of the data processing section during data processing based on the monitoring result of the monitoring means The logical specification of the processing unit is reconfigured to function as a reconfiguration unit that provides one or more new data processing units for performing the next data processing.

  According to the first aspect of the present invention, since a plurality of data processes are processed in parallel using the reconfigurable processing device, the processing efficiency can be improved.

  According to the second aspect of the present invention, it is possible to control reconfiguration based on data specifying information added to data to be processed.

  According to the third aspect of the present invention, it is possible to control reconstruction based on the type specifying information added to the data to be processed.

  According to the invention of claim 4, it is possible to perform a plurality of data processing based on the order of execution priority.

  According to invention of Claim 5, a data processing part is arrange | positioned according to the scale of a data processing part.

  According to the invention of claim 6, it is possible to increase the efficiency of image output.

  According to the seventh aspect of the present invention, since a plurality of data processes are processed in parallel using the reconfigurable processing device, the processing efficiency can be improved.

[Explanation of terms and concepts]
The data processing device is a device constructed using a computer (hardware) having an arithmetic processing function and a program (software) for controlling the computer. The data processing device includes a reconfigurable processing device, a monitoring unit, a reconfiguring unit, and the like.

  The reconfigurable processing device is an arithmetic processing device capable of reconfiguring logic specifications such as arithmetic logic or connection logic in software. In a reconfigurable processing apparatus, typically, a plurality of PEs (processor elements) are provided, and the logical specification is changed in units of PEs. Examples of the PE include an ALU (arithmetic logic unit) element provided with an arithmetic logic circuit and a memory element provided with a storage circuit. In the reconfigurable processing apparatus, a plurality of data processing units are provided as a result of setting logical specifications. Each data processing unit inputs data separately from each other and performs the data processing. The type of data processing is not particularly limited, and examples of data processing for image data include compression, expansion, color conversion, format conversion, and rendering.

  The monitoring means monitors the end of data processing in each data processing unit. The monitoring is performed, for example, by receiving a notification from the data processing unit or by making an inquiry to the data processing unit.

  The reconfiguration unit is a unit that reconfigures the reconfigurable processing device based on the monitoring result of the monitoring unit and changes its logical specification. The reconfiguring means performs the next data processing by reconfiguring the logical specifications of one or more data processing units that have finished processing, without reconfiguring the logical specifications of the data processing unit that is currently processing data. Alternatively, two or more new data processing units are provided. That is, as a result of the reconfiguration, the data processing unit that is processing data is maintained, and one or more data processing units that have completed the processing are changed to one or more new data processing units.

[Embodiment]
Hereinafter, embodiments of the present invention will be exemplified.

  FIG. 1 is a diagram showing an outline of a hardware configuration of an image processing system 10 according to the present embodiment. The image processing system 10 includes an image processing device 11, a network 30, and a PC (personal computer) 40. The image processing apparatus 11 is an apparatus as an example of a data processing apparatus, and the PC 40 is an apparatus used for a user to use the image processing apparatus 11. The image processing apparatus 11 and the PC 40 are connected to a network 30 constructed using the Internet or an intranet, and can communicate with each other.

  The image processing apparatus 11 includes a bus 12 as an internal communication path, a CPU (central processing unit) 14 connected to the bus 12, a memory 16, a reconfigurable device 18, a UI (user interface) 20, a scanner 22, a printer. 24, a CDD (Compact Disk Drive) 26, and a network interface 28. The CPU 14 is a device having an arithmetic processing function, and performs arithmetic processing, control of each component, and the like based on a program stored in the memory 16. The memory 16 is a storage device using a semiconductor element or the like, and stores a program and data for controlling the CPU 14 and the reconfigurable device 18, image data to be processed, and the like. The reconfigurable device 18 is a device as a reconfigurable processing device. The UI 20 is a device for a user to operate the image processing apparatus 11. The UI 20 is provided with an input device such as a touch panel and a keyboard for receiving input from the user, and a display device such as a liquid crystal panel for presenting image information to the user.

  The scanner 22 is a device for reading paper and generating image data, and the printer 24 is a device for printing on paper based on the image data. The CDD 26 is a device for reading and writing a CD (compact disc) as a recording medium. A program for controlling the image processing apparatus 11 may be provided through a CD. In this case, installation using the CDD 26 is performed. The network interface 28 is a device for communicating with the PC 40 and the like via the network 30. Further, a program for controlling the image processing apparatus 11 may be provided through the network 30. In this case, installation using the network interface 28 is performed.

  FIG. 2 is a diagram illustrating a hardware configuration of the reconfigurable device 18. The reconfigurable device 18 includes a bus 50, a reconfigurable processor 52 connected to the bus 50, a configuration memory 54, a processor 56, and an interface 58. The reconfigurable processor 52 is a processing device that includes a plurality of PEs and that can reconfigure its logical specifications. The configuration memory 54 is a storage device that uses a semiconductor element, and receives configuration data that defines the logical specifications of the reconfigurable processor 52. The processor 56 is a processing device that controls the reconfigurable device 18 and also serves as a reconfiguration scheduler of the reconfigurable processor 52. The operation of the processor 56 is generally controlled by a program. The interface 58 is a device that enables communication with the bus 12 of the image processing apparatus 11.

  FIG. 3 is a diagram for explaining processing functions set in the reconfigurable device 18. Here, image data generated by the scanner 22 is stored in the memory 16. The image data is input to the reconfigurable processor 52, and the processing result is output to the memory in the printer 24. A process for printing is assumed. In this processing, the reconfigurable processor 52, for example, performs image processing for converting image data expressed in the RGB color system to the YMCK color system, or image data for converting vector format image data into the raster format. Processing, image processing for compressing raster format image data, and the like are performed. In addition, the memory arbitration unit 60 reads out image data from the memory 16 and performs an arbitration process for inputting the image data to a predetermined location of the reconfigurable processor 52. Then, the memory arbitration unit 62 performs an arbitration process for writing processing results output from a plurality of locations of the reconfigurable processor 52 to the memory of the printer 24.

  In the illustrated example, the reconfigurable processor 52 includes four input buffers 64, 68, 72, 76, four address counters 66, 70, 74, 78, four image processing units 80, 82, 84, 86, Four output buffers 88, 92, 96, 100 and four address counters 90, 94, 98, 102 are constructed. The input buffers 64, 68, 72, and 76 acquire image data from the memory arbitration unit 60 and output the image data to the image processing units 80, 82, 84, and 86, respectively. Further, the address counters 66, 70, 74, 78 instruct the memory arbitration unit 60 of the storage addresses of the image data acquired by the input buffers 64, 68, 72, 76, respectively. The image processing units 80, 82, 84, 86 perform the set image processing on the input image data, and output the processing results to the output buffers 88, 92, 96, 100, respectively. The output buffers 88, 92, 96, and 100 output the processing results to the memory arbitration unit 62, and the output addresses are controlled by address counters 90, 94, 98, and 102, respectively.

  The processor 56 includes an end detection unit 110, a next processing area determination unit 112, a flow stop generation unit 114, a next processing load unit 116, and a next address setting unit 118 for scheduling the reconfigurable processor 52. Yes. The end detection unit 110 detects the end of image processing in the image processing units 80, 82, 84, 86 based on the output results from the output buffers 88, 92, 96, 100. The next processing area determination unit 112 determines in which area of the reconfigurable processor 52 the next image processing is to be executed, and typically the processing among the image processing units 80, 82, 84, 86. The next image processing is set to one or more processing units that have completed the above. The flow stop generation unit 114 temporarily stops the data flow and the execution of calculation when setting the next image processing. The next processing load unit 116 causes the configuration memory 54 to input configuration data for setting the next image processing, and thereby the processing target of the image processing units 80, 82, 84, 86 is changed. Reconfigure the logical specifications. Then, the next address setting unit 118 notifies the address counter 66, 70, 74, 78 of the address of the image data to be read.

  Here, the image data stored in the memory 16 will be described with reference to FIG. The image data is normally stored in order in the memory 16 based on a certain rule. However, in image processing, processing is not necessarily performed in the order of storage. In addition, the portions of the image data may be stored in an irregular order. In the illustrated example, the processing unit image data 120, 122, and 124 are stored in the memory 16 at positions where the addresses do not continue, but are set to be processed in this order.

  Each image data is composed of a header and processing data. For example, the image data 120 includes a header 126 and processing data 134, and information about the next address 128, the amount of captured data 130, and the processing type 132 is recorded in the header 126. The next address 128 represents the address where the image data 122 to be read next to the image data 120 is stored, and the amount of captured data indicates the size of the next image data 122. The processing type 132 indicates the type of image processing to be performed on the processing data 134.

  For reference, FIG. 5 shows a flow when image processing for such image data is executed by one image processing unit. In the process, first, a header of one unit of image data is fetched from the memory 16 (S10), and the header is interpreted (S12). Next, the type of image processing is determined based on the “type of processing” in the header, and the corresponding configuration data is loaded into the configuration memory 54 (S14). Further, the next address and the size of the fetched data amount are stored and set in the scheduler (S16). When the image processing starts (S18), the image processing unit captures the processing data (S20) and executes the image processing (S22). When the image processing for one unit is completed, it is determined whether or not the processing for all units (for example, one page) has been completed (S26), and the processing is ended (S28) or the processing for the next unit (S10). Transition.

  Next, processing when the four image processing units 80, 82, 84, and 86 shown in FIG. 3 are set in the reconfigurable processor 52 will be described with reference to FIGS.

  FIG. 6 is a diagram schematically illustrating the relationship between the image processing unit and the image data. The processor 56 first fetches the first image data 130 into the image processing unit 80 by the scheduling function. Then, the processor 56 sets the “next address” and the “captured data amount” in the header of the image data 130 in the address counter 70 corresponding to the image processing unit 82. The image processing unit 82 inputs the image data 132 according to the set “next address” and “capture data amount”. Further, the “next address” and “capture data amount” of the header of the image data 132 are set in the address counter 74 corresponding to the image processing unit 84. Similarly, the image processing unit 84 inputs the image data 134 according to the set “next address” and “capture data amount”, and the “next address” and “capture data amount” in the header of the image data 134 are: The address counter 78 of the image processing unit 86 is set. Further, the image processing unit 86 inputs the image data 136 according to the set “next address” and “capture data amount”. The “next address” and the “captured data amount” in the header of the image data 136 are set for the address counter of the image processing unit that has finished executing the processing.

  FIG. 7 is a flowchart illustrating a processing flow when four image processing units 80, 82, 84, 86 are set in the reconfigurable processor 52. In the processing, first, as described with reference to FIG. 6, four units of headers with N = 1 to 4 are fetched (S30), the address is set for the address counter, and the processing for the image processing unit is set by reconfiguration. Is performed (S32). The image processing unit captures the Nth unit of processing data and starts image processing (S34). Further, the processor 56 fetches and stores the header information of the (N + 1) th unit (S36). The end detection unit 110 monitors the end of image processing in any of the image processing units (S38). When the end detection is made, the next processing area determination unit 112 determines which image processing is to be performed next in which area (image processing unit), and the flow stop generation unit 114 determines the entire flow, that is, the data flow. The operation for that is temporarily stopped (S40). Then, the next processing load unit 116 changes the completed image processing unit to the next processing type and does not change the processing type of the remaining image processing unit (or constructs the same logical specification). Is executed (S42). Further, the next address setting unit 118 sets the address of the (N + 1) th unit in the address counter corresponding to the reconfigured image processing unit. This series of processing is repeated until the processing for all units is completed (S46).

  8 and 9 are diagrams illustrating examples in which image processing in the image processing unit is changed. In the example of FIG. 8, four processes of processes A, B, C, and D are performed in the four image processing units. However, when the process B ends, the flow is stopped and changed to the process E. Has been. FIG. 9 is a diagram showing temporal changes in the types of image processing set in the image processing units 80, 82, 84, 86. Processes A, B, C, and D are initially set for the image processors 80, 82, 84, and 86. Among them, the process B is completed earliest, and the logical specification for the process E is set in the image processing unit 82 by reconfiguration. Subsequently, the process D is finished and changed to the process F, and the process A is finished and changed to the process G. As described above, since the process is sequentially changed to a new process, the image processing units 80, 82, 84, and 86 always perform parallel processes. In the case where the same processing is performed on the next data as a matter of course, it is naturally not necessary to change the processing.

  Next, an aspect in which the size of the image processing unit changes will be described with reference to FIGS.

  FIG. 10 is a diagram corresponding to FIG. 7, and is a diagram for explaining the flow of processing in this mode. In this example, it is assumed that four image processing units are set in the reconfigurable processor 52 in the initial stage. Therefore, first, the header of N = 1 to 4th unit is fetched from the memory (S50). Then, the process of setting an address in the address counter and setting the process in the image processing unit (S52), the process of fetching the Nth unit of processing data and starting the image processing (S54), and the header of the (N + 1) th unit from the memory The process of taking in is performed in the same manner as in FIG.

  However, in this example, when the end of any process is detected (S58), it is determined whether or not a new process can be reconfigured (S60). This is determined based on whether the area required for the new process is larger than the area used for the completed process. When it is determined that reconfiguration is not possible, when it is detected that the next process has been completed (S58), it is determined whether or not a new process can be reconfigured again (S60). On the other hand, if the new process can be reconfigured, the entire flow is stopped (S62), the completed image process is reconfigured to the next image process (S64), and the corresponding address counter is updated to the (N + 1) th unit. Is set (S66). This series of processing is repeated until the processing of all units is completed (S68). If a plurality of image processes can be newly set after a certain image process is completed, a plurality of image processes are set.

  FIG. 11 is an example of a processing area table that manages the number of areas required for image processing. In this example, it is registered that one area is necessary for the processes A to D, three areas are necessary for the process E, and two areas are necessary for the process F. This processing area table is stored in the next processing area determining unit 112 shown in FIG. 3 and used for determining the next processing area.

  FIG. 12 is a schematic diagram for explaining the transition of image processing. In this example, the processes A, B, C, and D are executed, but the end of the process B is detected at the stage shown in FIG. Therefore, as shown in FIG. 12B, setting of the process E instead of the process B is being studied. However, since the area required for the process B is one while the area required for the process E is three, the process E cannot be set. For this reason, the remaining process is continued without setting the process E. Eventually, as shown in FIG. 12C, processes A and C are also terminated. Therefore, as shown in FIG. 12D, the areas of the processes A to C are reconfigured and the process E is set.

  FIG. 13 is a diagram corresponding to FIG. 9 and shows temporal changes in the types of image processing set in the reconfigurable processor 52. Here, initially, the processes A to D set by using each one area are executed. The process F to be executed next requires three areas, and is set after the completion of the three processes A, B, and C. Subsequently, when the process D ends, a process G that requires one area is set. Then, after the end of the process F, processes H, I, and J each requiring one area are set.

  In the above description, image processing for image data has been described. However, various types of data such as document data or audio data may be employed instead of image data.

It is a figure which shows the hardware structural example of an image processing system. It is a figure explaining the hardware structural example of a reconfigurable apparatus. It is a figure explaining the function structural example set to the reconfigurable apparatus. It is a figure explaining image data. It is a figure explaining the flow of processing used as a reference. It is a figure explaining the aspect by which image data is allocated to an image process part. It is a flowchart which shows the process in which an image process is performed by four image process parts. It is a figure which shows the example which changes a process by reconstruction. It is the figure which showed the transition of the process performed by four image process parts in time series. It is a flowchart explaining the setting process of the image processing from which the number of areas differs. It is a figure which shows the example of an area table. It is a figure which shows the example which changes a process by reconstruction. It is the figure which showed the example of a setting of the image processing from which the number of areas differs in time series.

Explanation of symbols

  10 image processing system, 11 image processing device, 12 bus, 14 CPU, 16 memory, 18 reconfigurable device, 20 UI, 22 scanner, 24 printer, 26 CDD, 28 network interface, 30 network, 40 PC, 50 bus, 52 reconfigurable processor, 54 configuration memory, 56 processor, 58 interface, 60, 62 memory arbitration unit, 64, 68, 72, 76 input buffer, 66, 70, 74, 78, 90, 94, 98, 102 address counter 80, 82, 84, 86 Image processing unit, 88, 92, 96, 100 Output buffer, 110 End detection unit, 112th order processing area judgment unit, 114 Flow stop generation unit, 116th order processing load unit, 118th order address set DOO unit, 120,122,124,130,132,134,136 image data, 126 header 128 primary address, 130 capture data amount, 132 types of processing, 134 process the data.

Claims (4)

A reconfigurable processing device in which a plurality of data processing units that perform data processing by separately inputting data from each other are provided by reconfiguration of logical specifications;
Monitoring means for monitoring the end of data processing in the data processing unit;
Based on the monitoring result of the monitoring means, the entire data input and data processing are temporarily stopped, the logical specification of the data processing unit during the data processing is not reconfigured, and the processing is completed. Reconfigure the logical specifications of the data processing unit to provide one or more new data processing units that perform the next data processing, and the scale of the one or more data processing units that have completed the processing is a new data processing If the size of the data processing unit is smaller than that of the data processing unit and a new data processing unit cannot be provided, the processing of the data processing unit being processed is completed and one or more new data processings are performed for the next data processing. Reconstruction means for providing a data processing unit;
Equipped with a,
The data to be processed is added with data specifying information for specifying the data to be processed next, and type specifying information for specifying the type of data processing to be performed on the data to be processed,
The reconfiguring means specifies data to be processed next based on the data specifying information, acquires type specifying information added to the data to be processed next, and acquires the type specifying information in the acquired type specifying information. Based on this, the scale of a new data processing unit that determines the size of a new data processing unit that performs data processing on the data to be processed next is determined, and the scale of one or more data processing units that have completed the processing is the scale of the new data processing unit. 1 or 2 or more new data processing units that perform the next data processing after waiting for the processing of the data processing unit being processed to end, when a new data processing unit cannot be provided. the data processing apparatus characterized by providing a. The data processing apparatus according to claim 1,
The reconfiguring means includes one or more new data processing units for performing next data processing based on information for specifying execution priority order of a plurality of data processing. The data processing apparatus according to claim 1 or 2 ,
The data to be processed is image data,
The data processing apparatus further comprises output means for performing image display output or image print output based on the data processing result. A computer including a reconfigurable processing device in which a plurality of data processing units that perform data processing by separately inputting data from each other are provided by reconfiguration of logical specifications,
Monitoring means for monitoring the end of data processing in the data processing unit;
Based on the monitoring result of the monitoring means, the entire data input and data processing are temporarily stopped, the logical specification of the data processing unit during the data processing is not reconfigured, and the processing is completed. Reconfigure the logical specifications of the data processing unit to provide one or more new data processing units that perform the next data processing, and the scale of the one or more data processing units that have completed the processing is a new data processing If the size of the data processing unit is smaller than that of the data processing unit and a new data processing unit cannot be provided, the processing of the data processing unit being processed is completed and one or more new data processings are performed for the next data processing. Reconfiguration means for providing a data processing unit,
To function as,
The data to be processed is added with data specifying information for specifying the data to be processed next, and type specifying information for specifying the type of data processing to be performed on the data to be processed,
The reconfiguring means specifies data to be processed next based on the data specifying information, acquires type specifying information added to the data to be processed next, and acquires the type specifying information in the acquired type specifying information. Based on this, the scale of a new data processing unit that determines the size of a new data processing unit that performs data processing on the data to be processed next is determined, and the scale of one or more data processing units that have completed the processing is the scale of the new data processing unit. 1 or 2 or more new data processing units that perform the next data processing after waiting for the processing of the data processing unit being processed to end, when a new data processing unit cannot be provided. data processing program and providing a.

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