JP5205843B2 - Arithmetic processing device and arithmetic processing program - Google Patents

Description

  The present invention relates to an arithmetic processing device or an arithmetic processing program.

  In Patent Document 1 below, when performing certain arithmetic processing, the CPU executes this processing during the reconfiguration of the reconfigurable circuit, and the reconfigurable circuit continues processing on behalf of the CPU after the reconfiguration is completed. Technology is disclosed. Note that the CPU and the reconfigurable circuit share data using a shared memory.

  The following Patent Document 2 includes a fixed value memory for storing a fixed value used in the operation of the reconfigurable circuit, in addition to the memory used for reconfiguring the reconfigurable circuit. A technique for reducing the storage capacity of a memory used for reconfiguration by setting a fixed value in a value memory is disclosed.

  Patent Document 3 below discloses a technique for generating a data flow graph representing the dependency of execution order between operations and determining the execution order of the data flow graph. The execution order is determined so as to shorten the waiting time for reading the data to be fed back, for example.

JP 2003-208305 A JP 2006-018453 A JP 2005-258593 A

  An object of the present invention is to provide an arithmetic processing device or an arithmetic processing program in which the processing time for generating a reference table in a reconfigurable circuit and executing an arithmetic operation is shortened compared to the case where the processing is performed by software processing. Is to provide.

  In one aspect of the arithmetic processing device of the present invention, an arithmetic circuit capable of reconfiguring arithmetic logic specifications, and a reconfigurable circuit including a storage circuit capable of reconfiguring data connection logic specifications with the arithmetic circuit; The operation logic specification and the connection logic specification are reconfigured to generate a generation logic for generating a reference table on the storage circuit, and a reference operation logic for performing an operation referring to the reference table on the operation circuit. Setting means.

  In one aspect of the arithmetic processing device of the present invention, generating means for generating the reference table based on the generation logic, and reference arithmetic means for performing an operation referring to the reference table based on the reference arithmetic logic, And the setting means performs reconfiguration so as to maintain at least one of the reference tables generated by the generation means before reconfiguration until after reconfiguration, and the reference operation logic is maintained until after reconfiguration. Logic that performs an operation with reference to at least one of the reference tables, and the generation logic is a new reference to the storage circuit that is different from the reference table that is maintained and referenced until after the reconfiguration. This is a logic for generating a table, and the generation means generates a new reference table in parallel with the calculation by the reference calculation means.

  In one aspect of the arithmetic processing apparatus of the present invention, the arithmetic circuit is constructed using a plurality of arithmetic elements arranged in a distributed manner capable of reconfiguring arithmetic logic specifications, and the storage circuit is data with the arithmetic element. The connection logic specification is constructed using a plurality of distributed storage elements that can be reconfigured, and the generation logic is a new reference table for the storage elements different from the reference table that is maintained until after the reconfiguration. Is the logic to generate

  In one aspect of the arithmetic processing apparatus of the present invention, the generation logic is logic for generating a new reference table in another storage element based on data stored in some of the storage elements.

  In one aspect of the arithmetic processing device of the present invention, the reconfigurable circuit includes an input / output line for performing high-speed input / output with the outside of the reconfigurable circuit, and the reference arithmetic logic is the input / output line. Is the logic to occupy and perform the operation.

  In one aspect of the arithmetic processing device of the present invention, the generation means starts generating a new reference table at the start or after the start of the calculation by the reference calculation means, and before or after the calculation by the reference calculation means is completed. Occasionally, the generation of a new reference table is terminated to generate a new reference table in parallel with the calculation by the reference calculation means.

  In one aspect of the arithmetic processing apparatus of the present invention, the reference operation logic is logic for performing an operation referring to the reference table for input image data, and the reference table is a free pixel of the image data. It has a size according to the degree or a size according to the number of pixels of the image data.

  In one aspect of the arithmetic processing program of the present invention, there is provided a reconfigurable circuit including an arithmetic circuit capable of reconfiguring arithmetic logic specifications, and a memory circuit capable of reconfiguring data connection logic specifications with the arithmetic circuits. A generating logic for reconstructing the operation logic specification and the connection logic specification and generating a reference table on the storage circuit, and a reference operation for performing an operation referring to the reference table on the operation circuit It functions as a setting means for setting logic.

  According to the first aspect of the present invention, since the reference table is generated more quickly than a mode in which the reference table is created by software processing, it is possible to shorten the execution time of the operation referring to the reference table. An arithmetic processing device is provided.

  According to the second aspect of the present invention, since the reference table is generated before reconfiguration, it is possible to quickly execute an operation referring to the reference table after reconfiguration.

  According to the third aspect of the present invention, the utilization factor of the calculation element and the storage element is increased, and as a result, the entire calculation time is shortened.

  According to the invention described in claim 4, it is possible to reduce the amount of communication with the outside of the reconfigurable circuit.

  According to the fifth aspect of the present invention, since the reference arithmetic logic can use the input / output line without competing with the connection logic, the input / output time is shortened.

  According to the invention described in claim 6, since the reference table is generated during the execution of the calculation, the entire calculation time can be shortened.

  According to the seventh aspect of the present invention, the efficiency of creating a relatively large reference table required for image processing can be increased.

  According to the eighth aspect of the present invention, since the reference table is generated more quickly than a mode in which the reference table is created by software processing, it is possible to shorten the execution time of the operation referring to the reference table. An arithmetic processing program is provided.

[Explanation of terms, etc.]
Here, terms and concepts used in the claims, the specification, or the drawings will be described.

  A reconfigurable circuit is also called a reconfigurable circuit, which is an arithmetic circuit such as an arithmetic logic unit (ALU) that mainly performs arithmetic processing and a memory such as a random access memory (RAM) that mainly stores data. Circuit. In the reconfigurable logic circuit, it is possible to change the logic specification defined by hardware into software (programmatic). In particular, when the logical specification can be switched within several clocks, dynamic reconfiguration for changing the logical specification is possible during a series of processes.

  The logical specifications to be switched include, for example, an arithmetic logic specification that defines the mode of arithmetic processing performed in the arithmetic circuit, a wiring logic specification that defines the wiring mode in the reconfigurable logic circuit, a reconfigurable logic circuit, and an external device And input / output logic specifications that define the manner of wiring. In the memory circuit, the internal logic specifications are typically fixed and the connection logic specifications or the input / output logic specifications are reconfigurable. For example, the internal logic specifications can be reconfigured. May be.

  A reconfigurable circuit typically includes a plurality of elements (elements) arranged in a distributed manner (for example, arranged in a two-dimensional array on a chip). Specifically, there are examples in which an arithmetic circuit is constructed by a plurality of arithmetic elements, and a memory circuit is constructed by a plurality of memory elements. In many cases, programming for reconstruction is performed in units of such arithmetic elements and storage elements.

  The setting means is means for reconfiguring the logic specification of the reconfigurable circuit so as to set predetermined generation logic and reference calculation logic for the calculation element. Here, the generation logic is logic for generating a reference table in the storage circuit, and the reference operation logic is logic for executing an operation referring to the reference table generated in the storage element on the operation circuit. The generation logic and the reference operation logic are set by changing, for example, the operation logic specification, the connection logic specification, the input / output logic specification, and the like.

  The reference table indicates a data group in which a data structure is set so that desired data can be referred (read). For lookup tables, search algorithms such as hashes and trees are often used. A typical example of the lookup table is a lookup table (LUT).

  The generation means is means for generating a reference table by inputting data to the storage circuit based on the generation logic. The input data may have been stored in an external storage device or processed from it, stored in a part of the storage circuit, or processed from it There may be. In the reference table, constant data whose value is fixed through a series of operations to be referred to may be input, or variable data whose values are rewritten in the course of the operation may be input.

  The reference operation means is means for executing an operation referring to the reference table generated by the generation means based on the reference operation logic. This calculation may involve input of data to be calculated or output of calculation result data.

  The arithmetic processing unit may include a reconfigurable circuit and a setting unit, and may further include a generation unit or a reference arithmetic unit. The reconfigurable circuit or the hardware that constitutes each means may be centrally arranged on a single board or in a single case, or may communicate with each other on multiple boards or in multiple cases. It may be distributed in a possible manner. In addition, some or all of the setting unit, the generation unit, and the reference calculation unit may be constructed using a reconfigurable circuit, or a non-reconfigurable circuit (a typical CPU is reconfigured). It may be constructed using (not configurable). The setting means, the generation means, and the reference calculation means are typically realized by controlling the operation of such computer hardware based on a computer program.

  Note that the timing at which the generation means generates the reference table and the timing at which the reference calculation means performs the calculation with reference to the reference table can be set variously. As an example, after the generation unit generates the reference table, a mode in which the reference calculation unit performs the calculation subsequently (without performing reconstruction) can be cited. As another example, in parallel with the generation unit generating a new reference table, the reference calculation unit performs an operation with reference to the reference table generated before reconstruction. Here, parallel means that at least a part of the execution process and at least a part of the generation process are performed at the same time zone.

[Embodiment]
Hereinafter, embodiments of the present invention will be exemplified.

  FIG. 1 is a schematic diagram illustrating a configuration example of an image processing apparatus 10 according to the present embodiment. The image processing apparatus 10 is a kind of arithmetic processing apparatus, and is configured as an apparatus having a single casing in the illustrated example. Inside the image processing apparatus 10, an internal bus 11 is provided as an internal communication path. The internal bus 11 includes a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 16, an HDD (Hard Disc Drive) 18, a reconfigurable system 20, a UI (User Interface) 21, a scanner 22, and a printer. 24, a CDD (Compact Disc Drive) 26, and a network interface 28 are connected to each other.

  The CPU 12 is a device that controls each component of the image processing apparatus 10 and performs image processing in accordance with a program stored in the ROM 14 or the like. The ROM 14 is a semiconductor memory (storage device) capable of long-term storage, and stores various programs and setting information. The RAM 16 is a semiconductor memory mainly used for short-term storage, and stores image data to be processed. In order to speed up the input / output between the RAM 16 and the reconfigurable system 20, there are cases in which both are directly connected without using the internal bus 11 or a DDR (double data rate) system is used. The HDD 18 is a large-capacity storage device configured using a magnetic disk or the like, and is used for long-term storage of image data.

  The reconfigurable system 20 is a device that includes a configuration memory 32 and a reconfigurable processor 34 and is typically installed on the same chip. The configuration memory 32 is a storage device to which logical specification data that defines the logical specification of the reconfigurable processor 34 is input. The configuration memory 32 is set such that, for example, a plurality of selectable logical specification data is switched by a switch, and the logical specification data to be adopted can be selected in several clocks (for example, one clock).

  The reconfigurable processor 34 is a device as a reconfigurable circuit, and includes a plurality of processor elements (PE) arranged in an array. The processor element is a small circuit constituting the reconfigurable processor 34, and includes, for example, an ALU element as an arithmetic element or a RAM element as a storage element. Among these, the ALU element is a small circuit that performs arithmetic processing on data based on the reconfigured logic specifications, and the RAM element is a small circuit that performs input / output and storage of data. The configuration memory 32 includes an arithmetic logic specification that is an internal logic specification of the ALU element, a connection logic specification that specifies connection with other ALU elements and RAM elements, an input / output logic specification that specifies connection with an external device, and the like. Is reconfigured based on the logical specification data set in The reconfigurable processor 34 is provided with a dedicated input / output I / F (interface) that performs high-speed input / output with an external device, a small arithmetic circuit with a fixed logical specification (non-reconfigurable), and the like. It is often done. The reconfigurable system 20 may include a control unit that controls selection of logical specification data, reconfiguration time, and the like in its own device to control its own operation, or may be operated by an external device such as the CPU 12. May be controlled. Such a control unit or CPU 12 inputs configuration data to the configuration memory 34 in accordance with a program, sets a configuration such as image processing logic in the reconfigurable processor 34, and executes it. The configuration data is stored in the ROM 14, the RAM 16, the HDD 18, and the like.

  The UI 21 includes a display device such as a liquid crystal display and a light emitting diode, and an input device such as a touch panel and a keyboard, and displays data to the user of the image processing apparatus 10 and receives an operation command from the user. The scanner 22 is a reading device that reads an image on a sheet surface and generates image data. The printer 24 is a printing device that performs printing on paper based on image data. The CDD 26 is a device that reads data recorded on a CD (compact disc) as a recording medium. For example, when a program for controlling the CPU 12 or the reconfigurable system 20 is provided by the CDD 26, the CDD 26 reads this program. Used for. The network interface 28 is an interface for inputting / outputting data by connecting to a network 30 such as the Internet. For example, when a program for controlling the CPU 12 or the reconfigurable system 20 is provided through the network 30, Used to receive program data signals.

  Here, the structure of the reconfigurable system 20 will be briefly described with reference to FIGS. FIG. 2 is a schematic diagram for explaining the ALU element. In this example, the configuration memory 32 stores setting data A and setting data B as configuration data, and a SEL (selection circuit) 40 for selecting one of these is provided. Further, the reconfigurable processor 34 is provided with an ALU 42 that constitutes an ALU element, and its arithmetic logic specification is reconfigured based on the selection of the SEL 40. Typically, the ALU 42 inputs two data of input data A and input data B, performs arithmetic processing according to arithmetic logic specifications, and outputs output data. Of course, depending on the setting, various types of arithmetic processing such as arithmetic processing with reference to the RAM element can be performed.

  FIG. 3 is a schematic diagram for explaining a RAM 44 as a RAM element provided in the reconfigurable processor 34. The RAM 44 receives an R / W (Read / Write) control signal for controlling reading or writing of data and an ADR (address) signal for controlling a reading or writing position. I / O is performed. A mechanism for reconfiguring internal logic specifications is not provided for the RAM 44. However, in general, the wiring logic specification or input / output logic specification that determines the input / output destination of the R / W control signal, ADR signal, data, etc. is reconfigured, or the data stored in the RAM 44 when the ALU element is reconfigured. It is possible to erase all at once.

[First embodiment]
Next, a 1st form is demonstrated with reference to FIG. 4 and FIG. Here, the description will be made on the assumption of the hardware configuration shown in FIGS.

  FIG. 4 is a diagram for explaining an example of logic set in the reconfigurable processor 34. In the image processing apparatus 10, the reconfigurable processor 34 is used for image processing such as color conversion processing, luminance conversion processing, compression / expansion processing, and filter processing. In this image processing, high-speed processing is performed using an image processing LUT such as a color conversion LUT or a luminance conversion LUT.

  In the example of FIG. 4, a part or all of the LUT data 50 stored in the RAM 16 is transmitted to the reconfigurable processor 34 to indicate a logic for generating the LUT. Specifically, the reconfigurable processor 34 includes a DDR (double data rate) interface 52 and RAMs 53 and 54 that are two RAM elements. Further, the address counter generator 58 and the write enable signal generator 60 are constructed by changing the logical specifications of a plurality of ALU elements.

  The DDR interface 52 is connected to an input / output signal line 62 that is an input / output line using the DDR system, and inputs the LUT data 50 from the RAM 16 via the input / output signal line 62. The LUT data 50 input to the DDR interface 52 is sent to the RAMs 53 and 54 through the data signal line 64 and also sent to the address counter generator 58 and the write permission signal generator 60. The address counter generator 58 increments the value every time there is a data input notification from the input notification line 65 to generate an address data signal for the RAMs 53 and 54. The address counter generator 58 transmits the generated address signal to the RAM 53 and the RAM 54 through the address signal line 66. Further, the write permission signal generation unit 60 generates an R / W signal that controls whether the data input to the DDR interface 52 is written to the RAM 53 or the RAM 54. The R / W signal for the RAM 53 is transmitted through a WE (Write Enable) 1 signal line 68, and the R / W signal for the RAM 54 is transmitted through a WE 2 signal line 70.

  Next, the operation in the reconfigurable processor 34 will be described. When the control unit sets the logic shown in FIG. 4 by reconfiguration, the control unit sequentially outputs data necessary for creating the LUT from the LUT data 50. The output data is input to the DDR interface 52 through the input / output signal line 62 and further input to the RAMs 53 and 54 through the data signal line 64. At this time, the address counter generation unit 58 generates an address signal indicating the storage position of each data, and outputs it to the RAMs 53 and 54 through the address signal line 66. Further, according to the setting, the write permission signal generation unit 60 determines which of the RAMs 53 and 54 to input the read LUT data 50, and outputs the R / W signal based on the determination result to the WE1 signal line 68 and the WE2 signal line. 70 to the RAM 53, 54. Typically, when writing to the RAM 53, writing to the RAM 54 is prohibited, and when writing to the RAM 54 is performed, writing to the RAM 53 is prohibited. Then, LUTs corresponding to the input LUT data 50 are generated in the RAMs 53 and 54, respectively.

  When the LUT is generated in the RAMs 53 and 54, the reconfigurable processor 34 executes image processing with reference to the LUT. The logic for performing image processing may be set at the same time when the setting shown in FIG. 4 is performed, or may be set by performing reconfiguration without destroying the LUT after generating the LUT. Further, the image data to be processed may be input / output through the input / output signal line 62 used for inputting the LUT data 50, or may be input / output through another line.

  FIG. 5 is a schematic diagram for explaining the processing time. Here, processing of LUT-1a and LUT-1b that generate two LUTs, image processing 1 that refers to the generated LUT, processing of LUT-2a and LUT-2b that newly generate two LUTs, and Image processing 2 with reference to the newly generated LUT is sequentially performed. FIG. 5A shows a case where the LUT data 50 is generated by software, and FIG. 5B shows the case where the LUT data 50 is generated by hardware (that is, in the mode shown in FIG. 4). Shows when to do. In FIG. 5A, about 1 μs per data (256 μs for a 256-data LUT) is required, and after the LUT is generated by software, image processing is performed by hardware. Assumed. Therefore, for example, the time required to generate an LUT of 256 data 100 times in a series of processing is 25.6 ms. On the other hand, in the example of FIG. 5B, about 1 ns per data (256 ns for a 256-data LUT) is required, and the LUT is generated by hardware. Subsequently, image processing is performed by hardware. It is assumed that it is done. Therefore, the time required for generating 256 LUTs 100 times is 25.6 μs. As described above, due to the difference between the software LUT generation time and the hardware LUT generation time, the time required for the entire processing is large in FIGS. 5A and 5B. Is different. Here, the time required for the reconfiguration of the reconfigurable processor 34 is not particularly considered, but if the reconfiguration is performed with several clocks (several ns), the influence on the example of FIG. 5 is considered to be small. It is done.

[Second form]
Next, a 2nd form is demonstrated using FIGS. 6-9. Similar to the first embodiment, the second embodiment is based on the hardware configuration shown in FIGS.

  FIG. 6 is a diagram corresponding to FIG. 4, and the elements corresponding to FIG. 6 shows the RAM 16 and the reconfigurable processor 34 as in FIG. However, the RAM 16 stores image data 80 in addition to the LUT data 50, and two input / output signal lines 82 and 84 using the DDR system are connected from the RAM 16 to the DDR interface 52. Yes. The reconfigurable processor 34 is provided with RAMs 53 and 54 as in the example of FIG. 4, and further includes a data signal line 64, an input notification line 65, an address counter generator 58, a write permission signal generator 60, An address signal line 66, a WE1 signal line 68, and a WE2 signal line 70 are set. Further, the reconfigurable processor 34 is provided with a RAM 92. The LUT 100 is generated before the reconfiguration, and the image preprocessing unit 90 and the image postprocessing unit 94 are generated by reconfiguring the ALU element. ing. The RAM 92 is connected with an address signal line 96 and a data signal line 98 from the image preprocessing unit 90, and the data of the LUT 100 is referred to based on the image processing result of the image preprocessing unit 90. Yes. The image post-processing unit 94 further performs image processing based on the result of referring to the data of the LUT 100.

  Next, the logic execution process shown in FIG. 6 will be described. First, before reconfiguration, the logic for inputting the LUT data 50 to the RAM 92 is set, and the LUT 100 is generated in the RAM 92 by executing this logic. Then, reconfiguration is performed without destroying the data of the LUT 100, and the logic shown in FIG. 6 is set. After reconfiguration, the LUT data 50 is input to the DDR interface 52 through the input / output signal line 84, and LUTs are generated in the RAMs 53 and 54 in the same manner as the example shown in FIG. In parallel with the generation of the LUT, the image data 80 is input from the RAM 16 to the DDR interface 52 through the input signal line 82. The image preprocessing unit 90 performs preprocessing on the image data 80, and determines a reference destination (address) in the LUT 100 based on the result. Then, the image post-processing unit 94 performs post-processing based on the reference result of the LUT 100, and outputs the processing result to the RAM 16 or the like. Through this pre-processing and post-processing, image processing with reference to the LUT data 100 is performed on the input image data 80.

  The next reconfiguration is performed so as not to destroy the LUT generated in the RAMs 53 and 54. Then, by reconfiguration, logic for performing image processing with reference to this LUT and logic for generating a new LUT used in subsequent image processing are set.

  Here, an example in which reconstruction is performed sequentially will be described with reference to FIGS. FIG. 7 is a diagram illustrating an example in which logic is sequentially set for the reconfigurable processor 34 and corresponding processing is executed. In the example of FIG. 7A, the reconfigurable processor 34 is provided with a processing 1A unit 110 and a processing 1B unit 114 using an ALU element, and an LUT 118 stored in the RAM 112. Further, the address signal line 122 and the data signal line 124 are set so that the LUT 118 can be referred to based on the image processing result by the processing 1A unit 110. Here, the LUT 118 is generated before the reconfiguration and maintained (not destroyed) until after the reconfiguration, and the processing 1A unit 110, the processing 1B unit 114, the address signal line 122, the data signal line 124, and the like. Are newly set logically. Further, in the reconfigurable processor 34, the address signal line 132 and the data signal line 134 are wired to the RAM 130, and the logic for generating the LUT 136 is set. When the logic shown in FIG. 7A is set, in the reconfigurable processor 34, the image processing referring to the LUT 118 by the processing 1A unit 110 and the processing 1B unit 114 and the generation processing of the LUT 136 for the RAM 130 are performed in parallel. To be done.

  FIG. 7B shows the logic set by reconfiguration after the process based on the logic shown in FIG. 7A is executed. Here, the logic for setting the address signal line 138 and the data signal line 140 to the RAM 112 and generating a new LUT 142 is set. In addition, the LUT 136 generated before reconfiguration is maintained in the RAM 130. Further, the processing 2A unit 144 and the processing 2B unit 146 are set using the ALU element, and the address signal line 152 and the data signal line are set so that the LUT 136 can be referred to based on the processing result of the processing 2A unit 144. 154 is wired. When the logic shown in FIG. 7B is set, processing for generating a new LUT 142 in the RAM 112 and image processing performed by the processing 2A unit 144 and the processing 2B unit 146 with reference to the LUT 136 are executed in parallel. Is done.

  Next, with reference to FIGS. 8 and 9, a mode in which image processing is specifically performed under the configuration described in FIGS. 6 and 7 will be described.

  FIG. 8 is a diagram schematically showing image data 160 to be subjected to image processing. Here, it is assumed that the image data 160 is data in which pixels are two-dimensionally arranged, and 2000 lines of 4000 pixels extending in the horizontal direction are arranged in the vertical direction. It is assumed that the image data 160 cannot be processed at a time due to restrictions on the number and capacity of RAM elements in the reconfigurable processor 34. Therefore, image processing is performed by dividing the image data 160 into 20 lines with 100 lines as one band.

  FIG. 9 is a flowchart showing overall control of image processing for the image data 160. When image processing is started, first, a control variable n representing the number of bands is set to 0 (S10). This n is incremented by 1 every time the band changes (S12), and when it exceeds 20 (S14), the process is terminated. On the other hand, when n is 20 or less, image processing 1 to 5 (S18, S22, S26, S30, S34) is sequentially executed for each band. From an algorithm point of view, the image processing 1 to 5 should be pipelined on the reconfigurable processor 34. However, since the performance of the ALU elements and the number and capacity of the RAM elements are not sufficient, the image processes 1 to 5 are sequentially reconfigured on the reconfigurable processor 34 here. Specifically, image processing 2 is performed on data output as a result of image processing 1, and image processing 3 is performed on data output as a result of image processing 2. Are output in the subsequent image processing. Prior to the execution of the image processes 1 to 5, reconstructions 1 to 5 (S16, S20, S24, S28, and S32) for setting logic for performing the image process are performed. In the repetition process of the reconstruction and the image processing, as described with reference to FIG. 7, an LUT used in the subsequent image processing is generated during the execution of the preceding image processing. Is preserved. For example, in parallel with execution of image processing 5 (S34), an LUT used in image processing 1 is generated, and reconstruction 1 (S16) is performed so that the LUT is not destroyed.

  Note that a new LUT is usually generated using RAM elements that are not used after reconfiguration. When a previously used LUT is stored in this RAM element, a new LUT is generated without maintaining this LUT. However, if there is a surplus in the number and capacity of RAM elements, the LUT that is reused after multiple reconfigurations may be maintained until that time.

  FIG. 10 is a schematic diagram for explaining the processing time of the processing shown in FIG. Here, as in the example shown in FIG. 5, the processing of LUT-1a and LUT-1b that generate two LUTs, the image processing 1 that refers to the generated LUT, and the LUT- that generates two new LUTs It is assumed that the processing 2a and LUT-2b and the image processing 2 referring to the newly generated LUT are sequentially performed. FIG. 10A is a diagram corresponding to FIG. 5B, and illustrates an aspect in which LUT generation and image processing are performed in a non-parallel manner. On the other hand, in FIG. 10B, as described with reference to FIG. 9, LUT generation and image processing are executed in parallel. Specifically, the LUT-2a and LUT-2b for generating the LUT used in the image processing 2 are performed in parallel with the execution of the image processing 1, and the image processing 3 is performed in parallel with the execution of the image processing 2. Processing of LUT-3a and LUT-3b for generating the LUT used in FIG. As a result, in the example of FIG. 10B, the total required time is shortened by the time required to generate the LUT, compared to the example of FIG.

[Third embodiment]
Finally, the third embodiment will be described with reference to FIG. The third mode is based on the hardware configuration shown in FIGS. 1 to 3 as in the first mode and the second mode.

  FIG. 11 is a diagram corresponding to FIG. 6, and the elements corresponding to FIG. In FIG. 11, image data 80 is stored in the RAM 16. A plurality of input / output signal lines 170, 172, 174, and 176 using the DDR method are connected from the RAM 16 to the DDR interface 52. The image pre-processing unit 90 and the image post-processing unit 94 perform image processing with reference to the LUT 100 on the image data input to the DDR interface 52, as in the example of FIG. Further, the reconfigurable processor 34 is provided with RAMs 53 and 54, and the LUT is generated using the address counter generator 58 and the write permission signal generator 60 as in the example of FIG. . However, the example of FIG. 11 is different from the example of FIG. 6 in that the read address counter 180 is generated using the ALU element and the shared LUT data 184 is stored in the RAM 182. That is, in the example of FIG. 11, data is read from the shared LUT data 184 of the RAM 182 according to the address signal output from the read address counter 180 and output to the RAMs 53 and 54.

  The shared LUT data 184 is set so that the value is not destroyed even by reconfiguration. It is also used when the LUT 100 is generated in the RAM 92 or when the LUT is generated in the other RAM 190, 192, 194. If the RAM 182 does not have enough capacity to store the shared LUT data 184, the RAM 182 may store the shared LUT data 184 in a plurality of RAMs.

It is a figure which shows the hardware structural example of the image processing apparatus concerning this Embodiment. It is a figure explaining the structural example of an ALU element. It is a figure explaining the structural example of a RAM element. It is a figure explaining the example of the logic to set. It is a figure explaining processing time typically. It is a figure explaining the modification of the logic to set. It is a figure explaining the example which reconfigure | reconstructs a logical specification. It is the figure which showed typically the image data used as a process target. 6 is a flowchart illustrating an example of overall control of image processing. It is a figure explaining processing time typically. It is a figure explaining another modification of the logic to set.

Explanation of symbols

  10 image processing apparatus, 11 internal bus, 12 CPU, 14 ROM, 16, 44, 53, 54, 92 RAM, 18 HDD, 20 reconfigurable system, 22 scanner, 24 printer, 28 network interface, 30 network, 32 config Memory, 34 Reconfigurable processor, 40 SEL, 42 ALU, 50 LUT data, 52 DDR interface, 58 Address counter generator, 60 Write permission signal generator, 80 image data, 90 image preprocessor, 94 Image postprocessor , 100 LUT.

Claims (7)

An arithmetic circuit capable of reconfiguring arithmetic logic specifications, and a reconfigurable circuit comprising a storage circuit capable of reconfiguring data connection logic specifications with the arithmetic circuit;
The operation logic specification and the connection logic specification are reconfigured, and a generation logic for generating a reference table on the storage circuit and a reference operation logic for performing an operation referring to the reference table on the operation circuit are set. Setting means;
Equipped with a,
The reference operation logic is a logic for performing an operation referring to the reference table for input image data,
The arithmetic processing apparatus , wherein the reference table has a size corresponding to the number of pixels of the image data . The arithmetic processing device according to claim 1,
Generating means for generating the lookup table based on the generation logic;
Reference operation means for performing an operation referring to the reference table based on the reference operation logic;
With
The setting means performs reconfiguration so as to maintain at least one of the reference tables generated by the generation means before reconfiguration until after reconfiguration,
The reference operation logic is logic that performs an operation with reference to at least one of the reference tables maintained until after reconfiguration,
The generation logic is a logic for generating a new reference table in a part different from the reference table that is maintained and referenced until after the reconfiguration for the storage circuit,
The calculation processing device is characterized in that the generation means generates a new reference table in parallel with the calculation by the reference calculation means. In the arithmetic processing unit according to claim 2,
The arithmetic circuit is constructed using a plurality of distributed arithmetic elements that can reconfigure the arithmetic logic specification,
The storage circuit is constructed using a plurality of distributed storage elements capable of reconfiguring data connection logic specifications with the arithmetic elements,
The arithmetic processing apparatus, wherein the generation logic is a logic for generating a new reference table for the storage element different from the reference table maintained until after reconfiguration. In the arithmetic processing unit according to claim 3,
The arithmetic processing apparatus, wherein the generation logic is logic for generating a new reference table in another storage element based on data stored in a part of the storage elements. In the arithmetic processing unit according to claim 4,
The reconfigurable circuit has an input / output line for performing high-speed input / output relative to the outside of the reconfigurable circuit,
The arithmetic processing device according to claim 1, wherein the reference arithmetic logic is a logic for performing an operation while occupying the input / output line. In the arithmetic processing unit according to claim 2,
The generation means starts generating a new reference table at or after the start of calculation by the reference calculation means, and ends generation of a new reference table before or at the end of the calculation by the reference calculation means. A new reference table is generated in parallel with the calculation by the reference calculation means. A computer including a reconfigurable circuit having an arithmetic circuit capable of reconfiguring arithmetic logic specifications, and a storage circuit capable of reconfiguring data connection logic specifications with the arithmetic circuit,
The operation logic specification and the connection logic specification are reconfigured, and a generation logic for generating a reference table on the storage circuit and a reference operation logic for performing an operation referring to the reference table on the operation circuit are set. an arithmetic processing program Ru to function as a setting unit,
The reference operation logic is a logic for performing an operation referring to the reference table for input image data,
The arithmetic processing program, wherein the reference table has a size corresponding to the number of pixels of the image data.

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