JP2008129851A - Processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the processing time and power are consumed by an instruction fetch operation from a processor and an influence of this consumption is remarkable especially in the case that a program is mounted on a memory of a chip other than a chip having the processor mounted thereon. <P>SOLUTION: An instruction of a central processing unit 105 is made extensible per operation. With respect to the extended instruction, a series of procedures to be frequently executed at this time are collected in a procedure processing holding buffer memory 114, and a plurality of desired processing steps can be executed by one instruction fetch operation under the control of an extended instruction control block. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device capable of optimizing arithmetic processing contents, and more particularly to an arithmetic processing device effective as an embedded device for portable devices.

According to a certain prior art, it is possible to easily develop a program for numerical calculation processing executed by the DSP while making use of the calculation processing performance of the DSP (see Patent Document 1).
Japanese Patent Laid-Open No. 2-67602

  In an embedded system, the central processing unit executes a program to perform calculation and control of the system. In order to execute a program, the central processing unit needs to read an instruction that is an element constituting the program by performing a fetch operation from a memory such as a flash memory.

  Normally, the central processing unit and a memory such as a flash memory are not accessed on the same semiconductor chip, and thus are accessed through an external IO. Access via an external IO is slower and consumes more power than access within the same semiconductor chip due to differences in voltage and capacitance.

  Moreover, the central processing unit is general-purpose and is rarely optimized for each embedded system. Therefore, in each embedded system, a plurality of general-purpose instructions included in the central processing unit are combined to execute a desired process.

  According to the present invention, the central processing unit has a memory for defining the contents of an instruction, defines a new instruction, and executes a new instruction once defined, thereby combining a plurality of existing instructions. A series of processes can be performed.

  Also, calculation contents are defined, and calculation processing contents can be newly defined using calculation processing resources provided in the central processing unit.

  According to the present invention, since a series of processing can be performed by newly defining an instruction and executing one instruction, the number of instruction fetches can be reduced, execution speed can be improved, and power consumption can be reduced. .

  In addition, by using the processing resources provided in the central processing unit and defining instructions suitable for each embedded system, the desired processing is executed without combining existing instructions, so the number of instruction fetches is reduced. In addition, the execution speed can be improved and the power consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< First Embodiment >>
FIG. 1 shows an audio / video processing system to which a system LSI including a central processing unit to which the present invention is applied is applied. This system is a video playback device that includes a system LSI 101, a flash memory 102, a monitor 103, and a speaker 104, and plays back video data with audio that has been written in the flash memory 102 in advance.

  In the flash memory 102, a series of procedures of a program that is a set of instructions executed by the central processing unit 105 housed in the system LSI 101, video data with audio, and an extended instruction control block 113 used in the present invention. Definition of and is included.

  The speaker 104 converts the electrical signal output from the system LSI 101 into sound. The monitor 103 converts the electrical signal output from the system LSI 101 into a video.

  Note that since the flash memory 102 is connected to the outside of the system LSI 101, it consumes more time and power for access than in the system LSI 101.

  The system LSI 101 includes an audio processing device 11, a video processing device 10, and a central processing unit 105 to which the present invention is applied. The voice processing device 11 converts the voice data into a voice signal that can be reproduced by the speaker 104 in accordance with an instruction from the central processing unit 105. The video processing device 10 converts the video data into a video signal that can be displayed on the monitor 103 in accordance with an instruction from the central processing unit 105.

  The central processing unit 105 includes an instruction read block 106, an instruction determination block 107, an instruction execution block 108, a register write block 109, a register load / store block 110, a bus interface block 111, a register block 112, an extended instruction control block 113, a procedure process. It comprises a holding buffer memory 114.

  The instruction read block 106 plays a role of reading instructions necessary for the central processing unit 105 to operate. Further, it further has a role of transferring the instruction transferred from the extended instruction control block 113 to the next instruction determination block 107.

  The instruction determination block 107 is responsible for determining the type of instruction and transmitting the processing contents to be performed to the instruction execution block 108. The instruction determination block 107 further has a function of requesting the extension instruction control block 113 to execute when it is determined as a predefined extension instruction.

  The instruction execution block 108 plays a role of executing the processing contents instructed by the instruction determination block 107.

  The register write block 109 has a function of writing the processing contents executed by the instruction execution block 108 to the register in the register block 112. The register write block 109 can also write a value to a setting register existing in the extension instruction control block 113. This setting register will be described later with reference to another drawing. Further, it is possible to write to the procedure processing holding buffer memory 114 through the register writing block 109.

  The register load / store block 110 has a function of reading and writing data between a memory space existing outside the central processing unit 105 and a register inside the central processing unit 105.

  The bus interface block 111 has an interface function with the outside of the central processing unit 105.

  The register block 112 has a temporary data storage function necessary for processing executed by the central processing unit 105.

  The extended instruction control block 113 has a function of determining the extended instruction requested by the instruction determining block 107 and sequentially transferring a plurality of instructions recorded in the procedure processing holding buffer memory 114 to the instruction reading block 106.

  The procedure processing holding buffer memory 114 has a function of holding a desired series of procedures and outputting them in order in response to a request from the extended instruction control block 113. Further, a series of procedures can be combined into one combination, and a plurality of procedures can be registered separately. The procedure processing holding buffer memory 114 is readable / writable by a program executed by the central processing unit 105, and by executing a certain instruction provided in advance by the central processing unit 105, the procedure processing holding buffer memory 114 can be read in advance. It is possible to read out a series of procedures from the area defined in (1) and write them in the procedure processing holding buffer memory 114. Further, when an interrupt is issued from the audio processing device 11 or the video processing device 10 to the central processing unit 105, the procedure processing holding buffer memory 114 stores an appropriate content in accordance with the interrupt issued by the extended instruction control block 113. Read from 102 predefined areas.

  FIG. 2 is a diagram showing the structure of the register block 112. The register block 112 of this embodiment has eight recording areas. Each recording area is named a, b, c, d, e, f, g, h, and can be specified by designating the name. In addition, each recording area can always be read out.

  FIG. 3 shows instructions necessary for explaining the present invention in the instruction set applied in this embodiment. Next, the contents of each line will be described.

  The contents shown in the first line relate to the operation instruction. It is possible to select one of the arbitrary recording areas of the register block 112 illustrated in FIG. 2 and select REG1, REG2, and REG3, and perform addition, subtraction, and multiplication. REG1, REG2, and REG3 can be specified in any of the eight recording areas shown in FIG. 2, and any of a, b, c, d, e, f, g, and h is applied by an instruction. . That is, in the case of the instruction a + b => c, the result of addition of the recording area a and the recording area b is written in the recording area c.

  The contents shown in the second line relate to the store instruction. 2. Select one of the arbitrary recording areas of the register block 112 shown in FIG. 2, select REG1 and REG2, and the contents of any of the eight recording areas shown in FIG. Is stored in the memory area indicated by the address stored in one of the eight recording areas shown in FIG. 2 designated by REG2.

  The contents shown in the third line relate to the load instruction. REG1 and REG2 are selected by selecting one of the arbitrary recording areas of the register block 112 shown in FIG. 2, and stored in one of the eight recording areas shown in FIG. 2 designated by REG1. The data at the specified address is loaded into one of the eight recording areas shown in FIG. 2 designated by REG2.

  The contents shown in the fourth line relate to the 0 write instruction. This instruction is similar in behavior to the store instruction, except that the value to be written is a fixed value of 0. That is, one of the arbitrary recording areas of the register block 112 shown in FIG. 2 is selected and REG1 is selected, and stored in one of the eight recording areas shown in FIG. 2 designated by REG1. 0 is written to the current address.

  FIG. 4 shows the contents of the procedure processing holding buffer memory 114 in this embodiment. In the present embodiment, two extension instructions can be defined in the procedure processing holding buffer memory 114. In FIG. 4, as the extended instruction EXT_1, a series of procedures for first executing b * c => b, then a + b => b, and finally b-d => a is defined. Further, as the extended instruction EXT_2, a series of procedures for executing a + a => a first, then a + b => a, and finally a + c => a is defined.

  When the EXT_1 instruction is executed, the instructions are executed in the order defined in the procedure processing holding buffer memory 114, and as a result, the result of (a + (b * c))-d is substituted for a. Similarly, when the EXT_2 instruction is executed, the result of a + a + b + c is assigned to a. Thus, a complicated process that cannot be normally performed by a single instruction is executed by executing the extension instruction once.

  The contents of the procedure processing holding buffer memory 114 can be written by the central processing unit 105.

  FIG. 5 shows the internal structure of the extended instruction control block 113. The extension instruction control block 113 includes an interrupt signal control block 201, an audio processing extension instruction control block 202, a video processing extension instruction control block 203, an extension instruction management block 204, and an extension instruction decode block 205.

  The audio processing extended instruction control block 202 and the video processing extended instruction control block 203 are provided with a setting register. This setting register is a setting register that will be described later in the description of FIG.

  The voice processing extended instruction control block 202 includes a setting register for recording the start address of the address where the contents of the extended instruction desired to be used when an interrupt from the voice processing device 11 occurs. In this embodiment, since two extension instructions are supported, two head addresses are provided.

  In the video processing extension instruction control block 203, as in the case of the audio processing extension instruction control block 202, the head address of the address where the contents of the extension instruction desired to be used when an interrupt from the video processing apparatus 10 occurs is recorded. A setting register is provided, and the same operation as the voice processing extended instruction control block 202 is performed.

  The extension instruction decode block 205 notifies the extension instruction management block 204 when the extension instruction EXT_1 or EXT_2 is issued.

  When the extended instruction is issued, the extended instruction management block 204 reads the instruction from the procedure processing holding buffer memory 114 and sends it to the instruction read block 106.

  Two interrupt signals are connected to the interrupt signal control block 201, one each from the audio processing device 11 and the video processing device 10, and the interrupt signal control block 201 indicates what interrupt factor has occurred. , Notify the extended command management block 204.

  When notified of an interrupt, the extended instruction management block 204 issues a DEFINE_EXT1 instruction or a DEFINE_EXT2 instruction, which will be described later with reference to FIG.

  FIG. 6 is an instruction for defining an extended instruction included in the central processing unit 105 of this embodiment. The DEFINE_EXT1 instruction and the DEFINE_EXT2 instruction exist, and a setting register provided in the audio processing extension instruction control block 202 or the video processing extension instruction control block 203 included in the extension instruction control block 113 can be designated as TARGET.

  For example, when DEFINE_EXT1 is executed, the definition of the EXT1 instruction is read in order from the address specified as TARGET, and the extension instruction EXT1 is defined. As a result, it is possible to define an extended instruction with a single instruction. DEFINE_EXT2 is the same as DEFINE_EXT1 except that the extension instruction EXT2 is targeted.

  The operation of the arithmetic processing unit configured as described above will be described with reference to an example from startup by turning on the power to video playback.

  First, the central processing unit 105 reads a startup program from the flash memory 102 when the power is turned on. In the activation program, the audio processing device 11 and the video processing device 10 and the central processing unit 105 are initialized, and further, the instructions shown in FIG. When image processing is performed on a startup image displayed immediately after the power is turned on, it is possible to perform image processing with fewer commands using this extension command.

  When the start program is completed, the central processing unit 105 reads the video data, writes the video data and audio data included in the video data to the video processing device 10 and the audio processing device 11, respectively, and plays back the video. Video data is information-compressed by a certain algorithm, and information decompression processing is required for reproduction.

  Video data has a packet structure defined by a predetermined standard, and is formed as an aggregate of a large number of packets. The packet includes a header and video data or audio data. In the header, information necessary for decompressing information of video data or audio data is described.

  At this time, the video processing device 10 and the audio processing device 11 notify the central processing unit 105 of an interrupt when they complete certain processes. The central processing unit 105 determines which device the interrupt is from, and executes processing according to the factor that generated the interrupt.

  If the video processing device 10 generates an interrupt, the central processing unit 105 needs to write the header of the next packet to the video processing device 10. At that time, it is convenient if there are an instruction for performing a load process three times from the flash memory 102 to the central processing unit 105 and an instruction for storing the central processing unit 105 in the video processing unit 10 three times by one instruction. This is preferable because writing of a header of a packet for 3 words is completed with two instructions. Therefore, for the extension instruction control block 113, the video processing extension instruction control block 203 in the extension instruction control block 113 includes the addresses where the extension instruction to be loaded three times and the extension instruction to be stored three times are stored in the flash memory 102. The extension instruction is automatically switched when an interrupt signal from the video processing apparatus 10 is notified.

  Similarly, an appropriate extension instruction can be defined for an interrupt from the voice processing device 11.

  With this configuration, desired processing can be executed with a small number of instructions, so that the number of accesses to the flash memory 102 is reduced, and processing can be executed at higher speed with less power consumption. In addition, since the number of instructions can be reduced, the program size in the flash memory 102 can be reduced.

<< Second Embodiment >>
FIG. 7 shows an audio / video processing system to which a system LSI including a central processing unit to which the present invention is applied is applied. This system is a video playback device that includes a system LSI 101, a flash memory 102, a monitor 103, and a speaker 104, and plays back video data with audio that has been written in the flash memory 102 in advance.

  This embodiment is different from the first embodiment in that the internal structure of the extended instruction control block 113 and the instruction execution block 108 is provided with an operation processing content definition memory 115 instead of the procedure processing holding buffer memory 114.

  The arithmetic processing content definition memory 115 is readable and writable by a program executed by the central processing unit 105, and is a pre-defined area of the flash memory 102 by executing a certain instruction that the central processing unit 105 has in advance. It is possible to read a series of procedures from and write them into the arithmetic processing content definition memory 115.

  FIG. 8 shows the internal structure of the instruction execution block 108. The instruction execution block 108 includes a pre-stage connection switch 301, a post-stage connection switch 302, a divider 303, a multiplier 304, a shifter 305, an ALU 306, and a connection decoding device 307.

  The pre-stage connection switch 301 connects the processing target data output from the register or selector to an execution unit group such as the ALU 306 existing in the next stage as instructed by the connection decoding device 307.

  The rear connection switch 302 selects the output from the output of all execution units such as the ALU 306 existing in the previous stage to the register write block 109, the one to return to the front connection switch 301 again, or the one not to output to any of them. And connect as instructed from the connection decoding device 307.

  The divider 303 is an execution unit that performs division. The multiplier 304 is an execution unit that performs multiplication. The shifter 305 is an execution unit that performs a shift operation. The ALU 306 is an execution unit responsible for functions related to execution of the central processing unit 105 excluding division, multiplication, and shift operations.

  The connection decoding device 307 decodes the instruction issuance from the instruction determination block 107 and the extended instruction control block 113 and determines the connection of the front connection switch 301 and the rear connection switch 302. Therefore, the order of passing through each execution unit can be freely defined. That is, it is possible to construct an optimal instruction by combining execution units.

  The extended instruction control block 113 in this embodiment will be described with reference to FIG. The difference from the first embodiment shown in FIG. 5 is that not the procedure processing holding buffer memory 114 but the arithmetic processing content definition memory 115 is connected. Further, the extension instruction does not define a series of procedures but is connection information in the instruction execution block 108, and the connection information is supplied to the instruction execution block 108 when the extension instruction is executed. Except for these points, behaviors such as processing at the time of interruption are the same as in the first embodiment.

  By configuring as described above, it is possible to optimize instructions according to the processing desired to be executed, and higher processing capability can be realized. In addition, since a plurality of arithmetic processes can be performed together, a desired process can be performed with fewer instructions. In addition, the number of accesses to the flash memory 102 is reduced, and processing can be performed at higher speed with less power consumption. In addition, since the number of instructions can be reduced, the program size in the flash memory 102 can be reduced.

<< Third Embodiment >>
FIG. 10 shows an audio / video processing system to which a system LSI including a central processing unit to which the present invention is applied is applied. This system is a video playback device that includes a system LSI 101, a flash memory 102, a monitor 103, and a speaker 104, and plays back video data with audio that has been written in the flash memory 102 in advance.

  The feature of this system is a combination of the first embodiment and the second embodiment. That is, FIG. 10 further includes an arithmetic processing content definition memory 115 in addition to the configuration of FIG. 1 as the first embodiment.

  In the present embodiment, the extension instruction used in the first embodiment and the extension instruction used in the second embodiment can be defined.

  The extension instructions used in the first embodiment are defined as EXT_1 and EXT_2, and the extension instructions used in the second embodiment are defined as EXT_a and EXT_b in this embodiment. That is, the extension instructions that call a series of procedures are EXT_1 and EXT_2, and the extension instructions that define the execution contents of the instruction execution block 108 are EXT_a and EXT_b.

  The definition contents of EXT_1 and EXT_2 are stored in the procedure processing holding buffer memory 114, and the definition contents of EXT_a and EXT_b are stored in the arithmetic processing content definition memory 115. Execution of EXT_a or EXT_b can be included in a series of procedures defined in EXT_1 and EXT_2.

  Therefore, since the desired processing can be executed with a smaller number of instructions than the contents described in the first and second embodiments, the number of accesses to the flash memory 102 is further reduced, and the speed can be increased with less power consumption. Processing can be executed.

  As described above, the present invention is suitable for a system or system LSI equipped with a processor, and is particularly suitable for a portable electronic device.

1 is a block diagram of an audio / video processing system according to a first embodiment of the present invention. It is a schematic diagram of the register block in FIG. It is a figure which shows the command set in the image sound processing system of FIG. FIG. 2 is a schematic diagram of a procedure processing holding buffer memory in FIG. 1. It is a block diagram which shows the internal structure of the extended instruction control block in FIG. It is a figure which shows the extension command definition command in the image audio | voice processing system of FIG. It is a block diagram of the image audio processing system in the 2nd Embodiment of this invention. It is a block diagram which shows the internal structure of the instruction execution block in FIG. FIG. 8 is a block diagram showing an internal structure of an extended instruction control block in FIG. 7. It is a block diagram of the image audio processing system in the 3rd Embodiment of this invention.

Explanation of symbols

10 video processing apparatus 11 audio processing apparatus 101 system LSI
102 flash memory 103 monitor 104 speaker 105 central processing unit 106 instruction read block 107 instruction determination block 108 instruction execution block 109 register write block 110 register load store block 111 bus interface block 112 register block 113 extended instruction control block 114 procedure processing holding buffer Memory 115 Calculation processing definition memory 201 Interrupt signal control block 202 Audio processing extension instruction control block 203 Video processing extension instruction control block 204 Extension instruction management block 205 Extension instruction decode block 301 Pre-stage connection switch 302 Sub-stage connection switch 303 Divider 304 Multiplier 305 Shifter 306 ALU
307 Connection decoding device

Claims (13)

A central processing unit that executes instructions such as operations and judgments;
A memory containing a program that is a set of instructions for the central processing unit;
Definition means for newly defining an instruction of the central processing unit during operation;
An instruction group definition memory capable of recording a plurality of combinations of instructions defined in advance in the central processing unit as a series of procedures;
An arithmetic processing apparatus, comprising: executing a series of procedures recorded in the instruction group definition memory by executing an instruction newly defined by the defining means. The arithmetic processing device according to claim 1,
An arithmetic processing unit characterized in that a plurality of types of the series of procedures can be stored in the instruction group definition memory. In the arithmetic processing unit according to claim 1 or 2,
The arithmetic processing unit, wherein the central processing unit itself writes the series of procedures in the instruction group definition memory. In the arithmetic processing unit according to claim 1 or 2,
The arithmetic processing unit, wherein the series of procedures is written into the instruction group definition memory by an instruction optimization unit from an address defined in advance with an interrupt signal from a peripheral device as a starting point. In the arithmetic processing unit according to any one of claims 1 to 4,
An arithmetic processing unit characterized in that the contents of the instruction group definition memory can be defined using a single instruction. A central processing unit that executes instructions such as operations and judgments;
A memory containing a program that is a set of instructions for the central processing unit;
Definition means for newly defining an instruction of the central processing unit during operation;
An arithmetic processing content definition memory for recording the arithmetic processing content of the newly defined instruction,
An arithmetic processing apparatus that executes a desired arithmetic process by combining arithmetic processing circuits existing in the central processing unit by executing an instruction newly defined by the defining means. The arithmetic processing unit according to claim 6, wherein
An arithmetic processing apparatus characterized in that a plurality of types of arithmetic processing contents can be stored in the arithmetic processing content definition memory. In the arithmetic processing unit according to claim 6 or 7,
The arithmetic processing unit, wherein the central processing unit itself writes the arithmetic processing content in the arithmetic processing content definition memory. In the arithmetic processing unit according to claim 6 or 7,
The arithmetic processing device is characterized in that the arithmetic processing content is written into the arithmetic processing content definition memory by an instruction optimization device from an address defined in advance with an interrupt signal from a peripheral device as a starting point. In the arithmetic processing unit according to any one of claims 6 to 9,
An arithmetic processing device characterized in that the contents of the arithmetic processing content definition memory can be defined using a single instruction. A central processing unit that executes instructions such as operations and judgments;
A memory containing a program that is a set of instructions for the central processing unit;
Definition means for newly defining an instruction of the central processing unit during operation;
An arithmetic processing content definition memory for recording the arithmetic processing content of the newly defined instruction;
It is equipped with an instruction group definition memory that can record multiple instructions as a series of procedures,
By executing the instruction newly defined by the definition means, a series of procedures recorded in the instruction group definition memory is executed, and a new one is newly stored in the memory recorded in the instruction group definition memory. An arithmetic processing device characterized in that, when the content of the arithmetic processing is defined, a desired arithmetic processing is executed by combining arithmetic processing circuits in the central processing unit. The arithmetic processing apparatus according to claim 11,
An arithmetic processing device characterized in that the contents of at least one of the arithmetic processing content definition memory and the instruction group definition memory can be defined using a single instruction.   A system in which the arithmetic processing device according to claim 1 is mounted.

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