JP4646853B2 - Control information supply device - Google Patents

Description

The present invention relates to the control information supply unit for supplying a control information such as commands and addresses to a plurality of the controlled object to perform parallel processing.

In recent years, attention has been focused on parallel processing circuits that operate a plurality of ALUs (Arithmetic and Logic Units) in parallel. The parallel processing circuit is realized by, for example, a reconfigurable circuit.
In this type of circuit, it is necessary to supply commands to all ALUs related to parallel operation at the same timing (same time). Further, the command to be supplied to each ALU changes every moment.

  By the way, in this type of circuit, it is relatively rare that all ALUs move simultaneously, and only some ALUs are operating at the same timing. For example, consider a case where commands are supplied in parallel to three ALUs, that is, ALU1, ALU2, and ALU3. For example, when a command sequence as shown in FIG. 18 is considered, at timing t1, commands d1, NOP, and NOP are supplied in parallel to ALU1, ALU2, and ALU3, respectively. Similarly, commands are supplied in parallel after timing t2.

  An ALU to which NOP (no-operation) is supplied does not require any operation at that timing. There are many such NOPs (invalid commands) in a program for a parallel processing circuit such as a reconfigurable circuit that operates a plurality of ALUs in parallel.

  In a parallel processing circuit such as a reconfigurable circuit, a command string as shown in FIG. 18 is stored in a command RAM (Random Access Memory). The existence of the NOP portion as described above is necessary for the command RAM. The memory area is increased, and the power consumption of the circuit is increased accordingly.

  A method that takes this into account is disclosed in Patent Document 1 below. In this method, except for invalid commands, only valid commands are packed and described, and data such as an index indicating validity / invalidity of each command is formed.

JP 7-175648 A

  The technique described in Patent Document 1 contributes to a reduction in the required memory area of the command RAM, and can function effectively in a certain aspect. However, since a memory for storing the index is necessary, when the number of bits of the original command is small, the ratio of the data amount of the index to all data is increased, and the compression effect is reduced. Further, when decoding, it is necessary to decompress the data described in a packed manner, and the decompression circuit becomes large, resulting in an increase in power consumption.

  Further, the conventional problems have been described focusing on the case of performing parallel operations, but similar problems also exist when processes other than operations such as parallel data read processing and parallel data write processing are performed in parallel.

Therefore, an object of the present invention is to provide a control information supply apparatus that contributes to a reduction in the amount of data that should be stored in order to cause a controlled object related to parallel processing to perform a necessary operation .

The control information supply device according to the present invention is a control information supply device that supplies control information for controlling the operation of the controlled object to each of the n controlled objects in parallel and one after another (n is An integer greater than or equal to 2), a first storage means for storing a compression control information sequence including a composite control information group composed of n pieces of control information obtained by combining control information for a plurality of timings; Supply control means for supplying control information included in the compression control information sequence to a control target, and the supply control means commonly sets the n combination control information groups at the plurality of timings. It supplies to the controlled object of.

Compression control information sequence includes a synthesized synthesis control information group control information for a plurality of supply timing, the plurality of supply timing, in common, supplies the synthetic control information group into n of the controlled object To do. That is, control information for a plurality of supply timings can be covered by one synthesis control information group. As a result, the amount of data to be stored in order to cause the controlled object related to the parallel processing to perform an operation can be reduced. As a result, for example, when an integrated circuit is formed using the present invention, a reduction in chip area and a reduction in power consumption can be expected.

In addition, for example, the control information supply device further includes a second storage unit that stores specific data for specifying control information to be supplied to each controlled object from the compression control information sequence at each supply timing. The supply control means supplies the composite control information group to the n controlled objects in common at the plurality of supply timings based on the specific data.

Also, specifically, for example, the compression control information sequence is generated based on an original control information sequence that represents control information to be supplied to each controlled object at each supply timing, and is included in the original control information sequence. each control information, the operation is classified into the effective control information indicating invalid control information or operation indicating that unnecessary, at each feed timing included before Symbol plurality of supply timing, the supply to each of the controlled object When the control information to be used is the first, second,..., Kth control information, the first to kth control information includes at least one of valid control information and invalid control information having the same contents. (K is an integer of 2 or more).

The first to kth control information related to a plurality of supply timings include only valid control information having the same contents, only invalid control information, or only valid control information and invalid control information having the same contents. Then, they may be combined into one to form a composite control information group, which may be supplied to the controlled object in common with the plurality of supply timings.

  According to the present invention, it is possible to expect a reduction in the amount of data to be stored in order to cause a controlled object related to parallel processing to perform a necessary operation.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. In the drawings to be referred to, the same parts are denoted by the same reference numerals.

<< First Embodiment >>
A first embodiment of the present invention will be described. First, the basic concept of the command compression method and the command supply method according to this embodiment will be described. An example in which commands are supplied in parallel to three ALUs (Arithmetic and Logic Units) included in the parallel processing circuit 11 shown in FIG. 1, that is, ALU [1], ALU [2], and ALU [3]. To

  Reference numeral 61 in FIG. 2 indicates the contents of the command that should be supplied to each of ALU [1] to ALU [3] in FIG. 1 at the timings T1, T2, T3, T4, T5,. Represents a command sequence enumerating. Hereinafter, this is referred to as an original command sequence 61. Time advances in the order of timing T1, T2, T3, T4, T5,. Hereinafter, the embodiment will be described with the description content of the original command sequence 61 as an example for the sake of concrete description.

The original command sequence 61 is
“At timing T1, the commands to be supplied to ALU [1], ALU [2], and ALU [3] are the command D1, NOP, and NOP, respectively.”
“At timing T2, the commands to be supplied to ALU [1], ALU [2], and ALU [3] are the commands NOP, D2, and NOP, respectively.”
“At timing T3, the commands to be supplied to ALU [1], ALU [2], and ALU [3] are the commands NOP, NOP, and D3, respectively.”
“At timing T4, commands to be supplied to ALU [1], ALU [2], ALU [3] are commands NOP, D4, D5” and “At timing T5, ALU [1], ALU [2], command to be supplied to ALU [3], command D6, NOP, NOP respectively ",
Is stipulated.

  The command NOP (no-operation) is an invalid command (invalid control information) indicating that the operation of the ALU at that timing is unnecessary. There are relatively few cases in which all ALUs need to operate simultaneously, and only some ALUs often operate at the same timing. For this reason, the program for performing parallel processing includes many NOPs as in the original command sequence 61.

  The commands D1 to D6 are used to specify the operation contents to be executed by the ALU (any one of ALU [1] to ALU [3]). For example, they are ADD corresponding to addition and SUB corresponding to subtraction. , MUL corresponding to multiplication, OR corresponding to logical sum, AND corresponding to logical product, and the like. These commands other than NOP can be called valid commands (valid control information) for instructing the arithmetic operation of the ALU, in contrast to the invalid commands.

  Note that the contents of the commands D0 to D6 may be different from each other, or all or a part thereof may be the same (the contents of the command may be referred to as a command type).

  The fact that a command NOP is defined at a certain timing for a certain ALU means that the operation of the ALU is not necessary at that timing, and therefore the output of the ALU is required for any circuit. Means not. That is, the output of the ALU is not used for any circuit at the timing (in other words, not connected to any circuit). Therefore, even if a command other than NOP is supplied at that timing and the ALU is caused to execute an operation according to the command, there is no problem in the overall operation of the parallel processing circuit 11 (and the device including it).

  Considering this, the commands at the timings T1 to T3 can be combined into one, and the commands at the timings T4 and T5 can be combined into one. The summary result is shown in FIG.

  A combination of commands at a plurality of timings is called a composite command group (composite control information group). One synthetic command group is composed of the same number of commands as the number of ALUs to which commands are to be supplied in parallel. In the example of this embodiment, since the number of ALUs is 3, one synthetic command group is composed of three commands.

  In FIG. 3, reference numeral 65 represents a combined command group in which the commands at timings T1 to T3 are combined into one, and reference numeral 66 represents a combined command group in which the commands at timings T4 and T5 are combined into one.

  The composite command group 65 includes a command D1 as a command to be supplied to ALU [1], a command D2 as a command to be supplied to ALU [2], and a command D3 as a command to be supplied to ALU [3]. , Consists of three commands. The composite command group 66 includes a command D6 as a command to be supplied to ALU [1], a command D4 as a command to be supplied to ALU [2], and a command D5 as a command to be supplied to ALU [3]. , Consists of three commands.

  A combination of the combination command groups 65 and 66 and another combination command group (not shown) is referred to as a compressed command sequence 62. However, the compressed command string 62 can also include a command group (non-synthetic command group) other than the synthetic command group. The method for generating the compressed command string will be further described later.

  The compressed command string 62 is stored in a command RAM (Random Access Memory) 12 shown in FIG. A composite command group 65 is stored at address A0 in the command RAM 12, and a composite command group 66 is stored at address A1 on the lower address side thereof.

  In the command RAM 12, commands D1, D2 and D3 are stored in order from the upper address side of the address A0, and commands D6, D4 and D5 are stored in order from the upper address side of the address A1. In each address (for example, A0 or A1), ALU [1], ALU [2], and ALU [3] are assigned in order from the command on the higher address side. That is, commands D1 and D6 are assigned as commands to be supplied to ALU [1], commands D2 and D4 are assigned as commands to be supplied to ALU [2], and commands D3 and D5 are assigned to ALU [3]. Are stored in the command RAM 12 while being assigned as commands to be supplied to the command RAM 12.

  In practice, a supply command sequence as indicated by reference numeral 64 in FIG. 4 is supplied to each ALU [m] (m is an integer between 1 and 3). That is, at each of the timings T1 to T3, the command (that is, the compressed command group 65) stored at the address A0 in the command RAM 12 is supplied to each ALU [m], and at each of the timings T4 and T5, the command RAM 12 The command (that is, the compressed command group 66) stored in the address A1 is supplied to each ALU [m].

  Accordingly, at each of timings T1 to T3, the command D1 is supplied to ALU [1], the command D2 is supplied to ALU [2], and the command D3 is supplied to ALU [3]. Further, at each of timings T4 and T5, a command D6 is supplied to ALU [1], a command D4 is supplied to ALU [2], and a command D5 is supplied to ALU [3]. Note that reference numeral 63 in FIG. 4 will be described later.

  In the original command sequence 61, for example, NOP is defined as a command to ALU [2] at the timing T1, but even if the command D2 is supplied instead of this, the above-described problem occurs. Absent. The same applies to other timings and other ALUs.

  If the original command sequence 61 is stored as it is in the command supply command RAM, the required memory area of the command RAM becomes very large. However, the original command sequence 61 is compressed to generate a compressed command sequence 62, and the compression is performed. If the command string 62 is stored in the command RAM 12, the required memory area of the command RAM 12 is reduced. As a result, the chip area and power consumption of an integrated circuit (an integrated circuit 2 in FIG. 5 described later) including the command RAM 12 can be reduced.

[Configuration of parallel processing system]
Next, a parallel processing system configured based on the above concept will be described. FIG. 5 is an overall configuration block diagram of the parallel processing system 1 according to the first embodiment. The parallel processing system 1 includes an integrated circuit 2, an original program 3, and a compression unit 4.

  FIG. 6 shows an internal block diagram of the integrated circuit 2. The integrated circuit 2 includes a parallel processing circuit 11, a command RAM 12, an address table 13, and a sequencer 14. The parallel processing circuit 11 in the integrated circuit 2 is the same as that in FIG.

  The parallel processing circuit 11 is, for example, a reconfigurable circuit having a function that enables reconfiguration of a logic circuit, and includes a plurality of ALUs to be controlled that perform four arithmetic operations, logical operations, and the like inside. ing. For the sake of concreteness and simplification of description, attention is paid to the three ALUs included in the parallel processing circuit 11, that is, ALU [1], ALU [2], and ALU [3] as described above. Actually, for example, about 10 to several hundreds of ALUs (not shown) that perform parallel processing are incorporated in the parallel processing circuit 11, and the command RAM 12 and the address table 13 are configured corresponding to the number of ALUs. Is done.

  The three ALU [1] to ALU [3] are incorporated in the parallel processing circuit 11 for performing parallel processing, and it is necessary to simultaneously supply commands to the three ALU [1] to ALU [3]. . Here, “simultaneous” is a concept including a slight time lag that does not hinder the operation of the parallel processing circuit 11.

  In the original program 3 of FIG. 5, an original command string listing commands to be originally supplied to ALU [1] to ALU [3] is expressed. For the sake of concrete explanation, the original command sequence is assumed to be the original command sequence 61 of FIG.

  The compression unit 4 functions as a compiler that converts the original command sequence 61 into a data format that can be supplied to the integrated circuit 2 while being compressed. The compression unit 4 is configured as a compression program, for example, and the compression program and the original program 3 in FIG. 5 are stored in a recording medium such as a hard disk. The compression unit 4 (compression program) operates on a computer (not shown) capable of reading the storage contents of the recording medium, compresses the original command sequence 61, and generates a compressed command sequence 62 as shown in FIG. Generate.

  The computer functions as a device (control information compression device) for realizing the function of the compression unit 4, and the computer is used as a parallel processing system according to the present embodiment (and a second embodiment to be described later). It can also be considered as a component of. Further, the entire parallel processing system according to the present embodiment (and a second embodiment to be described later) can be mounted on one apparatus. Further, the compression unit 4 may be configured by hardware.

  The compression unit 4 also generates table data (specific data) that specifies the content indicated by the reference numeral 63 in FIG. As described above, the command RAM 12 in FIG. 6 stores the compressed command string 62 in FIG. 3 at the specified addresses (addresses A0, A1,...). And at which timing stored data (command for ALU [m]) in the command RAM 12 is specified. In the case of the example described above, for example, table data listing addresses A0, A0, A0, A1, A1,... In order from the top of the table is generated. The generated table data is hereinafter referred to as table data 63.

  The contents of the compressed command sequence 62 and the table data 63 generated by the compression unit 4 are transmitted to the command RAM 12 and the address table 13 via the input terminals (not shown) of the integrated circuit 2 of FIG. The command RAM 12 stores a compressed command sequence 62, and the address table 13 stores table data 63.

  In FIG. 6, the sequencer 14 determines the timing at which commands are actually input to ALU [1] to ALU [3] according to the generated or input data clock. The timings T1, T2,... Described above are actually determined by the sequencer 14. An address table 13 is provided after the sequencer 14, and addresses in the table data 63 are sequentially supplied from the address table 13 to the command RAM 12 in accordance with instructions from the sequencer 14. The command RAM 12 sequentially supplies data (that is, commands) stored at addresses designated from the address table 13 to ALU [1] to ALU [3].

  Specifically, at the timing T1, the sequencer 14 causes the head data of the table data 63, that is, the address A0 to be output to the address table 13. In response to the output address A0, the command RAM 12 supplies the command stored at its own address A0 to ALU [1] to ALU [3]. In the case of the present example, the composite command group 65 of FIG. 3 is supplied to ALU [1] to ALU [3].

  At the timing T2 next to the timing T1, the sequencer 14 outputs the data next to the head data of the table data 63, that is, the address A0, to the address table 13, and the command RAM 12 receives the data at the address A0. The stored command is supplied to ALU [1] to ALU [3]. The same applies to the timing T3 and thereafter, and at the timing T3, T4, T5,..., The address table 13 designates the addresses A0, A1, A1,.

  Thus, as described above, at each of the timings T1 to T3, the command D1 is supplied to ALU [1], the command D2 is supplied to ALU [2], and the command D3 is supplied to ALU [3]. The Further, at each of timings T4 and T5, a command D6 is supplied to ALU [1], a command D4 is supplied to ALU [2], and a command D5 is supplied to ALU [3].

[Compression command generation method]
The compression command sequence 62 of FIG. 3 generated from the original command sequence 61 of FIG. 2 is given as an example of the compression command sequence, and the operation of the parallel processing system 1 according to the present embodiment has been described with reference to this. Here, a further description will be given of a method for generating a compressed command string by the compression unit 4 of FIG.

  The compressed command string is configured to include synthetic command groups such as the synthetic command groups 65 and 66 in FIG. 3, and the synthetic patterns of the synthetic command groups are roughly divided into three synthetic patterns. This will be described below as first, second, and third synthesis patterns.

  Now, commands α and β are defined as commands (valid commands) other than NOP. The commands α and β are commands having different contents (types). For example, the commands α and β are AND and SUB, respectively. However, the commands α and β may be the same.

  Also, first and second compositing target command groups as shown in FIG. 7 are defined as command groups describing commands for ALU [1] to ALU [3]. In the present embodiment, the command group means a generic name of three commands corresponding to ALU [1] to ALU [3].

  The first compositing target command group includes commands [i, 1], [i, 2], and [i, 3], and the second compositing target command group includes commands [j, 1], [j, 2]. ] And [j, 3]. Assuming that the original command sequence represented in the original program 3 is composed of commands for a total of N timings, i and j take each integer between 1 and N. However, i ≠ j. For example, the first and second compositing target command groups are command groups corresponding to the timings T1 and T2 included in the command sequence 61 of FIG. 2 and are included in the original command sequence 61, respectively.

The commands [i, 1], [i, 2] and [i, 3] are commands corresponding to ALU [1], ALU [2] and ALU [3], respectively, and the commands [j, 1], [J, 2] and [j, 3] are commands corresponding to ALU [1], ALU [2], and ALU [3], respectively.

――― First synthesis pattern (Fig. 8) ―――
FIG. 8 is a diagram for explaining the first synthesis pattern. In FIG. 8, commands [i, 1], [i, 2] and [i, 3] in the first synthesis target command group 81 are the commands α, NOP and NOP, respectively, and the second synthesis target command. Commands [j, 1], [j, 2] and [j, 3] in group 82 are commands NOP, β and NOP, respectively.

  The compression unit 4 reads “command [i, m] in the first compositing target command group 81 and command [j, m] in the second compositing target command group 82 for each of m = 1, 2, and 3. The at least one of the two commands is a NOP ”.

  As a result of the determination, a condition that “at least one of the two commands is NOP for all m = 1, 2, and 3” (this condition is referred to as “first synthesis condition”) is satisfied. In this case, the first and second synthesis target command groups 81 and 82 are synthesized to generate a synthesis command group 83.

In the example of FIG.
Regarding m = 1, the two commands corresponding to the command [i, 1] and the command [j, 1] are α and NOP, and include NOP. in addition,
Regarding m = 2, the two commands corresponding to the command [i, 2] and the command [j, 2] are NOP and β, and include NOP. in addition,
Regarding m = 3, the two commands corresponding to the command [i, 3] and the command [j, 3] are NOP and NOP, and include NOP.
For this reason, the first synthesis condition is satisfied and a synthesis command group 83 is generated.

  The synthesis command group 83 is generated by synthesizing commands corresponding to the same ALU [m] in the first and second synthesis target command groups 81 and 82. At this time, for each of m = 1, 2, and 3, if the effective command other than NOP is included in the two commands to be combined, the effective command is used as the post-synthesis command, and the two commands to be combined If both are NOPs, NOP is used as a command after synthesis.

  As a result, the combined command group 83 becomes a command group indicating that the commands corresponding to ALU [1], ALU [2], and ALU [3] are the commands α, β, and NOP, respectively.

  The composite command group 83 can be stored in the compressed command string as it is, for example. Actually, the synthesis command group 83 is newly treated as the first synthesis target command group, and further synthesis is attempted. For example, the synthesis command group 83 is handled as a first synthesis target command group as shown in FIG. 9, and the commands [j, 1], [j, 2] and [j, 3] are respectively NOP, NOP and An attempt is made to combine γ with the second compositing target command group. These are synthesized to satisfy the first synthesis condition.

――― Second synthesis pattern (Fig.10) ―――
FIG. 10 is a diagram for explaining the second synthesis pattern. In FIG. 10, commands [i, 1], [i, 2] and [i, 3] in the first synthesis target command group 84 are commands α, β and NOP, respectively, and the second synthesis target command. Commands [j, 1], [j, 2] and [j, 3] in group 85 are also commands α, β and NOP, respectively.

  The compression unit 4 reads “command [i, m] in the first compositing target command group 84 and command [j, m] in the second compositing target command group 85 for each of m = 1, 2, and 3. The two commands are referred to, and it is determined whether or not the two commands have the same content (type).

  As a result of the determination, a condition that “the two commands are commands having the same content (type) for all m = 1, 2, and 3” (this condition is referred to as “second synthesis condition”). When satisfied, the first and second compositing target command groups 84 and 85 are synthesized to generate a synthesized command group 86.

In the example of FIG.
Regarding m = 1, the two commands corresponding to the command [i, 1] and the command [j, 1] are both commands α. in addition,
Regarding m = 2, the two commands corresponding to the command [i, 2] and the command [j, 2] are both commands β. in addition,
Regarding m = 3, the two commands corresponding to the command [i, 3] and the command [j, 3] are both NOP.
For this reason, the second pattern synthesis condition is satisfied and a synthesis command group 86 is generated.

  The synthesized command group 86 is generated by synthesizing commands corresponding to the same ALU [m] in the first and second synthesis target command groups 84 and 85, as in the first synthesis pattern described above. Since the second synthesis condition is satisfied, any one of the first and second synthesis target command groups 84 and 85 may be handled as the synthesis command group 86 as it is. In the present example, as a result, the composite command group 86 is the same as the composite command group 83 of FIG.

  The composite command group 86 can be stored in the compressed command string as it is, for example. Actually, as described in the above-described first synthesis pattern, this synthesis command group 86 is newly handled as the first synthesis target command group, and further synthesis with another command group is attempted.

――― Third synthesis pattern (Fig.11) ―――
FIG. 11 is a diagram for explaining the third synthesis pattern. In FIG. 11, commands [i, 1], [i, 2] and [i, 3] in the first synthesis target command group 87 are commands α, β and NOP, respectively, and the second synthesis target command. Commands [j, 1], [j, 2] and [j, 3] in group 88 are commands NOP, β and NOP, respectively. The third synthesis pattern corresponds to a combination of the first and second synthesis patterns described above.

  The compression unit 4 reads “command [i, m] in the first compositing target command group 87 and command [j, m] in the second compositing target command group 88 for each of m = 1, 2, and 3. The at least one of the two commands is NOP, or whether the two commands are commands having the same content (type).

  As a result of the determination, a condition that “for all m = 1, 2 and 3, at least one of the two commands is a NOP, or the two commands are commands having the same content (type)”. When this condition is referred to as “third synthesis condition”, the first and second synthesis target command groups 87 and 88 are synthesized to generate a synthesis command group 89.

In the case of the example of FIG.
Regarding m = 1, the two commands corresponding to the command [i, 1] and the command [j, 1] are α and NOP, and include NOP. in addition,
Regarding m = 2, the two commands corresponding to the command [i, 2] and the command [j, 2] are both commands β. in addition,
Regarding m = 3, the two commands corresponding to the command [i, 3] and the command [j, 3] are both NOP.
For this reason, the third pattern synthesis condition is satisfied and a synthesis command group 89 is generated.

  The synthesized command group 89 is generated by synthesizing commands corresponding to the same ALU [m] in the first and second synthesis target command groups 87 and 88 as in the first synthesis pattern described above. At this time, for each of m = 1, 2, and 3, if the effective command other than NOP is included in the two commands to be combined, the effective command is used as the post-synthesis command, and the two commands to be combined If both are NOPs, NOP is a command after synthesis, and if both of the two commands to be synthesized are valid commands having the same contents, the valid command is taken as a command after synthesis. In the case of the present example, as a result, the composite command group 89 is the same as the composite command group 83 of FIG.

  The composite command group 89 can be stored in the compressed command string as it is, for example. Actually, as described in the above-described first synthesis pattern, this synthesis command group 89 is newly treated as the first synthesis target command group, and further synthesis with another command group is attempted.

[Compression command generation flow]
Next, the compression procedure of the original command sequence by the compression unit 4 in FIG. 5 will be described. FIG. 12 is a flowchart showing the compression procedure.

  First, in step S1, a command group (three commands) corresponding to the timing T1 in the original command sequence such as the original command sequence 61 in FIG. 2 is set as the first compositing target command group, and the command corresponding to the timing T2. Let the group (three commands) be the second compositing target command group. When the process of step S1 is completed, the process proceeds to step S2.

  In step S2, it is determined whether the first, second, and third synthesis conditions described above are satisfied for the first and second synthesis target command groups. If any of the first, second, and third synthesis conditions is satisfied, the process proceeds to step S3 (Y in step S2). If not satisfied, the process proceeds to step S5 (N in step S2). It should be noted that it is possible to modify the process so that the process proceeds to step S3 only when the first synthesis condition is satisfied, only when the second synthesis condition is satisfied, or only when the third synthesis condition is satisfied. . However, considering the compression efficiency, it is desirable not to perform this modification.

  In step S3, the first and second synthesis target command groups are synthesized according to the above description. When step S3 is completed, the process proceeds to step S4.

  In step S4, a synthesized command group obtained by this synthesis is newly set as a first synthesized object command group. When step S4 is completed, the process proceeds to step S5.

  In step S5, it is determined whether the second compositing target command group can be set for the current first compositing target command group, and if it can be set, the process proceeds to step S6 (Y in step S5). If it cannot be set, the process proceeds to step S7 (N in step S5). A command group already synthesized with another command group is not set as the second synthesis target command group. In addition, the command group that has already been subjected to the determination process in step S2 with the current first compositing target command group or the command group that is the basis of the current compositing target command group has This is not the second compositing target command group.

  In step S6, the second compositing target command group is set in relation to the current first compositing target command group, and the process returns to step S2. Thereafter, the processing after step S2 is repeated.

  In step S7, “There are two or more command groups that have not undergone the synthesizing process in step S3 in the original command sequence, and among the two or more command groups, the synthesis condition is established / not established in step S2. It is determined whether there is a combination of commands that has not been determined. If there is such a combination (Y in step S7), the process proceeds to step S8, two command groups forming the combination are set as the first and second compositing target command groups, and the process returns to step S2. On the other hand, when there is no such combination (N of step S7), the process shown in FIG. 12 is complete | finished.

  For example, consider a case where a compressed command string corresponding to the original command string as shown in FIG. 13 is generated. This original command sequence stores commands for six timings. Command groups corresponding to timings T1, T2, T3, T4, T5, and T6 in the original command sequence in FIG. 13 are referred to as command groups 91, 92, 93, 94, 95, and 96, respectively.

  In this case, first, command groups 91 and 92 are synthesized in step S3, and then command group 93 is newly set as a second synthesized command group in step S6. However, since the command group 91 and the command group 93 cannot be combined with the command group 93, the second determination in step S2 is No. After that, in step S6, the command group 94 is newly set as the second composite command group. Is set. Then, the command groups 91, 92, and 94 are synthesized through steps S2 and S3, and the process proceeds to step S7 through the loop processing of further steps S2 to S6.

  Then, after the processes of steps S7 and S8, the command groups 93 and 96 are synthesized, the command group 95 remains as it is, and the process of FIG.

  FIG. 14 shows a compressed command sequence generated by compressing the original command sequence shown in FIG. As described above, the compressed command string may include a command group other than the synthesized command group (non-synthesized command group; command group 95).

  Although not particularly provided in the flowchart of FIG. 12, table data to be stored in the address table 13 of FIG. 6 is also generated in the synthesis process in step S3 and the like.

<< Second Embodiment >>
In the first embodiment described above, an ALU is handled as a controlled object, and a command is handled as control information for controlling the operation of the controlled object. The configuration and method described in the first embodiment can be applied not only to an ALU that performs arithmetic processing in parallel, but also to a storage unit that performs data reading or data writing in parallel. The storage means is, for example, a recording medium such as a semiconductor memory such as a RAM and a ROM (Read Only Memory), and an optical disk.

  An embodiment in which the controlled object is a RAM is illustrated as a second embodiment. FIG. 15 is an internal block diagram of the integrated circuit 2a according to the second embodiment. The integrated circuit 2a corresponds to the integrated circuit 2 of FIG. The overall configuration of a parallel processing system (not shown) according to the second embodiment is different from that of the parallel processing system 1 according to the first embodiment in that the integrated circuit 2 is replaced with an integrated circuit 2a. Both are the same.

  As can be seen from the comparison between FIG. 6 and FIG. 15, the integrated circuit 2a has a configuration in which the parallel processing circuit 11 and the command RAM 12 in the integrated circuit 2 of FIG. 6 are replaced with the parallel processing circuit 11a and the address RAM 12a, respectively. In other respects, the integrated circuits 2 and 2a are similar.

  The parallel processing circuit 11a includes a plurality of RAMs to be controlled. Specifically, as shown in FIG. 15, the parallel processing circuit 11a includes a RAM [1], a RAM [2], and a RAM [3]. It is necessary to supply addresses to the three RAMs [1] to [3] at the same time (that is, in parallel) at each timing.

  The RAM [m] reads out and outputs the stored data in its own memory area corresponding to the address according to the supplied address, or writes the designated data in its own memory area corresponding to the address. (M takes each integer within the range of 1-3). Therefore, the address supplied to the RAM [m] can be called control information for controlling the operation of the RAM [m] such as data reading or data writing.

  The second embodiment basically corresponds to the “ALU” and “command” in the first embodiment replaced with “RAM” and “address”, and is the same as the contents described in the first embodiment. All the contents of can be applied to the second embodiment.

  That is, in the second embodiment, for example, in the original program 3, an original address column 71 as shown in FIG. 16 is listed in which addresses to be originally supplied to the RAM [1] to RAM [3] are listed. In the original address column 71, addresses to be supplied to the RAM [1] to the RAM [3] are described at the timings T1, T2, T3, T4, T5,.

The original address column 71 is
“At timing T1, the addresses to be supplied to RAM [1], RAM [2], and RAM [3] are addresses R1, XX, and XX, respectively”.
“At timing T2, the addresses to be supplied to RAM [1], RAM [2], and RAM [3] are addresses XX, R2, and XX, respectively.”
“At timing T3, the addresses to be supplied to RAM [1], RAM [2], and RAM [3] are addresses XX, XX, and R3, respectively.”
“At timing T4, the addresses to be supplied to RAM [1], RAM [2], and RAM [3] are addresses XX, R4, and R5,” and “At timing T5, RAM [1], Addresses to be supplied to RAM [2] and RAM [3] are addresses R6, XX and XX, respectively. "
Is stipulated.

  The addresses R1 to R6 designate addresses to be supplied to the RAM (any of RAM [1] to RAM [3]). The address XX is an invalid address indicating that the operation of the RAM at that timing is unnecessary. There are relatively few cases in which all RAMs need to operate simultaneously, and only some of the RAMs often operate at the same timing. For this reason, a program for performing parallel processing includes many addresses XX corresponding to invalid addresses as in the original address sequence 71.

  In the second embodiment, the compression unit 4 handles the address XX (invalid address) in the same manner as the NOP (invalid command) in the first embodiment, and compresses the original address string 71 shown in FIG. 16 as in the first embodiment. Thus, the compressed address string 72 shown in FIG. 17 is generated. Further, table data (specific data) corresponding to the compressed address column 72 is also generated.

  The compressed address string 72 includes a combined address group 75 in which the addresses at timings T1 to T3 are combined into one, and a combined address group 76 in which the addresses at timings T4 and T5 are combined into one. . The table data specifies “at which timing storage data (address for RAM [m]) in the address RAM 12 a is supplied to RAM [m]”.

  The compressed address string 72 is stored in the address RAM 12 a and the table data is stored in the address table 13. The address RAM 12a is the same as the command RAM 12 of FIG. 6 except that the stored contents are addresses instead of commands.

  Then, under the control of the sequencer 14, the address RAM 12a supplies the address R1 to the RAM [1] and the address R2 to the RAM [2] at each of the timings T1 to T3 according to the output value from the address table 13. Then, the address R3 is supplied to the RAM [3]. At timings T4 and T5, the address R6 is supplied to the RAM [1], the address R4 is supplied to the RAM [2], and the address R5 is supplied to the RAM [3].

  The fact that an invalid address (address XX) is defined at a certain timing with respect to a certain RAM means that the operation of the RAM is not necessary at the timing, and therefore, the output of the RAM is not transmitted to any circuit. Also means that it is not needed. That is, at the timing, the output of the RAM is not used for any circuit (in other words, not connected to any circuit).

  Therefore, when data is read from the RAM [m], another arbitrary address (effective address) is supplied to the RAM at that timing, and data corresponding to the address is output. And the entire operation of the apparatus including the same does not cause a problem. Even when control for writing data to RAM [m] is executed, actual data writing is not performed unless a write enable signal for permitting data writing is given to RAM [m]. Therefore, even in such a case, there is no problem even if an arbitrary address is supplied.

  Note that “NOP” in the first embodiment is read as “XX” in the second embodiment. Further, when considering the second and third synthesis conditions in the first embodiment, as described above, the identity of the contents of the command is considered. In the second embodiment, when considering the above-described second and third synthesis conditions, the identity of the address contents is similarly considered. “Contents of address” means an address value. If the contents of the addresses R1 and R6 are the same, the contents of the addresses R2 and R4 are the same, and the contents of the addresses R3 and R5 are the same, the second synthesis condition is satisfied, and FIG. The 17 composite address groups 75 and 76 can be combined into one.

  If the original address string 71 is stored in the address supply address RAM as it is, the required memory area of the address RAM becomes very large. However, the original address string 71 is compressed to generate a compressed address string 72 and compressed. If the address string 72 is stored in the address RAM 12a, the necessary memory area of the address RAM 12a is reduced. As a result, the chip area and the power consumption of the integrated circuit 2a including the address RAM 12a can be reduced.

<< Deformation, etc. >>
The functions of the parallel processing system in each of the embodiments described above can be realized by hardware, software, or a combination thereof.

  In FIG. 6 (or FIG. 15), the command RAM 12 (or the address RAM 12a), the address table 13 and the sequencer 14 are configured to send a command (control information) to ALU [m] (or RAM [m]) as a controlled object. Or a control information supply device (control information decompression device) that supplies an address).

  In addition, a function executed by the control information supply device (control information decompression device) is described as an decompression program, and the decompression program is executed on the computer, whereby ALU [m] (or RAM [m]) The command (or address) described above may be supplied.

  In the first embodiment, the command NOP (invalid command), the original command string 61, and the compressed command string 62 function as invalid control information, an original control information string, and a compressed control information string, respectively. Further, commands other than the command NOP (valid command; D1 in FIG. 2) function as valid control information.

  In the second embodiment, the address XX (invalid address), the original address string 71, and the compressed address string 72 function as invalid control information, an original control information string, and a compressed control information string, respectively. Addresses other than the address XX (valid address; R1 in FIG. 16) function as valid control information.

  In the first and second embodiments, the supply control means is mainly formed by the sequencer 14.

1 is an internal block diagram of a parallel processing circuit according to a first embodiment of the present invention. It is a figure showing the original command sequence which described the command which should be supplied to each ALU of FIG. FIG. 3 is a diagram illustrating a compressed command sequence generated by compression from the original command sequence of FIG. 2. It is a figure showing the command actually supplied to each ALU of FIG. 1 is an overall configuration block diagram of a parallel processing system according to a first embodiment of the present invention. FIG. 6 is an internal block diagram of the integrated circuit of FIG. 5. It is a figure for demonstrating the synthetic | combination method of the command by the compression part of FIG. It is a figure for demonstrating the 1st synthetic pattern applied to the compression part of FIG. It is a figure for demonstrating the 1st synthetic pattern applied to the compression part of FIG. It is a figure for demonstrating the 2nd synthetic | combination pattern applied to the compression part of FIG. It is a figure for demonstrating the 3rd synthetic | combination pattern applied to the compression part of FIG. It is a flowchart showing the compression procedure of the original command sequence by the compression part of FIG. It is a figure for demonstrating the process of the flowchart of FIG. It is a figure for demonstrating the process of the flowchart of FIG. It is an internal block diagram of the integrated circuit which concerns on 2nd Embodiment of this invention. It is a figure showing the original address row | line | column describing the address which should originally be supplied to each RAM of FIG. FIG. 17 is a diagram illustrating a compressed address string that is compressed and generated from the original address string of FIG. 16. It is a figure showing the command supplied with respect to the conventional parallel processing circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Parallel processing system 2, 2a Integrated circuit 3 Original program 4 Compression part 11, 11a Parallel processing circuit 12 Command RAM
13 Address table 14 Sequencer 12a Address RAM

Claims (3)

In a control information supply apparatus that supplies control information for controlling the operation of each of the n controlled objects in parallel to each controlled object one after another at a predetermined supply timing (n is an integer of 2 or more) ),
N controls obtained by combining control information supplied to the controlled objects at a plurality of supply timings from the i-th to the j-th (i and j are integers satisfying 0 <i <j). First storage means for storing a compression control information sequence including a composite control information group consisting of information;
Supply control means for supplying control information included in the compression control information sequence to each controlled object,
The supply control means supplies the composite control information group to the n controlled objects in common at the plurality of supply timings. The control information supply device further includes second storage means for storing specific data for specifying control information to be supplied to each controlled object at each supply timing from the compression control information sequence,
2. The supply control unit according to claim 1, wherein the supply control unit supplies the combination control information group to the n controlled objects in common at the plurality of supply timings based on the specific data. Control information supply device. The compression control information sequence is generated based on an original control information sequence representing control information to be supplied to each controlled object at each supply timing,
Each control information in the original control information sequence is classified into invalid control information indicating that no action is required or valid control information indicating an action,
When the control information supplied to each controlled object is the first, second,..., Kth control information at each of the supply timings included in the plurality of supply timings, the first to kth controls. 3. The control information supply apparatus according to claim 1, wherein the information includes at least one of valid control information and invalid control information having the same contents (k is an integer of 2 or more).

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