JP4512334B2 - Bus bridge circuit - Google Patents

Description

  The present invention relates to a bus bridge circuit between a CPU and an I / O circuit that enables a control operation corresponding to a difference in data bus width.

Some CPUs currently in general use have a 16-bit data bus configuration and allow 32-bit data access (see, for example, “VR14131” manufactured by NEC). At the time of execution of such an instruction, data processing is performed in which 16-bit access is repeated twice for consecutive addresses. However, it is not possible to determine whether 16-bit access or 32-bit access is performed at the first access. Therefore, in general, data is divided into upper 16 bits and lower 16 bits corresponding to the address accessed each time, and data processing is performed as 16-bit data divided into two times.
Japanese Patent Laid-Open No. 2002-24164

  However, there are some peripheral I / O circuits accessed from the CPU that do not operate normally when divided into 16 bits and are accessed twice, and require 32-bit simultaneous access. The present invention has been made in view of such inconveniences, and provides a bus bridge circuit that allows 32-bit access to a 32-bit I / O circuit from a CPU having a 16-bit data bus. Objective.

  A bus bridge circuit 10 according to the present invention, as schematically shown in FIG. 1, is between a CPU 14 and an I / O circuit 18 having a data bus width wider than that of the CPU 14. The data transfer operation corresponding to is possible.

  Then, the contents of the address signal and control signal sent from the CPU 14 are analyzed, and a control unit 20 that sends a predetermined address signal and control signal to the I / O circuit 18; and at the time of reading data from the I / O circuit 18 to the CPU 14 A data reading unit 22 that operates and enables the data bus width to be reduced, and a data writing unit 24 that operates when data is written from the CPU 14 to the I / O circuit 18 and enables the data bus width to be increased. ing.

  The data reading unit 22 is between the first data bus 12 on the CPU 14 side and the second data bus 16 on the I / O circuit 18 side, and is directed from the second data bus 16 toward the first data bus 12. The difference between the first buffer means that can regulate the output timing of data having a bus width defined by one data bus 12, the bus width of the second data bus 16, and the bus width of the first data bus 12. And first latch means for temporarily storing data corresponding to.

  When the controller 20 confirms the data read operation from the I / O circuit 18 to the CPU 14, the data corresponding to the predetermined number of bits in the second data bus 16 is sent through the first buffer means. On the other hand, control for holding the data for the remaining number of bits in the first latch means is performed. Further, when the data read operation from the continuous address is confirmed, the data held in the first latch means is output to the CPU 14 without going through the data read operation again.

  The data writing unit 24 is located between the first data bus 12 on the CPU 14 side and the second data bus 16 on the I / O circuit 18 side, and can temporarily store data of the bus width of the first data bus 12. Second latch means, and second buffer means capable of regulating the data output timing corresponding to the difference between the bus width of the second data bus 16 and the bus width of the first data bus 12. I have.

  When the data write operation from the CPU 14 to the I / O circuit 18 is confirmed in the control unit 20, control is performed to hold this data in the second latch means, and further data write to continuous addresses is confirmed. Then, the data held in the second latch means and the data output from the second buffer means are simultaneously output to the I / O circuit 18 while the data writing to the continuous addresses is not confirmed. In this case, only the data held in the second latch means is sent to the I / O circuit 18.

  As described above, the present invention includes a latch unit and a buffer unit, and when it is determined that the addresses to be accessed are continuous, it can be accessed in units of 32 bits. 32-bit access can be performed without malfunction even for an I / O circuit having a 32-bit data bus width, and the instruction execution time can be reduced compared to the 16-bit access that was divided twice. It can be shortened.

  As shown in FIG. 1, the bus bridge circuit 10 according to the present invention includes a CPU 14 connected to a first data bus 12 having a 16-bit bus width and a 32-bit bus width. Between the I / O circuits 18 connected to the two data buses 16, data processing corresponding to the difference in bus width between the two is possible.

  In the present embodiment, an example in which the entire circuit is made into one chip by using a gate array using ASIC technology is shown, but the present invention is not limited to this, and the actual circuit configuration such as individual circuit configuration of each component is shown. Of course, the technology is not limited, and various modifications can be made. A part of the circuit can be converted into firmware by a program.

  Here, the bus bridge circuit 10 includes a control unit 20 mainly responsible for the overall control operation, a data reading unit 22 that operates when reading data, and a data writing unit 24 that operates when writing data.

  The control unit 20 includes an address decoder 26 and a determination circuit 28. Here, as illustrated in FIGS. 4 to 7, the address decoder 26 receives the first address data 30 and the first control signal group 32 from the CPU 14 side, and outputs the second address data to the I / O circuit 18. The address data 34 and the second control signal group 36 can be output.

  The determination circuit 28 checks changes in the input first address data 30 and the first control signal group 32, and sends third and fourth control signal groups to the data reading unit 22 and the data writing unit 24. 38/40 can be output. The detailed operation of the determination circuit 28 will be described later.

  The data reading unit 22 includes one latch circuit 42 and two buffer circuits 44 and 46. The first latch circuit 42 is a register having a data width of 16 bits, and the output side is connected to the first data bus 12 while the input side is connected to the upper 16 bits in the second data bus 16. To do. Then, in conjunction with the input of the third control signal 38 output from the control unit 20, the upper 16 bits of data are fetched from the I / O circuit 18 and temporarily stored, and in conjunction with the input of the control signal 38, the CPU 14. 16 bits of data can be output simultaneously.

  Both the first and second buffer circuits 44 and 46 have a data width of 16 bits, and in accordance with the input timing of the control signal 38, data from the I / O circuit 18 side to the CPU 14 is stored. The output time can be regulated. Further, by connecting the first buffer circuit 44 to the upper 16 bits of the second data bus 16 and connecting the second buffer circuit 46 to the lower 16 bits, the upper and lower 16 bits of data are selected. Therefore, it is possible to output to the CPU 14.

  The data writing unit 24 has substantially the same configuration as that of the data reading unit 22, and includes one latch circuit 48 including a register having a data width of 16 bits and two buffer circuits 50 and 52. The Here, the second latch circuit 48 connects the input side to the first data bus 12, and connects the output side to the lower 16 bits of the second data bus 16. Then, in conjunction with the input of the fourth control signal 40 output from the control unit 20, the 16-bit data output from the CPU 14 is fetched and temporarily stored, while being interlocked with the input of the control signal 40, the lower 16 Bit data can be output to the I / O circuit 18.

  Both the third and fourth buffer circuits 50 and 52 have a data width of 16 bits, and correspond to the input timing of the control signal 40 and the data from the CPU 14 side to the I / O circuit 18 side. The output time can be regulated. Further, by connecting the third buffer circuit 50 to the lower 16 bits in the second data bus 16 and connecting the fourth buffer circuit 52 to the upper 16 bits, the upper and lower 16 bits in the I / O circuit 18 are connected. Bit data can be selectively output.

  Next, based on the flowcharts shown in FIGS. 2 and 3 and the waveform diagrams of FIGS. 4 to 7, specific control operations of the data reading unit 22 and the data writing unit 24 by the determination circuit 28 will be described in detail. . First, when the determination circuit 28 determines from the signals illustrated in FIGS. 4 and 5 that the data read from the I / O circuit 18 by the CPU 14 is started, the data read process starting from step ST11 in FIG. Is started.

  Upon entering this process, it is checked in step ST11 whether the address 30 is divisible by “4”. If it is not divisible by “4”, it can be determined as the upper 16 bits in the 32-bit data. Therefore, in step ST12, the corresponding address is read-accessed, and the upper address in the second data bus 16 is sent to the CPU 14 via the first buffer circuit 44, thereby completing the data reading by 16-bit access.

  Next, if the determination in step ST11 is YES, 32-bit data is read at a time from the I / O circuit 18 to the second data bus 16 in step ST14. The lower 16 bits of the read 32 bits are output to the CPU 14 via the second buffer circuit 46 (step ST15), and at the same time, the upper 16 bits are written to the first latch circuit 42 (step ST16).

  When the next read cycle is entered, in step ST17, for example, if access to the continuous address 30a is determined by the IOCS signal shown in FIG. Without sending a data read command, the data for the upper 16 bits stored in the first latch circuit 42 is sent to the CPU 14 to complete the data read for 32 bits (step ST18).

  Next, when it is determined from the signal group in FIG. 6 and FIG. 7 that the CPU 14 has started the data writing process, it is first checked in step ST21 in FIG. 3 whether or not 8-bit access has been made, and if so, step ST22. Then, write access to the I / O circuit 18 is performed using the write data and address.

  Next, when the determination in step ST21 is NO, it is determined whether or not the address 30 is divisible by “4” in the next step ST23. If it is not divisible, it is determined that writing to the upper 16 bits is performed. Write access is performed as shown in FIG.

  If the determination in step ST23 is YES, the write data is stored in the second latch circuit 48 in step ST24, and then in step ST25, it is determined whether or not there is continuous access from the IOCS signal. If it is not continuous access, it can be determined that the access is 16-bit, so the process proceeds to step ST26, and the 16-bit write access to the I / O circuit 18 is performed using the lower 16-bit data stored in the second latch circuit 48. .

  On the other hand, in the case of continuous access, it can be determined that 32-bit access is made. Therefore, the data output from the CPU 14 at that time is set to upper 16 bits via the fourth buffer circuit 52, and the data stored in the second latch circuit 48 is stored. By simultaneously outputting the 32-bit data having the lower 16 bits to the second data bus 16, a 32-bit write access is performed as shown in FIG. 7 (step ST 27).

It is a block diagram which shows the whole structure of this invention. It is a flowchart explaining the data reading process in a determination circuit. It is a flowchart explaining the data writing process in a determination circuit. 6 is a waveform diagram showing an example of a signal group input / output to / from the bus bridge circuit when data is read by 16-bit access, where (a) shows a signal group input / output to / from the CPU, and (b) shows an I / O circuit Shows a group of signals to be input / output. FIG. 4 is a waveform diagram showing an example of a signal group input / output to / from the bus bridge circuit when data is read by 32-bit access, where (a) shows a signal group input / output to / from a CPU and (b) shows an I / O circuit Shows a group of signals to be input / output. 6 is a waveform diagram showing an example of a signal group input / output to / from the bus bridge circuit when data is written by 16-bit access, where (a) shows a signal group input / output to / from the CPU, and (b) shows an I / O circuit Shows a group of signals to be input / output. FIG. 4 is a waveform diagram showing an example of a signal group input / output to / from the bus bridge circuit when data is written by 32-bit access, where (a) shows a signal group input / output to / from a CPU, and (b) shows an I / O circuit. Shows a group of signals to be input / output.

Explanation of symbols

10 bus bridge circuit 12 first data bus 14 CPU
16 Second Data Bus 18 I / O Circuit 20 Control Unit 22 Data Reading Unit 24 Data Writing Unit 26 Address Decoder 28 Decision Circuit 30 First Address Data 32 First Control Signal Group 34 Second Address Data 36 Second 2 control signal group 38 third control signal group 40 fourth control signal group 42 first latch circuit 44 first buffer circuit 46 second buffer circuit 48 second latch circuit 50 third buffer circuit 52 fourth buffer circuit

Claims (3)

A bus bridge between a CPU (14) having a data bus width of 16 bits and an I / O circuit (18) having a data bus width of 32 bits and enabling a data transfer operation corresponding to the difference in the data bus width A circuit,
A control unit (20) for analyzing the contents of address data and control signals sent from the CPU (14) and sending predetermined address data and control signals to the I / O circuit (18);
The work from the CPU (14) the I / O circuit according to (18) at the time of data reading from the CPU (14), comprising data reading section that enables a reduction in the data bus width and (22),
The data reading unit (22)
Between the first data bus (12) on the CPU (14) side and the second data bus (16) on the I / O circuit (18) side, from the second data bus (16) to the first data bus (16). To the data bus (12), the output timing of the data of the bus width defined by the first data bus (12) can be individually regulated by upper 16 bits and lower 16 bits. Two buffer circuits (44) (46),
A first latch circuit (42) for temporarily storing upper 16-bit data in the second data bus (16),
The control unit (20) further includes a determination circuit (28),
The determination circuit (28) checks whether the read address output from the CPU (14) is divisible by “4”.
If it is not divisible by “4”, it is determined that the upper 16-bit data is read access, the corresponding address in the I / O circuit (18) is read-accessed, and the first buffer circuit (44) is used for the first access. The data read operation by 16-bit access is completed by sending the upper 16-bit data in the data bus (16) of 2 to the CPU (14).
When it is divisible by “4”, 32 bits of data are read from the I / O circuit (18) at a time, and the lower 16 bits of the read 32 bits of data are read out from the second buffer circuit (46). At the same time, the upper 16 bits of data are controlled to be held in the first latch circuit (42).
Further, if the reading of data for addresses consecutive to the reading address output from the CPU (14) is not confirmed, the reading operation ends. However, if confirmed, the higher order held in the first latch circuit (42). A bus bridge circuit which outputs 16-bit data to the CPU (14). A bus bridge between a CPU (14) having a data bus width of 16 bits and an I / O circuit (18) having a data bus width of 32 bits and enabling a data transfer operation corresponding to the difference in the data bus width A circuit,
A control unit (20) for analyzing the contents of address data and control signals sent from the CPU (14) and sending predetermined address data and control signals to the I / O circuit (18);
A data writing section (24) that operates at the time of data writing from the CPU (14) to the I / O circuit (18) and enables the data bus width to be expanded;
The data writing unit (24)
Between the first data bus (12) on the CPU (14) side and the second data bus (16) on the I / O circuit (18) side, the lower 16 in the first data bus (12) A second latch circuit (48) capable of temporarily storing bit data, and a fourth buffer circuit (52) capable of regulating the output timing of upper 16 bits of data on the first data bus (12) . While comprising
The control unit (20) further includes a determination circuit (28),
The determination circuit (28) checks whether the write address by the CPU (14) is divisible by “4”,
If it is not divisible by “4”, it is determined that the upper 16-bit data is a write access, and the upper 16-bit data is sent to the second data bus (16) via the fourth buffer circuit (52). The data write operation by 16-bit access is completed by performing write access to the corresponding address in the I / O circuit (18).
When it is divisible by “4”, control is performed to hold the lower 16 bits of data in the second latch circuit (48).
Further the writing of the data is confirmed for continuous addresses in the outputted write address from said CPU (14), the data held in the second latch circuit (48) and the lower 16 bits of the data, when the The 32-bit data, which is the upper 16 bits of data output from the CPU (14) through the fourth buffer circuit (52) , is simultaneously output to the I / O circuit (18). While having write access
A bus bridge characterized in that when writing data to consecutive addresses is not confirmed, only the lower 16 bits of data held in the second latch circuit (48) are sent to the I / O circuit (18). circuit. A bus bridge between a CPU (14) having a data bus width of 16 bits and an I / O circuit (18) having a data bus width of 32 bits and enabling a data transfer operation corresponding to the difference in the data bus width A circuit,
A control unit (20) for analyzing the contents of address data and control signals sent from the CPU (14) and sending predetermined address data and control signals to the I / O circuit (18);
The work from the CPU (14) the I / O circuit according to (18) at the time of data reading from the CPU (14), the data reading unit which allows a reduction in the data bus width (22),
A data writing section (24) that operates at the time of data writing from the CPU (14) to the I / O circuit (18) and enables the data bus width to be expanded;
The data reading unit (22)
Between the first data bus (12) on the CPU (14) side and the second data bus (16) on the I / O circuit (18) side, from the second data bus (16) to the first data bus (16). To the data bus (12), the output timing of the data of the bus width defined by the first data bus (12) can be individually regulated by upper 16 bits and lower 16 bits. Two buffer circuits (44) (46),
A first latch circuit (42) for temporarily storing upper 16-bit data in the second data bus (16),
The control unit (20) further includes a determination circuit (28),
The determination circuit (28) checks whether the read address output from the CPU (14) is divisible by “4”.
If it is not divisible by “4”, it is determined that the upper 16-bit data is read access, the corresponding address in the I / O circuit (18) is read-accessed, and the first buffer circuit (44) is used for the first access. The data read operation by 16-bit access is completed by sending the upper 16-bit data in the data bus (16) of 2 to the CPU (14).
When it is divisible by “4”, 32 bits of data are read from the I / O circuit (18) at a time, and the lower 16 bits of the read 32 bits of data are read out from the second buffer circuit (46). At the same time, the upper 16 bits of data are controlled to be held in the first latch circuit (42).
Further, if the reading of data for addresses consecutive to the reading address output from the CPU (14) is not confirmed, the reading operation ends. However, if confirmed, the higher order held in the first latch circuit (42). 16-bit data is output to the CPU (14),
The data writing unit (24)
Between the first data bus (12) on the CPU (14) side and the second data bus (16) on the I / O circuit (18) side, the lower 16 in the first data bus (12) The second latch circuit (48) capable of temporarily storing bit data, and the output timing of the bus width data defined by the first data bus (12) are expressed by the lower 16 bits and the upper 16 bits. While including the third and fourth buffer circuits (50) and (52) that can be individually regulated,
The control unit (20) further includes a determination circuit (28),
The determination circuit (28) checks whether the write address by the CPU (14) is divisible by “4”,
If it is not divisible by “4”, it is determined that the upper 16-bit data is a write access, and the upper 16-bit data is sent to the second data bus (16) via the fourth buffer circuit (52). The data write operation by 16-bit access is completed by performing write access to the corresponding address in the I / O circuit (18).
When it is divisible by “4”, control is performed to hold the lower 16 bits of data in the second latch circuit (48).
Further, when it is confirmed that data is written to an address continuous to the write address output from the CPU (14), the data held in the second latch circuit (48) is used as lower 16-bit data. 32-bit data, which uses the data output from the CPU (14) as upper 16-bit data via the fourth buffer circuit (52), is simultaneously output to the I / O circuit (18). While having write access,
A bus bridge characterized in that if writing of data to consecutive addresses is not confirmed, only the lower 16 bits of data held in the second latch circuit (48) are sent to the I / O circuit (18). circuit.

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