JPH02217923A - Data processor - Google Patents

Abstract

PURPOSE:To shorten a waiting time required after executing a branch instruction by allowing an instruction word reading part to read out the succeeding instruction word at the succeeding clock when an instruction decoding part decides the branch instruction. CONSTITUTION:When the instruction decoding part 3 decides a branch instruction, a branch objective instruction cache memory 8 receives an operand address specifying part consisting of a direct instruction word modification register number part 12 and an operand address deforming part 13 from the decoding part 3 and sends the copy of a part of the contents stored in a storage means 1 to the decoding part 3 based upon the operand address specifying part. Thereby, a branch objective instruction can be quickly read out from the memory 8. Consequently, the waiting time required after executing the branch instruction can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that performs processing using a vibe line method, and particularly to a data processing device that has improved branch instruction processing.

[Prior art] Figure 4 shows a pipe diagram in a conventional data processing device of this type.
It shows one stage of the line, and in the figure, (1) is a storage means (MEN) in which stored contents such as data and command words are stored, and (2) is the next execution stage stored in this storage means. Instruction word reading unit (IF) that reads out the instruction word to be used
, (3) is an instruction decoding unit (IDC) that interprets the instruction word read by this instruction word reading unit, and (4) performs operand access in response to instructions from the instruction word interpreted by this instruction decoding unit. Calculates and outputs the operand address as the required logical address, and
An operand address calculation unit (OAC) that generates a jump address of the branch instruction, which is a logical address, when the instruction word is determined to be a branch instruction by the instruction decoding unit (3).
, (5) is an address translation unit (TRN) that converts the logical operand address and logical jump address from this operand address calculation unit into physical addresses, respectively.
When receiving a logical jump address and reading out a command word at an address following the jump address, the jump address as a physical address and the command word corresponding to the physical jump address are read from the storage means (1). It is given to the instruction word reading unit (2) in order to perform the instruction. (6) receives the physical operand address from this address translation section, and
An operand access control unit (OP) that accesses the storage means (1) according to an address reads data stored at an address according to a physical operand address of the storage means (1) according to an instruction to be executed. (7) is an execution unit that processes the data read from the storage means (1) by this operand access control unit and outputs data to be written to the storage means (1). (EX[J), (
8) is a branch target instruction cache memory (1) which is a type of cache memory and has a structure that is referenced by a logical address and stores a copy of a part of the memory contents of the storage means (1). BGM) receives a logical jump address from the operand address calculation unit (4), and stores a copy of a part of the memory contents of the storage means (1) corresponding to this logical jump address. , sends a copy of a portion of this stored memory content to the instruction decode (3),
If it is not stored, this logical jump address is registered, and the storage means (1) corresponding to this logical jump address read from the instruction word reading section (2) is stored.
Stores part of the memory contents of. (9) is a signal line for transmitting the logical jump address from the operand address calculation unit (4) to the branch target instruction cache memory (8).

As shown in FIG. 5, the instruction word stored in the storage means (1) includes an instruction code section (10) that specifies the action of the instruction word.
, an operand address number section (R) (11) that specifies the number of the register that is the target of the operation of the instruction word, and an operand address number section (R) (11) that specifies the memory address required for the operation specified by the instruction code section (10). Qualification register section (I>(12)
and an operand address designation section consisting of an operand address displacement section (DSP) (13). And to find the memory address from this operand address.

The contents of the modification register with the number specified by the modification register number part (12) and the operand address displacement part (13)
).

Next, the operation of the data processing apparatus configured in this manner will be explained. First, a case where the instruction code part (lO) of the instruction word to be read does not specify a branch instruction will be described. The instruction word to be executed next is read from the storage means (1) by the instruction word reading section (2). This read instruction word is input to an instruction decoding section (3) and interpreted, that is, the instruction code section (10) of the instruction word is read. The operand address calculation unit (4), which receives instructions from this interpreted instruction word, calculates the operand address as a logical address necessary for operand access, that is, specifies it in the qualified register number section (12) of the instruction word. The contents of the modified register numbered and the operand address displacement part (13)
The logical operand address is determined by adding the value of .

This logical operand address is the address translation unit (5)
The address is converted into a physical operand address and input to the operand access control unit (6). The operand access control unit (6) accesses the storage means (1) using this physical operand address. That is,
If the instruction to be executed by the instruction code section (10) of the instruction word interpreted by the instruction decoding section (3) is an instruction that requires reading data, the operand access control section (6) The execution unit (7) reads data from the storage means (1) according to the physical operand address.
This data is processed by the execution unit (7). Further, the instruction to be executed by the instruction code section (10) of the instruction word interpreted by the instruction decoding section (3) is an instruction that requires writing the execution result into the storage means (1), so to speak.
The operand access control section (6) writes the output of the execution section (7) into the storage means (1) using the physical operand address, and a series of operations proceed in this manner. This series of operations is shown in a time chart as shown in FIG.

In FIG. 6, the horizontal axis shows time and the vertical axis shows each stage of the pipeline.Instructions A and B do not require writing of operand data.

It shows how C is continuously pipelined.

Next, a case will be described in which there is a branch instruction in the instruction code section (1o) of the read instruction word. Instruction word reading section (2
) Instruction code part (10) of the instruction word read by
When the instruction decoding unit (3) determines that it is a branch instruction, the operand is determined by the instruction decoding unit (3).
The address calculation section (4) is the instruction word modification register number section (
The contents of the modification register with the number specified in step 12) and the value of the operand address displacement section (13) are added to generate a logical jump address, which is a branch instruction. This logical destination address is a signal! (9) to the branch target instruction cache memory (8). If a copy of a part of the memory contents of the storage means (1) corresponding to the input logical jump address is stored in this branch target instruction cache memory (8), one copy of the stored memory contents may be stored in the branch target instruction cache memory (8). A copy of the copy is sent to the instruction decoding section (3), and instruction processing from the destination address is started. Processing based on the instruction word at the address following this destination address is performed by the instruction word succession unit (2).
, the instruction decoding unit (3), the operand address calculation unit (4), the address translation unit (5), the operand access control unit (6), and the execution unit (7) process the instruction words that do not have the above-mentioned branch instruction. Processed in the same way as the based processing. On the other hand, if a copy of a part of the memory contents of the storage means (1) corresponding to the logical jump address inputted to the branch target instruction cache memory (8) is not stored, this logical jump address will be converted into an address. It is converted into a physical destination address in section (5).

This physical jump address is sent to the instruction word reading unit (2).

This instruction word successive section (2) reads the memory contents from the storage means (1) according to the physical jump address, stores the memory contents in the branch target instruction cache memory (8) as a copy of a part of the memory contents, and , the logical jump address from the operand address calculation unit (4) is stored as registration information. At the same time, the read memory contents are sent to the instruction decoding section (3), and instruction processing from the destination address is started. Processing based on the instruction word at the address following this jump address is performed by the instruction word reading section (2), instruction decoding section (3), operand address calculation section (4), address conversion section (5), operand access The control unit (6) and the execution unit (7) process the instruction word in the same way as the above-mentioned instruction word without a branch instruction. A series of operations proceed in this manner. This series of operations is shown in a time chart in the case where a copy of a part of the memory contents corresponding to the logical jump address in the branch processing is stored in the branch target instruction cache memory (8). It becomes like this. This figure 7 shows time on the horizontal axis and each stage of the pipeline on the vertical axis, and shows instructions A, B, C1, branch instructions BR, and branch instructions that do not require writing operand data. This shows how instructions E and F, which do not require writing after instruction execution, are sequentially processed in a pipeline. In particular, the instruction is an instruction stored at the destination address. As is clear from FIG. 7, when the instruction decoding unit (1) determines a branch instruction, the instruction word reading unit ( Since the next instruction word is read in step 2), a waiting time of two clocks is required after execution of the branch instruction.

In addition, as a data processing device similar to the conventional pipeline type data processing device mentioned above,
No. 45, JP-A-57-34254, JP-A-Sho. 5
Publication No. 8-1.29660 and JP-A-57-85148
It is shown in the publication No.

[Problems to be Solved by the Invention] In the conventional data processing device configured as described above, when the instruction decoding unit (3) determines that the instruction is a one-branch instruction, the operand address calculation unit (4) Since the branch destination instruction is executed after finding the logical jump address based on the operand address specification part of was there.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to obtain a pipeline type data processing device that shortens the waiting time after execution of one branch instruction.

[Means for Solving the Problems] A pipeline data processing device according to the present invention includes an instruction code section that specifies the action of an instruction word, and a memory address that specifies the action specified by the instruction code section. When the instruction word is determined to be a branch instruction, it receives the operand address specification part of the instruction word from the instruction decode unit that interprets the instruction word having the operand address specification part, and responds and stores the instruction word based on this operand address specification part. A branch target instruction cache memory is provided for sending a copy of a portion of the stored contents of the storage means to the instruction decoding section.

[Function] In the present invention, when the instruction decoding unit determines that the instruction is a branch instruction, the one-branch target instruction cache memory receives the operand addressing part of the instruction word directly from the instruction decoding unit, and receives the operand addressing part of the instruction directly from the instruction decoding unit. A copy of a portion of the stored contents of the storage means is sent to the instruction decoding section based on the instruction decoding section.

To shorten the waiting time after executing a branch instruction.

[Embodiment] An embodiment of the present invention will be described below based on FIG. 1. In FIG. ) is an instruction reading unit (IF) that reads out the next instruction to be executed stored in this storage means, and (3) is an instruction decoding unit (ID) that interprets the instruction read by the instruction successive unit.
C) and (4) receive instructions from the instruction word interpreted by this instruction decoding unit, calculate and output an operand address as a logical address necessary for operand access, and are also processed by the instruction decoding unit (3). An operand address calculation unit (OAC) generates a jump address of the branch instruction, which is a logical address, when the instruction word is determined to be a branch instruction. (5) calculates the logical operand address and The address translation unit (TRN) that converts each logical jump address into a physical address receives the logical jump address, and when reading the instruction word at the address following the jump address, converts the jump address as a physical address, A command word corresponding to the physical jump address is given to the command reading unit (2) in order to read it from the storage means (1). (6) receives the physical operand address from this address translation section,
By this physical operand address, the storage means (1
) Operand access control unit (OP) that accesses
According to the instruction to be executed, reading and writing of data stored in the address according to the physical operand address of the storage means (1) is performed.

(7) is an execution unit (EXU) which processes the data read from the storage means (1) by this operand access control unit and outputs data to be written into the storage means (1); 8) is a branch target instruction cache memory (1) which is a type of cache memory and has a structure that is referenced by a logical address and stores a copy of a part of the memory contents of the storage means (1). B.G.
M) receives an operand address designation part consisting of an instruction word modification register part (12) and an operand address displacement part (I3) shown in FIG. 5 from the output from the instruction decode part (3). , by using the relationship between this operand address specification part and the memory address.
If a copy of a part of the memory contents of the storage means (1) is stored based on the address designation part, the copy of the stored part of the memory content is sent to the instruction decode (3).

If it has not been stored, register this operand address specification section, and also register the instruction word succession section (2).
A part of the storage contents of the storage means (1) corresponding to this operand address designation section read from is stored. The reason why it can be used as a logical address to refer to the operand address specification section in this way is that the destination address of a branch instruction is the contents of the modification register of the number specified by the modification register number section (12) of the instruction word and the operand address.・Since it is the addition of the value of the address displacement part (13),
As long as the contents of the qualified register do not change, the memory can be accessed only by the operand address specification part, that is, the qualified register number part (12) and the operand address displacement part (13).
This is because the address is uniquely determined.
(91) is a signal line for transmitting the operand address designation part of the instruction word from the instruction decoding section (3) to the branch target instruction cache memory (8).

Next, the operation of the data processing apparatus configured in this manner will be explained. First, a case where the instruction code section (10) of the instruction word to be read does not specify a branch instruction will be explained. The instruction word to be executed next is read out from the storage means (1) by the instruction word succession unit (2). This read instruction word is input to an instruction decoding section (3) and interpreted, that is, the instruction code section (10) of the instruction word is read. In response to instructions from this interpreted instruction word, the verando address calculation section (4) calculates the operand address as a logical address necessary for operand access, that is, the instruction word's qualified register number section (12). The contents of the modification register number specified by and the operand address displacement part (13
) to find the logical operand address. This logical operand address is determined by the address translation unit (5
) is converted into a physical operand address and input to the operand access control unit (6). The operand access control unit (6) accesses the storage means (1) using this physical operand address. That is, if the instruction to be executed by the instruction code section (10) of the instruction word interpreted by the instruction decoding section (3) is an instruction that requires data reading, the operand access control section (6) The execution unit (7) reads the data from the storage means (1) according to the physical operand address.
), and this data is processed by the execution unit (7).

Further, if the instruction to be executed by the instruction code section (10) of the instruction word interpreted by the instruction decoding section (3) is an instruction that requires writing the execution result into the storage means (1), the operand access control section (6) stores the output of the execution unit (7) in the storage means (1) by physical operand address.
The output of the execution unit (7) is written to the . This is how a series of operations proceed.

Next, a case will be described in which there is a branch instruction in the instruction code section (lO) of the read instruction word. Instruction word reading section (2
) Instruction code part (10) of the instruction word read by
When the instruction decode unit (3) determines that it is a branch instruction, the instruction word's modification register number part (12) and the operand
An operand addressing section consisting of an address displacement section (13) is input to the branch target instruction cache memory (8) via a signal line (91). The operand address specification part of the instruction word input to this branch target instruction cache memory (8) functions as a logical supplementary address, and a copy of a part of the memory contents of the corresponding storage means (1) is stored. If so, a copy of this part of the stored memory contents is sent to the instruction decoding section (3), and instruction processing from the destination address is started. Processing based on the instruction word at the address following this jump address is performed by the instruction word successive section (2), instruction decoding section (3), operand address calculation section (4), address conversion section (5), and operand access section. The control unit (6) and execution unit (7) perform the same processing as the above-described processing based on an instruction word without a branch instruction. On the other hand, if a copy of a part of the memory contents of the storage means (1) corresponding to the operand address specification part of the instruction word inputted to the 1-branch target instruction cache memory (8) is not stored, this operand address The operand address calculation section (4) calculates the logical jump address using the specification section. This logical jump address is converted into a physical jump address by the address conversion unit (5), and this physical jump address is sent to the instruction word reading unit (2), which The stored contents are read from the storage means (1) according to the address, and the stored contents are stored in the branch target instruction cache memory (8) as a copy of a part of the stored contents, and the operand address designation part of the instruction word is registered in the register information. Store as . At the same time, the read memory contents are sent to the instruction decoding section (3), and instruction processing from the destination address is started. Processing based on the instruction word at the address following this destination address is performed by the instruction word reading unit (
2) Instructions that do not have the above-mentioned branch instructions in the instruction decoding unit (3), operand address calculation unit (4), address translation unit (5), operand access control unit (6), and execution unit (7) Processed in the same way as words. A series of operations proceed in this manner. This sequence of operations is shown in a time chart for the case where a copy of a part of the memory contents corresponding to the operand address specification part of the instruction word in branch processing is stored in the branch target instruction cache memory (8). and as shown in Figure 2. This figure 2 shows time on the horizontal axis and each stage of the pipeline on the vertical axis, and shows instructions A, B, and C1 that do not require writing operand data, branch instructions BR, and branch instruction execution. Instructions that do not require subsequent writing, E.

It shows how F is continuously processed by the vibe line. As is clear from FIG. 2, the instruction decoding section (3
), when a branch instruction is determined, instruction 81 is executed at the primary clock.
! Since the next instruction word is read at the output section (2), the waiting time after execution of one branch instruction is reduced by one crotch compared to the conventional system shown in Fig. 7, and the processing time can be shortened. It is something.

Next, a specific configuration example of the 1-branch target instruction cache memory (8) is shown in which the instruction word modification register number part (12) is 2b.
it, operand address displacement part (13) is 8 bits
The case will be explained based on FIG. 3. In the figure, (21a) is the write signal IRV to the modification register via the signal IIA (21). Signal line (22a) (22b
) is the register digital number IRAO that indicates the register number when writing to the modified register in 2 bits.
.

A first logic means to which IR, 41 is input as an inverted signal.

(21b) represents the write signal IRv, the register digital number IRAI, and the register digital number I.
a second logic means inputted with RAO as an inverted signal; (
21c) is a third logic means which receives the write signal IRV, the register digital number IRAO, and the register digital number IRA1 as inverted signals; (21d)
) is the write signal IRV and the register digital number IRA
a fourth logic means into which O5IflA1 is input, (14a
) to (14d) are the upper 4 bits D of the operand address displacement part (13) of the instruction word via the signal line (lab).
Address input terminal A to which SP (4 to 7) is input, and data input to which lower 4 bitosp (o to 3) of the operand address displacement part (13) of the instruction word is input via the signal line (18a). Each of the first to fourth tag arrays is constituted by a memory array having a terminal I, a data output terminal O, a write instruction signal input terminal W, and a clear instruction signal input terminal C. The clear instruction signal input terminal C has the first to
The outputs of the second logic means (21a) to (21d) are respectively input, and when the clear instruction signal input terminal C becomes significant, all contents are erased. (15a) to (15d) are the output 0 of these first to fourth tag arrays (14a) to (14d) and the lower 4 of the operand address displacement part (13).
The first to fourth comparators (17a) that compare bit DSP (0 to 3) receive the outputs from these first to fourth comparators, and also
A first multiplexer to which bits IO and II are input via signal lines (23a) (23b), and 2bit I
O, It outputs one of the first to fourth comparators. (16a) to (16d) are signal lines (
18b) via the operand address displacement part (13)
An address input terminal A to which the upper 4 bits of DSP (0 to 3) are input, a data input terminal to which data from the storage means (1) is input, an output terminal O, and a write instruction signal input terminal W. (17b) is the output O of these first to fourth data arrays and 2 bits of the modification register number part (12) of the instruction word. The second multiplexer to which l01II is input, the first to fourth multiplexers are input by 2bLtIo,
One of the data arrays (16a) to (16d) is output to the instruction decoding section (3). (24) is the 2 bits of the instruction word modification register number part (12): 1
0. Il is input and the first to fourth tag arrays (
14, a) to (14d) and the first to fourth data arrays (16a) to (16d).

Branch 1 instruction cache memory configured in this way (
The operation of 8) will be explained. When the instruction decode unit (3) determines that the instruction is a branch instruction and the operand address specification part of the instruction word is input to the branch target instruction cache memory (8), 2bit IO1 of the modification register number part (12)
The controller (24) controls one of the first to fourth tag memories (14a) to (14d) and the first to fourth tag memories (14a) to (14d).
One of the data arrays (16a) to (16d) is selected and the contents of the selected tag memory are compared by a comparator. If the comparison results match, the control section (24) controls the contents of the data array corresponding to the number in the modification register number section (12) via the first multiplexer (17a), that is, the storage means (1 ) as a second copy of the data.
The instruction decoding unit (
3). On the other hand, comparators (1, 4a) to (14
If the comparison result according to d) does not match, the control unit (24)
The first to fourth data arrays (16a) to (16
d) is not selected, and the data is stored in the instruction decode section 3.
), the data read from the storage means (1) using the physical address output by the address translation unit (5) is stored in the data array, and the operand
The upper 4 bits of the address displacement part (13) are stored in the tag array as registration information. Furthermore, in this branch target instruction cache memory (8),
Unless the contents of the qualification register are changed, the contents of the destination address storage means (1) are uniquely determined by the operand address specification part of the instruction word, so the contents of the qualification register will not change. , the register number at the time of writing the modification register is expressed in 2 bits I
RAOlIRAI is indicated and the write signal lRb1 to the modification register becomes significant, so the corresponding tag
All contents of the array will be erased.

In this invention, one of the specific configurations is to copy a part of the data stored in the destination address which is a branch instruction among the memory contents stored in the storage means and to branch to this destination address. A branch target instruction cache memory that holds the part that specifies the jump address of the instruction word that becomes the branch instruction to be executed, that is, the operand address designation part, as the registered information of the copy; means for determining whether or not a copy of the contents corresponding to the jump address of the storage means is stored in the memory from a part specifying the jump address of the instruction word of the branch instruction; means for using a copy of the destination address as a destination instruction word when it is determined that a copy corresponding to the destination address is stored in the branch target instruction cache memory; If it is determined that the jump address is not stored in the memory, the content corresponding to the jump address obtained from the part that specifies the jump address of the branch instruction is read from the storage means, and the content is branched together with the part that specifies the jump address of the branch instruction. A means for storing in a target instruction cache memory, a means for detecting whether the contents of a register used when obtaining a jump address from a part specifying a jump address of a 1-branch instruction has been changed, and a 5-branch target instruction cache memory. Data processing that is equipped with a means to delete all registered information in which the jump address specification part of the branch instruction required when finding the jump address is the register information that has been changed from among the registered information held. It's in the device.

[Effects of the Invention] As described above, the present invention has an instruction code section that specifies the action of an instruction word, and an operand address specification section that specifies the memory address required for the action specified by the instruction code section. When the instruction decoding unit that interprets the instruction word determines that it is a two-branch instruction, the operand of the instruction word
A branch target instruction cache memory is provided which receives the addressing section and sends a copy of a portion of the stored contents of the storage means corresponding to the operand addressing section to the instruction decoding section. .

This has the advantage that a branch target instruction can be quickly read from a branch target instruction cache memory, the waiting time after execution of a branch instruction can be shortened, and a data processing device with high processing performance can be obtained.

[Brief explanation of the drawing]

Figures 1 to 3 show one embodiment of the present invention.
The figure is a block diagram showing one stage of the pipeline, and Figure 2 is a timing chart showing a series of operations.
FIG. 3 is a block diagram showing an example of a branch target instruction cache memory (8), FIG. 4 is a block diagram showing one stage of a conventional data processing device, and FIG. 5 shows the format of an instruction word. FIGS. 6 and 7 are timing charts showing the series of operations shown in FIG. 4. In the figure, (1) is the storage means, (2) is the instruction word succession unit, (3) is the instruction decode unit, (4) is the operand address calculation unit, (5) is the address translation unit, and (6) is the operand・Access control section, (7) is the execution section, (8) is the branch target instruction cache memory, (10) is the instruction code section of the instruction word, (12) and (13) are the operand address specification section of the instruction word. These are a qualified register number part and an operand address displacement part. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] Storage means for storing storage contents such as instruction words and data, which has an instruction code section that specifies the action of the instruction word, and an operand address specification section that specifies the memory address required for the action specified by the instruction code section. , an instruction word reading unit that reads out the instruction word stored in this storage means, an instruction decoding unit that interprets the instruction word read by this instruction word reading unit, and an operand address designation part of the instruction word as registered information. A copy of a part of the memory contents of the storage means is stored, and when the instruction decoding section determines that the instruction word is a branch instruction based on the instruction code of the instruction word, it receives the operand address designation part of the instruction word from the instruction decoding section and reads this operand. - A data processing device comprising a branch target instruction cache memory which sends a copy of the corresponding and stored portion of the stored contents of the storage means based on the addressing section to the instruction decoding section.