JP2007304818A - Image processor and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a configuration and speeding up processing in an image processor executing a plurality of pieces of image processing. <P>SOLUTION: Line identification information showing sections of a line is embedded in image data. The image processor includes a plurality of image processing blocks 132 executing prescribed image processing, and each of the blocks 132 includes an additional information extraction block B1, an image processing execution block B2 and additional information re-addition block B3. The block 132 recognizes line identification information and deletes the information from the image data at the block B1, and then, executes prescribed image processing at the block B2. In executing the image processing, the identification information recognized at the block B1 is utilized. The block 132 embeds the identification information again in the image data to which the image processing is executed to output the image data to the subsequent stage at the block B3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for executing a plurality of different image processes in an image processing apparatus.

  Some image processing apparatuses using an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) can execute a plurality of image processing. In addition, some image processing executed by the image processing apparatus requires parameters corresponding to the respective processing (for example, magnification or the like in the case of enlargement / reduction processing). Such parameters are written in a register corresponding to a processing block that executes each image processing, and each image processing is started after the writing to the register is completed.

  An example of the configuration of a conventional image processing apparatus is shown in FIG. As shown in the figure, the image processing apparatus 900 includes an image input unit 910, a register setting unit 920, an image processing unit 930, a buffer unit 940, and an image output unit 950. In this configuration, the register setting unit 920 is realized by a CPU (Central Processing Unit), and the image processing unit 930 is realized by an ASIC. In such an image processing apparatus 900, the register setting unit 920 is connected to each processing block (input IF 931, image processing blocks 932 a to 932 c, and image processing unit 930) via the register IF (interface) unit 934 of the image processing unit 930. It is necessary to write parameters to the registers 935a to 935e corresponding to the output IF 133).

In addition, when the image processing block performs a process of referring to a plurality of lines of image data such as a filter process, a line buffer as shown in FIG. 10 is necessary. In order to properly store the image data of each line in the line buffer, it is necessary to correctly recognize the line and page break of the image data. Therefore, the image processing unit 930 is supplied with a line synchronization signal indicating a line break and a page synchronization signal indicating a page break via a signal line different from a signal line supplying image data. Further, in the image processing blocks 932a to 932c, it is necessary to count pixel data using the pixel counters 936a to 936c and specify the line or page break.
JP 2003-304381 A

  However, in the image processing apparatus having the above-described configuration, in order to execute each image processing, it is necessary to wait for the CPU to write to the register, so that the processing is delayed. Further, since an IF for writing to the register and a signal line for inputting a line synchronization signal / page synchronization signal are necessary, the package size of the image processing unit (that is, ASIC or the like) is increased, and the cost is increased. There were also inconveniences.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique for enabling simplification of the configuration and speeding up of processing in an image processing apparatus that executes a plurality of image processing. It is in.

  In order to achieve the above-mentioned object, the present invention provides an information adding means for embedding additional information used for image processing to be executed for image data composed of inputted pixels of a plurality of rows and a plurality of columns in the image data, An image processing unit that recognizes additional information embedded in the image data by the information adding unit and executes the image processing on the image data using the additional information, and an image on which the image processing is performed by the image processing unit An image processing apparatus including an output unit that outputs data is provided.

  In the present invention, the image processing means includes a plurality of image processing units that execute different image processes, and at least one of the plurality of image processing units extracts the additional information from the image data. Using the additional information deleted from the image data by the extraction unit, a processing execution unit for performing image processing on the image data from which the additional information has been deleted, and image processing by the processing execution unit. It is desirable to include a supply unit that adds information corresponding to the additional information deleted by the extraction unit to the executed image data and supplies it to the subsequent image processing unit.

  Alternatively, in the present invention, the image processing unit includes a plurality of image processing units that execute different image processes, and the information adding unit uses a parameter used for each of the plurality of image processing units as the additional information. It is desirable that the structure be embedded. Further, at least one of the plurality of image processing units includes a recognition unit that recognizes a parameter included in additional information embedded in the image data, and a parameter used by the recognition unit for the parameter recognized by the recognition unit. A processing execution unit that performs image processing on the image data using the parameter, and a supply unit that deletes a parameter used in the processing execution unit from the additional information and supplies the parameter to the subsequent image processing unit A configuration is more preferable.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, two embodiments will be described as examples of the image processing apparatus according to the present invention. These image processing apparatuses are mounted on an image forming apparatus such as a copying machine or a color printer. In the following two embodiments, different image processing apparatuses are described, but it is also possible to carry out by appropriately combining these.

  Further, for convenience of explanation, in the embodiment described below, pixel data is data having 8-bit gradation (that is, 256 gradations for each color) for each color of red (R), green (G), and blue (B). Suppose that That is, the image data in the following embodiments is so-called 24-bit color full-color image data. In the following description, the color of pixel data is indicated by a 6-digit hexadecimal value. The notation is distinguished from a decimal number by adding “0x” to the head in accordance with a notation method such as C language. For example, the value expressed as “0x000000” represents the gradation of R in the first and second digits, the gradation of G in the third to fourth digits, and the gradation of B in the fifth to sixth digits. This represents that the color of the pixel data described in is “black”. Similarly, for example, values represented as “0xffffff” and “0xff0000” represent that the color of the pixel data is “white” and “red”, respectively.

[First Embodiment]
FIG. 1 is a functional block diagram showing a functional configuration of an image processing apparatus 100 according to the first embodiment of the present invention. As shown in the figure, when the configuration of the image processing apparatus 100 is classified by function, it is roughly divided into an image input unit 110, an information adding unit 120, an image processing unit 130, a buffer unit 140, and an image output unit 150. Is done.

  The image input unit 110 is an interface unit for acquiring image data from an input device such as a scanner or a computer, and realizes a function of supplying image data to the image processing device 100. Here, the image data is a set of data representing one page by arranging pixel data each representing a predetermined color tone and gradation in a matrix. That is, the image data is data obtained by arranging a plurality of pixel data in the row direction and the column direction. The image input unit 110 sequentially supplies such image data as a one-dimensional data string from the first row.

  The information adding unit 120 realizes a function of embedding additional information in the image data supplied from the image input unit 110. The function of the information adding unit 120 is realized, for example, when the CPU executes a predetermined program. Here, the additional information is information representing a line break or page break of image data. The additional information is embedded at predetermined intervals in the data string representing the image data.

  FIG. 2 is a conceptual diagram showing image data in which additional information is embedded in the present embodiment. In the figure, D1, D2, and D3 represent the image data of the first row, the second row, and the third row, respectively. L1, L2, and L3 respectively represent “line identification information” indicating the end of the image data of the first row, the second row, and the third row, and P1 indicates “page identification indicating the end of the image data. Information ". This line identification information and page identification information correspond to “additional information” in the present embodiment. Although not shown in the figure, the line identification information indicating the separation is embedded between the image data of each row in the same manner for the fourth and subsequent rows as well. The line identification information corresponds to a line synchronization signal (line sync), and the page identification information is additional information corresponding to a page synchronization signal (page sync). Further, by embedding page identification information, it is possible to recognize a break between image data of different pages.

  Each of the line identification information and the page identification information is data corresponding to a pattern of a predetermined number of pixels (in this embodiment, “4”). It can be identified. Further, the line identification information and the page identification information can be distinguished from the image data by using pixel patterns that cannot be generated in normal image data. For example, a sudden change in the adjacent pixel data from “black (0x000000)” to “white (0xffffff)” hardly occurs in normal image data. Therefore, in the present embodiment, such a combination of gradation changes is used as additional information. Specifically, for example, the line identification information is a combination of pixel data for four pixels “black, white, black, white”, and the page identification information is a pixel for four pixels “white, black, white, black”. A combination of data may be used.

  Returning to the description of FIG. The image processing unit 130 realizes a function of executing a plurality of predetermined image processes. This function is realized by, for example, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). More specifically, the image processing unit 130 is classified into an input IF 131, image processing blocks 132a, 132b, and 132c, and an output IF 133.

  The input IF 131 and the output IF 133 are interface (InterFace) units for the image processing unit 130 to input and output image data. The input IF 131 and the output IF 133 write information about image processing and image data in the buffer unit 140, or read information from here. The buffer unit 140 is configured by a memory such as a RAM (Random Access Memory) and implements a function of temporarily storing necessary data.

  The image processing blocks 132a to 132c execute different image processing. Note that image processing performed in the image processing blocks 132a to 132c is not particularly limited, and examples thereof include color conversion processing, compression / expansion processing, enlargement / reduction processing, and filter processing. Further, in the following description, when there is no need to particularly distinguish the image processing blocks 132a to 132c, the notation “image processing block 132” is used as a generic term for these.

  FIG. 3 is a block diagram showing the configuration of the image processing block 132. As shown in the figure, the image processing block 132 is classified into an additional information extraction block B1, an image processing execution block B2, and an additional information re-addition block B3. The additional information extraction block B1 has a function of recognizing and deleting additional information embedded in image data. That is, the additional information extraction block B1 supplies the image data with the additional information extracted to the image processing execution block B2. The image processing execution block B2 has a function of executing predetermined image processing on the image data supplied from the additional information extraction block B1. The image processing execution block B2 refers to the additional information extracted by the additional information extraction block B1 as necessary, and executes image processing using this additional information. The additional information re-addition block B3 has a function of adding the additional information again to a predetermined position of the image data on which the image processing execution block B2 has executed the image processing, and supplying this image data to the subsequent image processing block. The reason why such a function is installed in the image processing block 132 is as follows.

  FIG. 4 is a conceptual diagram showing changes in the length (that is, capacity) of image data before and after various types of image processing. In the figure, D1 represents image data for one row before processing (hereinafter referred to as “line data”), and D1a, D1b, and D1c represent line data after processing. As shown in the figure, depending on the type of image processing, the length of the line data changes before and after that. For example, the line data becomes longer in the enlargement process, and the line data becomes shorter in the compression process. In particular, in the case of compression processing, the length of line data after processing is not necessarily constant depending on the algorithm, so the length of line data in each row after processing may vary. For this reason, when image data is output as a one-dimensional data string, it is impossible to recognize the delimitation without information indicating the delimitation of each line data, and it is impossible to perform appropriate image processing thereafter. Become.

  Further, even in image processing in which the length of image data does not change before and after processing, such as filter processing, the content of pixel data included in line data itself changes. Therefore, when the image processing execution block B2 executes the image processing while including the additional information, the content of the pixel data corresponding to the additional information is different from the original content, and it can be recognized that it is the additional information. Disappear. For these reasons, the image processing block 132 temporarily deletes additional information from the image data supplied to the image processing execution block B2. Further, for the convenience of processing in the subsequent image processing block, the image processing block 132 adds the additional information to the processed image data again.

  Returning to the description of FIG. The image output unit 150 is an interface unit for outputting image data, and realizes a function of supplying image data to the image forming apparatus. The image forming apparatus supplied with the image data from the image output unit 150 forms an image represented by the image data on a recording sheet.

  According to the image processing apparatus 100 configured as described above, since the line and page break of the image data can be recognized by the additional information (line identification information, page identification information), the CPU performs line synchronization with the image processing unit 130. There is no need to supply a signal or a page synchronization signal or to count pixel data for each image processing block. Therefore, according to the image processing apparatus 100, signal lines and terminals for supplying a line synchronization signal and a page synchronization signal are not required, and a pixel counter is not required, so that the apparatus is simplified and the package size is small. Can be realized.

[Second Embodiment]
Subsequently, a second embodiment of the present invention will be described. FIG. 5 is a functional block diagram showing a functional configuration of the image processing apparatus 200 of the present embodiment. As shown in the figure, when the configuration of the image processing apparatus 200 is classified by function, it is roughly divided into an image input unit 210, an information addition unit 220, an image processing unit 230, a buffer unit 240, and an image output unit 250. Is done. Among these, the functions of the image input unit 210, the buffer unit 240, and the image output unit 250 are substantially the same as the functions of the image input unit 110, the buffer unit 140, and the image output unit 150 of the above-described image processing apparatus 100, respectively. is there. Therefore, description of each of these parts is omitted here.

  The information addition unit 220 has a function of embedding additional information in the image data supplied from the image input unit 210, as in the information addition unit 120 described above. However, the information addition unit 220 of the present embodiment includes the additional information to be embedded. There are different parts of The information adding unit 220 is configured to embed header information necessary for image processing executed by the image processing unit 230 in image data, in addition to the information corresponding to the line identification information and page identification information described above. Details of the header information will be described later.

  The image processing unit 230 realizes a function of executing a plurality of predetermined image processes. More specifically, the image processing unit 230 is classified into an input IF 231, image processing blocks 232 a, 232 b and 232 c, and an output IF 233. The image processing blocks 232a, 232b, and 232c each execute predetermined image processing. The image processing performed in the image processing blocks 232a to 232c is not particularly limited, and examples thereof include color conversion processing, compression / expansion processing, enlargement / reduction processing, and filter processing. Hereinafter, the image processing performed by the image processing blocks 232a, 232b, and 232c is referred to as “image processing A”, “image processing B”, and “image processing C”, respectively. In the following description, when it is not necessary to distinguish the image processing blocks 232a to 232c in particular, the notation “image processing block 232” is used as a general term for these.

  FIG. 6 is a block diagram showing the configuration of the image processing block 232. As shown in the figure, the image processing block 232 is classified into an additional information extraction block b1, an image processing execution block b2, and an additional information re-addition block b3. The additional information extraction block b1 has a function of recognizing and deleting additional information embedded in image data. The image processing execution block b2 has a function of executing predetermined image processing on the image data supplied from the additional information extraction block b1. At this time, the image processing execution block b2 refers to the header information necessary for the own block among the additional information extracted by the additional information extraction block b1, and executes image processing using this header information. The additional information re-addition block b3 has a function of adding additional information again to a predetermined position of the image data on which the image processing execution block b2 has executed the image processing, and supplying this image data to the subsequent image processing block. At this time, the additional information re-addition block b3 is configured to exclude header information used by the image processing execution block b2, that is, header information necessary for the own block, and add additional information other than the header information. .

  Note that the input IF 231 and the output IF 233 of this embodiment have functions equivalent to the above-described additional information extraction block b1 and additional information re-addition block b3 in addition to the same functions as the input IF 131 and output IF 133 of the first embodiment. is doing. The input IF 231 and the output IF 233 write or read additional information such as header information and parameters in the buffer unit 240. The additional information written in the buffer unit 240 includes, for example, parameters that do not depend on individual processing blocks, parameters that are common to all processing blocks, and the like.

  Here, the parameter is setting information required when executing various image processing. For example, “magnification” corresponds to an example of a parameter for enlargement / reduction processing, and “compression rate (compression level)” corresponds to an example of a parameter for compression processing. As described above, information that does not depend on individual processing blocks is also included in the parameters. Examples of such parameters include the size and format of image data.

  FIG. 7 is a conceptual diagram showing image data in which additional information is embedded in the present embodiment. In the figure, D1, D2, and D3 represent the image data of the first row, the second row, and the third row, respectively. Pe1 represents “page identification information” indicating the end of the image data. The page identification information is embedded in the image data as a predetermined pixel pattern.

  Further, Hs, H1, and He at the head of the image data constitute additional information indicating “header information” as a whole. Among these, Hs and He are pixel patterns representing the start position and end position of the header information, respectively, and H1 is data such as a parameter which is the substantial content of the header information.

  The header information H1 includes a plurality of process IDs (ID1, ID2, ID3...) And corresponding parameters (P11, P12, P21, P31...). The process ID is identification information for uniquely specifying the image processing block 232, the input IF 231 or the output IF 233. That is, each processing ID corresponds to one of the image processing block 232, the input IF 231 and the output IF 233. Each process ID is associated with one or more parameters, and these parameters are used in the image processing block 232 corresponding to each process ID.

  Note that the “line identification information” of this embodiment also has a structure similar to the header information described above. Ls1 and Le1 are pixel patterns representing the start position and end position of the line identification information corresponding to the line data of the first row, respectively, and parameters (P1) are embedded so as to be sandwiched between these pixel patterns. ing. Such parameters are embedded when setting unique information for each line. This structure is the same for the line identification information corresponding to the line data of the second row (Ls2, P2, Le2) and the third row (Ls3, P3, Le3).

  Next, an operation when the image processing apparatus 200 executes image processing will be described. Here, the description will focus on the processing for the header information, and other processing will be omitted as appropriate. In the following description, the process IDs corresponding to the input IF 231, the image processing blocks 232 a, 232 b, 232 c and the output IF 233 are “ID1”, “ID2”, “ID3”, “ID4”, and “ID5”, respectively. Suppose that

  FIG. 8 is a diagram for explaining image data supplied to each unit of the image processing unit 230. In the figure, additional information other than the header information is omitted. That is, the data D shown in the figure includes line identification information and page identification information. As shown in the figure, the image data supplied to the input IF 231 includes all header information corresponding to the input IF 231, the image processing blocks 232 a to 232 c, and the output IF 233. The input IF 231 supplied with the image data specifies the process ID (ID1) corresponding to itself from the header information, and writes the parameters (P11, P12) associated with the process ID in the buffer unit 140. Then, the input IF 231 adds the processing ID used by itself and header information from which the parameters are deleted to the image data, and supplies the image data to the subsequent image processing block 232a.

  A part of the header information is deleted from the image data supplied to the image processing block 232a. This is because the header IF used by the input IF 231 which is the preceding processing block is deleted. The image processing block 232a specifies the processing ID (ID2) corresponding to itself from the header information of the image data, and executes the image processing using the parameter (P21) associated with the processing ID. Then, the image processing block 232a adds the processing ID used by itself and the header information from which the parameters are deleted to the image data, and supplies the image data to the subsequent image processing block 232b.

  Although the image processing block 232b differs in specific image processing contents, basically, the header information is referred to from the image data in the same procedure as the image processing block 232a described above, or the header information is added to the image data. Or perform actions. However, when the processing ID (ID3) corresponding to the own block is not included in the header information as shown in the figure, the image processing block 232b does not execute the image processing and the image data is left as it is. This is supplied to the subsequent image processing block 232c. Each of the image processing block 232c and the output IF 233 performs the same operation as the above-described input IF 231 and the image processing blocks 232a and 232b.

  By performing such an operation, the image processing apparatus 200 according to the present embodiment can execute image processing without writing parameters relating to individual image processing to a register. Therefore, the image processing apparatus 200 does not require a register or a signal line or a terminal for the CPU to write data into the register, so that the apparatus can be simplified and the package size can be reduced. In addition, according to the image processing apparatus 200 of the present embodiment, since it is not necessary to write parameters from the CPU to the register, it is possible to execute image processing without depending on the clock frequency (that is, performance) of the CPU. . Therefore, for example, when the ASIC of the image processing unit 230 can operate at a higher speed than the CPU of the image processing apparatus 200 or the host apparatus, the image processing can be executed while fully exhibiting the original performance of the ASIC. it can.

[Modification]
In the above description, the present invention has been described by exemplifying two embodiments. However, the present invention is not limited to the above-described embodiments, and can be implemented in various other modes. . In the present invention, for example, the following modifications can be applied to the above-described embodiment. These modifications can be combined as appropriate.

  In the above-described embodiment, it has been described that the image data is a set of pixel data having a gradation of 8 bits for each color of R, G, and B. However, the image data is not limited to such a format. For example, it may be image data consisting only of the luminance component (Y), image data consisting of the luminance component and the color difference components (Cb, Cr), or image data having a larger (or smaller) number of gradations. Also good.

  Further, in the second embodiment described above, an aspect has been described in which used header information (that is, parameters used in the processing block in the previous stage) is deleted. However, it is not always necessary to delete used header information. Alternatively, it may be supplied to the subsequent processing block as it is. However, in view of the data capacity processed by each processing block, it can be said that efficient image processing can be executed by deleting the used header information.

  Further, in the second embodiment described above, in order to prevent a specific processing block from performing processing, it has been described that the corresponding processing ID is not embedded in the header information. It is not limited to. For example, it is good also as an aspect which embeds the information that the process in the said block is not performed in header information, and it is good also as an aspect which designates the process block from which CPU requests | requires execution of a process. In the latter case, when a certain processing block is not requested to execute the processing, only the processing for deleting the header information corresponding to the own block may be performed, and the image data may be supplied as it is to the subsequent processing block. .

  In addition, the functions realized by the CPU and ASIC in the above-described embodiment can also be realized by a computer executing a program. That is, the present invention can be provided not only as the above-described image processing apparatus but also as a program for realizing a function executed by the above-described image processing apparatus.

1 is a functional block diagram illustrating a functional configuration of an image processing apparatus according to a first embodiment of the present invention. It is the conceptual diagram which showed the image data in which the additional information in the same embodiment was embedded. FIG. 2 is a block diagram showing a configuration of an image processing block in the same embodiment. It is the conceptual diagram which showed the change of the length of the image data before and after various image processing. It is the functional block diagram which showed the function structure of the image processing apparatus which is the 2nd Embodiment of this invention. FIG. 2 is a block diagram showing a configuration of an image processing block in the same embodiment. It is the conceptual diagram which showed the image data in which the additional information in the same embodiment was embedded. It is a figure for demonstrating the image data supplied to each part of an image processing part in the embodiment. It is the figure which showed an example of the structure of the conventional image processing apparatus. It is the figure which showed an example of the structure of the conventional image processing part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100, 200, 900 ... Image processing apparatus, 110, 210 ... Image input part, 120, 220 ... Information addition part, 130, 230 ... Image processing part, 131, 231 ... Input IF, 132, 132a, 132b, 132c, 232 232a, 232b, 232c ... image processing block, B1, b1 ... additional information extraction block, B2, b2 ... image processing execution block, B3, b3 ... additional information re-addition block, 133 ... output IF, 140 ... buffer unit, 150 ... Image output part

Claims (7)

Information adding means for embedding additional information used in image processing to be executed for image data composed of input pixels of a plurality of rows and a plurality of columns in the image data;
Image processing means for recognizing additional information embedded in the image data by the information adding means and executing the image processing on the image data using the additional information;
An image processing apparatus comprising: output means for outputting image data subjected to image processing by the image processing means. The information adding means includes
The image processing apparatus according to claim 1, wherein information indicating a line break of the image data is embedded as the additional information. The information adding means includes
The image processing apparatus according to claim 1, wherein information indicating the end of the image data is embedded as the additional information. The image processing means includes
A plurality of image processing units that execute different image processing,
At least one of the plurality of image processing units includes:
An extraction unit for deleting the additional information from the image data;
Using the additional information deleted from the image data by the extraction unit, a processing execution unit that executes image processing on the image data from which the additional information has been deleted;
A supply unit that adds information corresponding to the additional information deleted by the extraction unit to the image data that has been subjected to image processing by the processing execution unit, and supplies the image data to a subsequent image processing unit. The image processing apparatus according to claim 1. The image processing means includes
A plurality of image processing units that execute different image processing,
The information adding means includes
The image processing apparatus according to claim 1, wherein a parameter used for each of the plurality of image processing units is embedded as the additional information. At least one of the plurality of image processing units includes:
A recognition unit for recognizing a parameter included in the additional information embedded in the image data;
When the parameter recognized by the recognition unit includes a parameter used by itself, a processing execution unit that executes image processing on the image data using the parameter;
The image processing apparatus according to claim 5, further comprising: a supply unit that deletes a parameter used in the processing execution unit from the additional information and supplies the parameter to a subsequent image processing unit. On the computer,
A function of embedding additional information used for image processing to be executed for image data composed of input pixels of a plurality of rows and a plurality of columns in the image data;
A function of recognizing the additional information embedded in the image data and executing predetermined image processing on the image data using the additional information;
A program for realizing a function of outputting image data subjected to the image processing.

Images