JP6864721B2 - Information processing device and its control method - Google Patents

Description

The present invention relates to an information processing apparatus, and a control how.

Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) that can change the logic circuit are well known. Generally, a PLD or FPGA switches logic circuits by writing circuit configuration information stored in a non-volatile memory such as a ROM to a configuration memory which is an internal volatile memory at startup. Further, since the information in the configuration memory is erased when the power is turned off, it is necessary to reconfigure the logic circuit by writing the circuit configuration information from the non-volatile memory to the configuration memory again when the power is turned on. In this way, the method of configuring the logic circuit of PLD or FPGA only once is called static reconstruction.

On the other hand, FPGAs and the like that can change the logic circuit while the circuit is operating have been developed, and the method of changing the logic circuit during the operation is called dynamic reconstruction. In addition, some FPGAs can rewrite only a specific area instead of the entire chip, and such rewriting is called partial reconstruction. In particular, partial reconstruction of other logic circuit parts without stopping the operation of the operating logic circuit is called dynamic partial reconstruction.

In the dynamic partial reconstruction, the logic circuit in the FPGA can be partially reconstructed by rewriting only a part of the configuration memory area instead of rewriting the entire configuration memory at the time of the dynamic partial reconstruction. By using such a dynamic partial reconstruction technique, it is possible to implement a plurality of logic circuits in one area in the FPGA, so that it is possible to realize a logic circuit in which hardware resources are time-division-multiplexed. As a result, it is possible to flexibly realize various functions according to the application with a small amount of hardware resources while maintaining high computing performance by the hardware.

As a technique using this dynamic partial reconstruction, for example, in Patent Document 1, in pipeline processing, the circuit is reconstructed on a reconfigurable circuit in order from the first circuit of the pipeline, and data processing is performed while switching functions. The method is disclosed.

In recent years, image processing devices such as MFPs (Multi Function Printers) can select multiple processes (copy job, print job, SEND job, etc.) according to the request from the user, and the image processing according to each process is hardware. Or it is executed by software. When a reconfigurable circuit such as an FPGA is used for the image processing hardware of this image processing device, the circuit configuration of the FPGA can be dynamically and partially switched for each of the above-mentioned functions. As a result, various image processing functions can be realized with a small amount of hardware resources. However, in the configuration for partial reconstruction, if the partial reconstruction fails due to some factor such as device failure, electrical noise, write timing, etc., the necessary circuit will not be configured and the intended data processing will be realized. You will not be able to do it.

Japanese Unexamined Patent Publication No. 2011-186981

As described above, when the reconfigurable circuit is used while being partially reconfigured, if the partial reconfiguration fails, the performance of the device deteriorates. For example, since a specific image processing function is required, if the partial reconstruction of a certain image processing function fails for some reason, the image processing function cannot be used and the processing stops. As a result, the performance of the image processing device deteriorates. Therefore, in a configuration in which a reconfigurable circuit is used while being partially reconstructed, it is necessary to implement it in consideration of the possibility that the partial reconstruction will fail.

An object of the present invention is to solve the above-mentioned problems of the prior art.

Feature of the present invention, there is provided an information processing apparatus having a partially reconfigurable reconfigurable circuit of the circuit arrangement, when the reconfiguration of the reconfigurable circuit fails, to suppress as much as possible performance deterioration of the device Is to provide the technology that can be used.

The image processing apparatus according to one aspect of the present invention in order to achieve the above object has the following configuration. That is,
In an information processing device having a plurality of regions including at least a first region and a second region, and the circuit can be independently reconfigured for each region.
A first circuit configuration information for configuring a circuit that executes a first function in the first region, and a second circuit for configuring a circuit that executes a second function in the second region. A storage means for storing configuration information and a third circuit configuration information for configuring a circuit that executes the first function in the second region.
Based on the first circuit configuration information stored in the storage means, a circuit for executing the first function is configured in the first region, and the second circuit stored in the storage means. Based on the configuration information, the control means for configuring the circuit for executing the second function in the second region, and the control means.
It has a detection means for detecting that the process of forming a circuit for executing the first function in the first region by the control means has failed.
When the number of times that the detection means has detected that the process of forming the circuit for executing the first function in the first region has failed is less than a predetermined number, the control means detects it by the detection means. based, wherein, without the need to reconfigure the circuit configured in the second region, it has again the row processing included in a circuit for performing the first function to the first region, said detecting means the When the number of times that the process of forming the circuit that executes the first function in the first region has been detected has failed is a predetermined number or more, the third circuit is based on the detection by the detection means of the detection means. It is characterized in that a process of forming a circuit for executing the first function is performed in the second region according to the configuration information.

According to the present invention, in the information processing apparatus having a partially reconfigurable reconfigurable circuit of the circuit arrangement, when the reconfiguration of the reconfigurable circuit fails, to suppress as much as possible performance deterioration of the device It has the effect of being able to.

Other features and advantages of the present invention will become apparent in the following description with reference to the accompanying drawings. In the attached drawings, the same or similar configurations are designated by the same reference numbers.

The accompanying drawings are included in the specification and are used to form a part thereof, show embodiments of the present invention, and explain the principles of the present invention together with the description thereof.
The block diagram explaining the structure of the image processing apparatus which concerns on embodiment of this invention. The block diagram explaining the configuration particularly related to the partial reconstruction of the image processing apparatus which concerns on embodiment. The figure explaining the data structure of the configuration data stored in the configuration ROM which concerns on embodiment. The flowchart explaining the processing of the image processing apparatus which concerns on embodiment of this invention. The flowchart explaining the details of the partial reconstruction execution processing of the FPGA of S403 of FIG. 4 by the image processing apparatus which concerns on this embodiment. The flowchart explaining the details of the processing of S506 of FIG. 5 by the image processing apparatus which concerns on embodiment. FIG. 5 is a flowchart illustrating a full-scale reconstruction process executed in S405 of FIG. 4 by the image processing apparatus according to the embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments do not limit the present invention according to the claims, and not all combinations of features described in the present embodiment are essential for the means for solving the present invention. ..

FIG. 1 is a block diagram illustrating a configuration of an image processing device 100 according to an embodiment of the present invention.

The image processing device 100 includes an operation unit 103 having keys and a touch panel operated by a user who uses the image processing device 100, a scanner unit 109 that scans a document and reads an image of the document, and a sheet of paper based on the image data. It has a printer unit 107 for printing an image. The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp for reading a document, a scanning mirror (all not shown), and the like. The printer unit 106 includes a CPU (not shown) for controlling the printer unit 106, a photoconductor drum for performing image formation and fixing (not shown), and the like.

Further, the image processing device 100 includes a CPU 101 that comprehensively controls the operation of the image processing device 100, and the CPU 101 executes a control program for controlling each unit of the image processing device 100. Further, the ROM 104 stores a control program executed by the CPU 101 and each data. The RAM 111 provides a system work memory for operating the CPU 101 and an image memory for temporarily storing image data. The memory controller 110 controls the writing of data to the RAM 111 and the reading of data from the RAM 111. The memory controller 110 is connected to the system bus 120 and the image bus 121, and controls access to the RAM 111.

The FPGA (Field Programmable Gate Array) 140 is a reconfigurable circuit, and constitutes an image processing circuit or the like of the image processing device 100. In the embodiment, FPGA is described as an example of the reconfigurable circuit, but a reconfigurable circuit other than FPGA may be used. The config controller 130 controls the circuit configuration of the FPGA under the control of the CPU 101. The configuration ROM 150 stores circuit configuration information (config data) for configuring the circuit of the FPGA 140. The circuit configuration information of the FPGA 140 can be dynamically rewritten and partially rewritable. That is, while the circuit configured as part of the reconfigured portion of the FPGA 140 is operating, another circuit can be configured in another portion that does not overlap with the portion occupied by the circuit.

The network I / F 102 communicates (transmits and receives) with a general-purpose computer or the like (not shown) on the network. The printer I / F 106 connects the image bus 121 and the printer unit 107, and controls the interface with the printer unit 107. The scanner I / F 108 outputs the image data input from the scanner unit 109 to the image bus 121 to control the interface with the scanner unit 109. The USB I / F 114 communicates (transmits and receives) with a general-purpose computer, a USB device, etc. (not shown) connected to the image processing device 100 via a USB interface. The FAXI / F115 connects to a public network and communicates (transmits and receives) with an image processing device and a facsimile machine (not shown). The ROMI / F112 controls reading data from the ROM 104, such as a program executed by the CPU 101. The operation unit I / F 113 controls the interface between the CPU 101 and the operation unit 103. Here, the FPGA 140, the scanner I / F 108, and the printer I / F 106 are connected to the image bus 121 for transferring the image data to be processed. The network I / F102, USBI / F114, FAXI / F115, operation unit I / F113, ROMI / F112, config controller 130, and FPGA140 are connected to the CPU 101 via the system bus 120. The CPU 101 sets parameters for the FPGA 140, the scanner I / F 108, and the printer I / F 106 via the system bus 120.

Next, a configuration related to partial reconstruction in the image processing apparatus 100 according to the present embodiment will be described with reference to FIG.

FIG. 2 is a block diagram illustrating a configuration particularly related to partial reconstruction of the image processing apparatus 100 according to the embodiment. In FIG. 2, the parts described with reference to FIG. 1 are indicated by the same reference numbers.

The FPGA 140 has four partial reconstruction parts (PR1 to PR4) 201 to 204 inside. Each partial reconstruction unit can dynamically reconstruct its circuit configuration. In the embodiment, an example in which a circuit having an image processing function is configured in the partial reconstruction unit is described, but it goes without saying that a circuit other than the image processing function can be configured in the partial reconstruction unit.

The config controller 130 writes the configuration data stored in the configuration ROM 150 to the designated partial reconfiguration unit of the FPGA 140. The config controller 130 has a reconstruction management unit 205 and an error detection unit 206. The reconstruction management unit 205 manages each of the partial reconstruction units 201 to 204. For example, the availability of each partial reconstruction unit is managed, such as whether each of the partial reconstruction units 201 to 204 is used for the current processing. Then, it is determined whether or not each partial reconstruction unit is rewritable. The reconstruction management unit 205 rewrites the configuration data to each of the partial reconstruction units 201 to 204 based on the instruction from the CPU 101 and the determination result of whether or not each partial reconstruction unit is rewritable.

The error detection unit 206 detects an error when each partial reconstruction of the partial reconstruction units 201 to 204 is not normally completed. For example, when the partial reconstruction unit 201 is rewritten, the error signal output by the reconfigurable circuit (FPGA) is monitored when the rewriting of the configuration data fails for some reason. When the error detection unit 206 detects this error signal, it notifies the reconstruction management unit 205. The process when an error is detected by the error detection unit 206 will be described later with reference to FIGS. 4 to 7.

Next, with reference to FIG. 3, a method of storing configuration data constituting the partial reconstruction units 201 to 204 of the FPGA 140 in the image processing apparatus 100 according to the embodiment will be described.

FIG. 3 is a diagram illustrating a data configuration of configuration data stored in the configuration ROM 150 according to the embodiment.

In the configuration ROM 150, a plurality of configuration data necessary for the partial reconstruction of the partial reconstruction units 201 to 204 of the FPGA 140 are stored in association with the partial reconstruction unit. The configuration data 300 for the partial reconstruction unit 201 (PR1) represents the configuration data that constitutes a logic circuit in the partial reconstruction unit 201. In FIG. 3, the case where the partial reconstruction unit 201 has four functions A, B, C, and D that can be configured is taken as an example. The configuration data 301 is the configuration data for configuring the circuit of the function A in the PR1. Similarly, the configuration data 302 to 304 are configuration data for configuring the circuit configurations of the function B, the function C, and the function D in the PR1, respectively.

Further, the configuration data 310 represents the configuration data constituting the logic circuit in the partial reconstruction unit (PR2) 202. The configuration data 310 for PR2 also stores the configuration data of the four functions A, B, C, and D, and the configuration data 311 is a configuration for configuring the circuit of function A in PR2. It is data. Similarly, the configuration data 312 to 314 are configuration data for configuring the circuit configurations of the function B, the function C, and the function D in the PR2, respectively.

Further, the configuration data 320 represents the configuration data constituting the logic circuit in the partial reconstruction unit (PR3) 203. The configuration data 320 for PR3 also stores the configuration data of the four functions A, B, C, and D, and the configuration data 321 is the configuration for configuring the circuit of function A in PR3. It is data. Similarly, the configuration data 322 to 324 are configuration data for configuring the circuit configurations of the function B, the function C, and the function D in the PR3, respectively.

Further, the configuration data 330 represents the configuration data constituting the logic circuit in the partial reconstruction unit (PR4) 204. The configuration data 330 for PR4 also stores the configuration data of the four functions A, B, C, and D, and the configuration data 331 is a configuration for configuring the circuit of function A in PR3. It is data. Similarly, the configuration data 332 to 334 are configuration data for configuring the circuit configurations of the function B, the function C, and the function D in the PR4, respectively.

As described above, it is necessary to prepare the configuration data for each partial reconstruction unit. For example, consider the case where the circuit configuration of the function A is configured by the partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202. In this case, even if the same function A is used, it is necessary to prepare different configuration data depending on the partial reconstruction unit, such as the configuration data 301 of the function A for PR1 and the configuration data 311 of the function A for PR2. There is.

Therefore, if a large amount of configuration data for each partial reconstruction unit is provided, each partial reconstruction unit can be used for various functions, but the amount of data stored in the configuration ROM 150 increases. On the other hand, if the reconfiguration unit to be configured for each function is limited, the functions that can be configured in each partial reconfiguration unit are limited, but the amount of configuration data can be reduced, so that the capacity of the configuration ROM 150 can be reduced. Can be done.

In the present embodiment, the FPGA 140 has four partially reconstructed regions, and the case where the functions configured in the partially reconstructed regions are A, B, C, and D will be described as an example. Of course, the reason for limiting the area of partial reconstruction and the functions configured therein to four is only for the sake of clarity of explanation, and it is not necessary to limit the area to four.

FIG. 4 is a flowchart illustrating processing by the image processing apparatus 100 according to the embodiment of the present invention. Each procedure in the flowchart of FIG. 4 is executed by the CPU 101 executing the control program stored in the ROM 104.

First, in S401, when the CPU 101 receives a job, the CPU 101 proceeds to S402, and the CPU 101 identifies a function that must be configured in the FPGA 140 when executing the received job. For example, when the function A is required to execute the received job, the function A is specified as the function for executing the job. Next, the process proceeds to S403, and the CPU 101 configures the function specified in S402 in the partial reconstruction unit of the FPGA 140. In this S403, under the control of the CPU 101, the config controller 130 reads the configuration data necessary for configuring the function from the configuration ROM 150 and writes it to the partial reconfiguration unit of the FPGA 140. Details of the partial reconstruction execution process of S403 will be described later with reference to FIG.

Next, proceeding to S404, the CPU 101 determines in S403 whether or not the configuration of the partial reconstruction unit of the FPGA 140 has been successful so that the function specified in S402 can be executed. Here, the CPU 101 determines whether or not the configuration of the partial reconstruction unit has succeeded based on the detection result acquired from the error detection unit 206 by the reconstruction management unit 205 of the config controller 130. If the CPU 101 determines in S404 that all the functions necessary for executing the job specified in S402 can be configured in the partial reconstruction unit of the FPGA 140, the process proceeds to S407. In S407, the CPU 101 processes the received job by using the function configured in the FPGA 140, and ends this process.

On the other hand, when it is determined in S404 that the configuration of the partial reconstruction unit has failed, the process proceeds to S405. In S405, the CPU 101 causes the config controller 130 to execute the complete reconfiguration of the FPGA 140 because the partial reconfiguration of the functions required for executing the job has ended with an error. The execution flow of the full-scale reconstruction of the FPGA 140 executed in S405 will be described later with reference to FIG. 7. When the processing of S405 is completed, the process proceeds to S406, and the CPU 101 determines whether the entire reconfiguration of the FPGA 140 has been completed normally. Here, too, the CPU 101 determines whether or not the reconstruction management unit 205 of the config controller 130 succeeds based on the detection result acquired from the error detection unit 206. In S406, when the CPU 101 determines that the complete reconstruction of the FPGA 140 has been completed normally, the process proceeds to S407, and when the error ends, the CPU 101 proceeds to S408 to notify an error and end this process. In this error notification, an error is displayed on the display unit of the operation unit 103 under the instruction of the CPU 101, and the power is turned on again.

As a result, the function required to execute the received job can be configured in the reconfigurable circuit (FPGA), and the job can be executed by using the reconfigurable circuit in which the function is configured.

Next, the process of executing the partial reconstruction will be described in detail with reference to FIG.

FIG. 5 is a flowchart illustrating the details of the partial reconstruction execution process of the FPGA of S403 of FIG. 4 by the image processing device 100 according to the present embodiment. Each procedure in the flowchart of FIG. 5 is executed by the config controller 130 under the instruction of the CPU 101 or the CPU 101.

First, in S501, the CPU 101 identifies the configuration data corresponding to the function configured in the partial reconstruction unit from the partial reconstruction unit to be reconstructed and the configuration data stored in the configuration ROM 150. .. For example, when the circuit of the function A is configured in the partial reconstruction unit (PR1) 201, the configuration data 301 of the function A for PR1 is specified from the configuration data stored in the configuration ROM 150. Here, the CPU 101 identifies a rewritable partial reconfiguration unit that is not used for job processing in the FPGA 140, based on the information from the reconstruction management unit 205.

Next, the process proceeds to S502, and the CPU 101 instructs the config controller 130 to execute the partial reconstruction. Specifically, the configuration data specified in S501 and the partial reconstruction unit to be written are instructed. Here, for example, the configuration data is instructed to be written to the partial reconstruction unit (PR1) 201. Then, the process proceeds to S503, and the CPU 101 determines whether or not the partial reconstruction of S502 has been completed normally based on the response from the config controller 130. In this determination, the reconstruction management unit 205 monitors a signal indicating that the partial reconstruction output by the FPGA 140 has ended normally, and when the error detecting unit 206 does not detect an error, it determines that the partial reconstruction has ended normally. When the CPU 101 determines in S503 that the partial reconstruction has been completed normally, the process proceeds to S508, and the CPU 101 determines whether the partial reconstruction of all the functions necessary for executing the job has been completed. When the partial reconstruction of all the functions is completed, this process is completed and the process proceeds to S404 in FIG. On the other hand, if the CPU 101 determines in S508 that the partial reconfiguration of all the functions required to execute the job has not been completed, the process returns to S501 and the partial reconfiguration of the remaining necessary functions is executed.

On the other hand, if the CPU 101 determines in S503 that the partial reconstruction has not been completed normally, the process proceeds to S504. In S504, since the partial reconstruction executed in S502 has failed for some reason, the CPU 101 instructs the config controller 130 to re-execute the partial reconstruction executed in S502. Then, the process proceeds to S505, and the CPU 101 determines whether or not the re-execution of the partial reconstruction executed in S504 has been normally completed, as in the case of S503 described above. If the CPU 101 determines in S505 that the re-execution of the partial reconstruction has been completed normally, the process proceeds to S508, and if not, the process proceeds to S506. If it is determined in S505 that the partial reconstruction has not been completed normally, the CPU 101 may execute the processes of S504 and S505 a plurality of times.

In S506, the CPU 101 instructs the config controller 130 to switch the partial reconfiguration unit for writing the configuration data for executing the function to the partial reconfiguration unit for which other processing is not executed. Further, the switched partial reconstruction unit is instructed to write the corresponding configuration data. For example, when an attempt to configure a circuit of function A in the partial reconstruction unit (PR1) 201 fails, if the partial reconstruction unit (PR2) 202 is available, the circuit of function A is reconfigured there. carry out. The process of switching the partial reconstruction unit and executing the partial reconstruction in S506 will be described later with reference to FIG. Then, the process proceeds to S507, and the CPU 101 determines whether the partial reconstruction by switching the partial reconstruction unit executed in S506 was successful. Similar to S503 and S505, this determination is also performed by the configuration management unit 205 and the error detection unit 206 monitoring signals indicating normal termination and error termination of the FPGA. If the CPU 101 determines in S507 that the partial reconstruction has been completed normally, the process proceeds to S508, and if the error ends, the process ends the partial reconstruction process and proceeds to S404 in FIG.

In this way, when writing the configuration data to a certain partial reconstruction unit of the FPGA fails, the configuration data that executes the same function can be written to another partial reconstruction unit of the FPGA. As a result, even if the configuration of a certain function in a certain partial reconstruction part of the FPGA fails, the same function can be configured in another partial reconstruction part.

Next, with reference to FIG. 6, a process of switching the partial reconstruction unit and executing the partial reconstruction will be described in detail.

FIG. 6 is a flowchart illustrating details of the processing of S506 in FIG. 5 by the image processing apparatus 100 according to the embodiment. Each procedure in the flowchart of FIG. 6 is executed by the config controller 130 under the instruction of the CPU 101 or the CPU 101.

First, in S601, the CPU 101 determines whether or not there is a vacant partial reconstruction unit in the partial reconstruction unit of the FPGA 140 based on the information from the reconstruction management unit 205. If the CPU 101 determines in S601 that there is a vacant partial reconstructing unit in the FGA 140 partial reconstructing unit, the process proceeds to S602, and if there is no vacant area, the process proceeds to S604. In S602, the CPU 101 specifies the configuration data to be written in the vacant partial reconstruction unit. For example, when the partial reconstruction unit (PR2) is vacant and the function A is configured there, the configuration data 311 of the PR2 function A is specified from the configuration ROM 150. Then, the process proceeds to S603, and the CPU 101 writes the configuration data specified in S602 to the vacant partial reconstruction unit found in S601 to execute the partial reconstruction, and ends this process. In S602, it is conceivable that the configuration data for executing the function corresponding to the vacant partial reconstruction unit is not stored in the configuration ROM 150. In that case, you may search for another vacant partial reconstruction part that stores the configuration data that executes the function.

On the other hand, in S604, the CPU 101 determines whether or not there is a rewritable partial reconstruction unit in the partial reconstruction unit of the FPGA 140 because there is no empty partial reconstruction unit in the partial reconstruction unit of the FPGA 140. .. Here, the rewritable partial reconstruction unit is a partial reconstruction unit in which some configuration data has already been written in the partial reconstruction unit, but is not used in the current processing. In S604, the CPU 101 proceeds to S605 when it determines that there is a rewritable partial reconfiguration part in the partial reconfiguration part of the FPGA 140, but if there is no rewritable partial reconfiguration part, this process ends. Proceed to S507 of FIG.

In S605, the CPU 101 specifies the configuration data configured in the rewritable partial reconstruction unit specified in S604 because there is a rewritable partial reconstruction unit in the partial reconstruction unit of the FPGA 140. For example, when the function A is configured in the partial reconstruction unit (PR3) 203, the configuration data 331 of the PR3 function A in the configuration ROM 150 is specified. Then, the process proceeds to S606, and the CPU 101 overwrites the configuration data specified in S605 with the rewritable partial reconstruction unit found in S604, and ends this process. In S605, it is conceivable that the configuration data for executing the function corresponding to the rewritable partial reconstruction unit is not stored in the configuration ROM 150. In that case, you may search for another rewritable partial reconstruction part that stores the configuration data that executes the function.

According to this, when the configuration of a partly reconfigured part of the FPGA fails, the part of the FPGA that is vacant (configuration has not been executed) or is configured, but is currently in use. Find the unreconstructed part. When such a partial reconstruction part is found, the configuration data corresponding to the partial reconstruction part and the function to be configured there is specified, and the FPGA configuration is performed with the specified configuration data. Can be executed.

Next, with reference to FIG. 7, the process of executing the full-scale reconstruction of S405 of FIG. 4 will be described in detail.

FIG. 7 is a flowchart illustrating a full-scale reconstruction process executed in S405 of FIG. 4 by the image processing apparatus 100 according to the embodiment. Each procedure in the flowchart of FIG. 7 is achieved by the CPU 101 and the config controller 130 executing the process under the instruction of the CPU 101.

In S701, the CPU 101 acquires the type of config data configured in the partial reconstruction unit of the FPGA 140 from the config controller 130 and stores it in the RAM 111. Here, the type of config data configured in the partial reconstruction unit is stored in order to execute the partial reconstruction after the complete reconstruction and to make the circuit configuration of the FPGA 140 in the same state as before the full reconstruction. Next, the process proceeds to S702, and the CPU 101 executes a complete reconfiguration of the FPGA 140. Here, the functions A to D of the FPGA 140 are configured for each of the partial reconstruction units 201 to 204 of the FPGA 140. For example, the partial reconstruction unit 201 has a function A, the partial reconstruction unit 202 has a function B, the partial reconstruction unit 203 has a function C, and the partial reconstruction unit 204 has a function D. Next, the process proceeds to S703, and the CPU 101 executes partial reconstruction as necessary so as to be the same as the state before the full reconstruction stored in S701. Here, for example, the partial reconstruction unit 201 is configured with the function B, and the partial reconstruction unit 202 is configured with the function A. In S702, if the entire reconfiguration of the FPGA 140 is executed based on the type of the config data configured in the partial reconstruction unit of the FPGA 140 stored in S701, the processing of S703 can be omitted.

As described above, according to the present embodiment, in an image processing apparatus provided with an FPGA capable of dynamic partial reconstruction, recovery control that suppresses performance deterioration as much as possible even if dynamic partial reconstruction fails is performed. It becomes feasible.

(Other embodiments)
The present invention is also realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiment is supplied to the system or device via a network or various storage media, and the computer (or CPU, MPU, etc.) of the system or device reads the program. This is the process to be executed.

The present invention is not limited to the above embodiments, and various modifications and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.

100 ... Image processing device, 101 ... CPU, 104 ... ROM, 111 ... RAM, 120 ... System bus, 121 ... Image bus, 130 ... Config controller, 140 ... FPGA, 150 ... Configuration ROM, 205 ... Reconfiguration management unit , 206 ... Error detector.

Claims (9)

In an information processing device having a plurality of regions including at least a first region and a second region, and the circuit can be independently reconfigured for each region.
A first circuit configuration information for configuring a circuit that executes a first function in the first region, and a second circuit for configuring a circuit that executes a second function in the second region. A storage means for storing configuration information and a third circuit configuration information for configuring a circuit that executes the first function in the second region.
Based on the first circuit configuration information stored in the storage means, a circuit for executing the first function is configured in the first region, and the second circuit stored in the storage means. Based on the configuration information, the control means for configuring the circuit for executing the second function in the second region, and the control means.
It has a detection means for detecting that the process of forming a circuit for executing the first function in the first region by the control means has failed.
When the number of times that the detection means has detected that the process of forming the circuit for executing the first function in the first region has failed is less than a predetermined number, the control means detects it by the detection means. based, wherein, without the need to reconfigure the circuit configured in the second region, it has again the row processing included in a circuit for performing the first function to the first region, said detecting means the When the number of times that the process of forming the circuit that executes the first function in the first region has been detected has failed is a predetermined number or more, the third circuit is based on the detection by the detection means of the detection means. An information processing apparatus characterized in that a process of forming a circuit for executing the first function is performed in the second region according to the configuration information. The control means has the first function in the first region based on the number of times that the detection means has detected that the process of forming the circuit for executing the first function has failed in the first region. The information processing apparatus according to claim 1, wherein the processing for forming the circuit for executing the above is performed again. When the number of times that the detection means has detected that the process of forming the circuit that executes the first function has failed in the first region is a predetermined number or more, the second region is obtained from the plurality of regions. and further comprising a specifying means for specifying a region constituting the circuit for executing the first function,
The control means is characterized in that a circuit is configured based on the third circuit configuration information for configuring a circuit that executes the first function in the second region specified by the specific means. The information processing apparatus according to claim 1 or 2. The second function, the information processing apparatus according to claim 3, characterized in that the function is not for interest in the execution of the predetermined process. When the number of times that the detecting means has detected that the processing for forming the circuit that executes the first function has failed in the first region is equal to or more than a predetermined number , the control means is set in the second region. claims 1 to any one of 4, characterized in that a circuit for performing the first function by overwriting the circuit composed of the circuit which is constituted by the third circuit configuration information The information processing device described in. Further having a reading means for reading an image on a document and generating image data,
The information processing apparatus according to any one of claims 1 to 5 , wherein the first function is a function of processing the image data generated by the reading means. It also has a printing means for printing images on paper,
The information processing apparatus according to any one of claims 1 to 6 , wherein the first function is a function of generating an image printed by the printing means. The information processing apparatus according to any one of claims 1 to 7 , wherein the first region and the plurality of regions including the second region are included in one module. A circuit that has a plurality of regions including at least a first region and a second region and can be reconstructed independently for each region.
A first circuit configuration information for configuring a circuit that executes a first function in the first region, and a second circuit for configuring a circuit that executes a second function in the second region. In a control method of an information processing apparatus having a storage means for storing configuration information and a third circuit configuration information for configuring a circuit that executes the first function in the second region.
Based on the first circuit configuration information stored in the storage means, a circuit for executing the first function is configured in the first area, and the second circuit stored in the storage means. A first control step that configures a circuit for executing the second function in the second region based on the configuration information, and
In the first control step, a detection step of detecting that the process of forming a circuit for executing the first function in the first region has failed, and a detection step of detecting failure .
When the number of times that the process of forming the circuit that executes the first function in the first region is detected in the detection step is less than a predetermined number, the second is based on the detection in the detection step. of without performing reconfiguration of the circuit constituted in the region, the circuitry for performing the first function have again line processing constituting the first region, the first region in the detection step When the number of times that the process of forming the circuit that executes the first function is detected has failed is equal to or more than a predetermined number, the second is based on the detection in the detection step and according to the third circuit configuration information. A control method for an information processing apparatus, which comprises a second control step for performing a process of forming a circuit for executing the first function in the region of the above.

Images