JP2018165908A - Information processor and information processing method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor having a re-configuration device capable of changing a circuit configuration based on circuit information that makes re-configuration of a logic circuit avoiding a failure block when detecting a hardware failure of the re-configuration device.SOLUTION: A processor has an FPGA capable of changing a circuit configuration by re-constituting a programmable block in a logic based on circuit information, a circuit information synthesis part synthesizing the circuit information from a source code of a circuit processing a tack, and an FPGA circuit monitoring part detecting a failure of the FPGA, specifies a failure block when the FPGA circuit monitoring part has detected a hardware failure of the FPGA, and the circuit information synthesis part synthesizes the circuit information avoiding the specified failure block to make re-configuration of a logic circuit avoiding the failure block possible.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

  An information processing apparatus (FPGA) having a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array) capable of changing the configuration of a programmable logic circuit based on circuit information, and executing part of the processing by the FPGA Server). Faults occurring in the FPGA include a soft error in which circuit information data is changed due to cosmic rays or the like, and a hard error in which the circuit cannot be rewritten due to disconnection or short circuit. If a soft error occurs, it can be recovered by writing the same circuit information again. However, if a hard error occurs, the fault location is physically broken and cannot be used permanently.

  Faults in the FPGA are generally detectable. For example, a failure of a memory (CRAM) in which circuit information is written can be detected by an error detection method such as CRC (Cyclic Redundancy Code), and a failure of a circuit can be detected by using test data for operation confirmation. is there. Further, there has been proposed an FPGA that can detect a failure portion of a cell portion by using a self-checking circuit that detects a failure (see, for example, Patent Document 1).

  In the FPGA, even in a circuit that realizes the same function, circuit information is different if the position of the circuit in the FPGA is different. Prepare multiple circuit information for realizing the same function in advance, and when a failure is detected by the FPGA, it is possible to avoid the failure location by switching to the circuit information that configures the circuit without including the failure location. Has been proposed (for example, see Patent Document 2).

JP-A-10-84275 JP-A-9-62528

  As described above, when a plurality of pieces of circuit information for realizing the same function are prepared in advance, it is necessary to prepare circuit information for only the types of positions that are assumed to cause a hardware failure (hard error). This can be done either by preparing a large amount of circuit information that disables use of a small range including a fault location, or by preparing circuit information that disables use of a rough range including a fault location. There are challenges. If many types of circuit information are prepared, it is possible to reduce the range in which the circuit information cannot be used as a failure location, but the storage capacity for storing the prepared circuit information increases. On the other hand, if the number of types of circuit information to be prepared is small, the range that cannot be used as a failure location increases, and the circuit resources that can be used decrease. In one aspect, an object of the present invention is to avoid a failure block when a hardware failure of a reconfiguration device is detected in an information processing apparatus having a reconfiguration device capable of changing a circuit configuration based on circuit information. An object of the present invention is to provide an information processing apparatus that enables reconfiguration of a logic circuit.

  One aspect of an information processing apparatus includes a reconfigurable device having a plurality of logic programmable blocks and capable of changing a circuit configuration by reconfiguring the blocks based on circuit information, and a source of a circuit that processes a task A synthesis unit that synthesizes circuit information from the code, and a detection unit that detects a failure of the reconfigurable device. When the detection unit detects a hardware failure of the reconfigurable device, the detection unit identifies a block having a hardware failure, and the synthesis unit synthesizes circuit information that avoids the identified block having the hardware failure.

  In one aspect of the invention, when a hardware failure of a reconfigurable device is detected, a block in which a hardware failure is identified and circuit information that avoids the failed block is synthesized, and a plurality of circuit information is prepared in advance. It is possible to reconfigure the logic circuit avoiding the failure block.

FIG. 1 is a diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a functional configuration example of the management server and the FPGA server in the present embodiment. FIG. 3 is a diagram illustrating an example of the flow of processing during normal operation in the present embodiment. FIG. 4A and FIG. 4B are diagrams illustrating an example of a processing flow when a failure occurs in the present embodiment. FIG. 5A to FIG. 5F are diagrams for explaining processing related to circuit information when a failure occurs in the present embodiment. 6A and 6B are diagrams illustrating another example of a processing flow when a failure occurs in the present embodiment. FIG. 7 is a diagram illustrating another functional configuration example of the FPGA server according to the present embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of an information processing system according to an embodiment of the present invention. The information processing system according to this embodiment includes a management server 10 and a plurality of FPGA servers 20 that can communicate via a network 30.

  The management server 10 includes a CPU (Central Processing Unit) 11 and a storage unit 12. Each function of the management server 10 is realized by the CPU 11 reading the program from the storage unit 12 and executing it. The storage unit 12 stores various data including programs executed by the CPU 11.

  The management server 10 receives a task processing request from a client server (not shown), allocates the task to each FPGA server 20, and receives the task execution result from the FPGA server 20 and returns it to the client server. The task execution result may be returned directly from the FPGA server 20 to the client server.

  In addition, the management server 10 synthesizes circuit information from the source code of the circuit that processes the task and provides it to the FPGA server 20. Here, when the management server 10 receives a request from the FPGA server 20 to re-synthesize new circuit information that avoids the failed block, the management server 10 synthesizes circuit information for arranging the logic circuit while avoiding the failed block. To provide.

  The FPGA server 20 includes a CPU 21, a storage unit 22, and an FPGA (Field Programmable Gate Array) 23. Each function of the FPGA server 20 is realized by the CPU 21 reading out and executing the program from the storage unit 22, and performs control related to the FPGA 23, for example. The storage unit 22 stores various data including a program executed by the CPU 21 and circuit information written in the FPGA 23.

  The FPGA 23 as a reconfigurable device has a plurality of logic programmable blocks, and can be changed by partially reconfiguring the circuit configuration of the programmable blocks without stopping the operation of the operating logic circuit. It is an FPGA capable of dynamic partial reconfiguration that can be performed. That is, the FPGA 23 can change the configuration of the logic circuit by dynamic partial reconfiguration. The FPGA 23 asynchronously arranges a plurality of tasks in one FPGA by allocating a circuit for processing a task to be newly executed to an empty block by dynamic partial reconfiguration without stopping other running tasks. It is feasible.

  When the FPGA server 20 receives an inquiry from the management server 10 as to whether or not task processing can be executed, the FPGA server 20 returns a response to the inquiry to the management server 10. Further, when the execution of the task is requested from the management server 10, the FPGA server 20 writes the circuit information of the circuit that processes the task into the FPGA 23, executes the task, and returns the execution result to the management server 10. The task execution result may be returned directly to the client server that requested the task processing.

  The FPGA server 20 has a function of detecting a hardware error (hardware failure) in the FPGA 23. When the FPGA server 20 detects a hardware error in the FPGA 23, it identifies the failed block, discards the circuit information that uses the identified failed block, and manages the resynthesis of new circuit information that avoids the failed block. Request to server 10. After the recombination in the management server 10 is completed, the management server 10 provides the circuit information recombined to the FPGA server 20 so that the FPGA server 20 is returned to be able to execute the task.

  FIG. 2 is a block diagram illustrating a functional configuration example of the management server and the FPGA server in the present embodiment. In FIG. 2, only one FPGA server is illustrated. The management server 210 includes a task control unit 211, a circuit source storage unit 212, and a circuit information synthesis unit 213. The task control unit 211 is an example of a control unit, and the circuit information synthesis unit 213 is an example of a synthesis unit. The task control unit 211 and the circuit information synthesis unit 213 are realized by, for example, the CPU 11 of the management server reading and executing a program from the storage unit 12, and the circuit source storage unit 212 is realized by the storage unit 12 of the management server, for example. The

  The task control unit 211 receives a request for task processing from the client server, and makes an inquiry to each FPGA server 220 as to whether or not the requested task processing can be executed. The task control unit 211 determines an FPGA server 220 to which a task is assigned based on a response from the FPGA server 220 to the inquiry, and sends a task execution request to the FPGA server 220. The task control unit 211 receives the task execution result from the FPGA server 220 and returns it to the client server that requested the task processing.

  The circuit source storage unit 212 stores a source code of a logic circuit that processes each task (for example, a circuit configuration described in HDL: Hardware Description Language). The circuit information synthesis unit 213 synthesizes circuit information for configuring the logic circuit into an FPGA from the source code of the logic circuit stored in the circuit source storage unit 212 and provides the synthesized circuit information to the FPGA server 220. In addition, when the circuit information synthesis unit 213 receives a request for re-synthesis of new circuit information avoiding the failed block from the FPGA server 220, the circuit information synthesis unit 213 generates a failed block based on the source code stored in the circuit source storage unit 212. The circuit information constituting the logic circuit is recombined and provided to the FPGA server 220.

  The FPGA server 220 includes a task management unit 221, a circuit information management unit 222, a circuit information storage unit 223, a circuit information writing unit 224, an FPGA circuit unit 225, an execution result storage unit 226, and an FPGA circuit monitoring unit 227. The task management unit 221 is an example of a control unit, the circuit information management unit 222 is an example of a management unit, the circuit information storage unit 223 is an example of a storage unit, and the FPGA circuit unit 225 is an example of a reconfigurable device. The FPGA circuit monitoring unit 227 is an example of a detection unit. The task management unit 221, the circuit information management unit 222, the circuit information writing unit 224, and the FPGA circuit monitoring unit 227 are realized, for example, by the CPU 21 of the FPGA server reading out a program from the storage unit 22 and executing it. In addition, the circuit information storage unit 223 and the execution result storage unit 226 are realized by the storage unit 22 of the FPGA server, for example, and the FPGA circuit unit 225 is realized by the FPGA 23 of the FPGA server, for example.

  The task management unit 221 receives an inquiry from the management server 210 as to whether the task processing can be executed, determines whether the task processing can be executed, and returns a response to the management server 210 as to whether the processing can be executed. The task management unit 221 has circuit information of the logic circuit that processes the requested task, whether there is a free block in the FPGA circuit unit 225 in which the circuit information can be written, and there is no free block in which the circuit information can be written. In this case, it is determined whether or not task processing can be executed based on what task is being executed.

  When the task management unit 221 receives a task execution request from the management server 210, the task management unit 221 controls the circuit information writing unit 224 to write the circuit information of the logic circuit that processes the task into the FPGA circuit unit 225 to execute the task. I do. The task management unit 221 returns the execution result of the task stored in the execution result storage unit 226 to the management server 210.

  The circuit information management unit 222 performs management related to circuit information in the FPGA server 220. The circuit information management unit 222 stores, in the circuit information storage unit 223, circuit information synthesized based on the source code and provided from the management server 210. The circuit information management unit 222 is notified of the monitoring result by the FPGA circuit monitoring unit 227. When a hard error is detected in the FPGA circuit unit 225 by the FPGA circuit monitoring unit 227 and a failure block is notified, the circuit information management unit 222 detects the failure from the circuit information stored in the circuit information storage unit 223. Delete the circuit information that uses the block. In addition, the circuit information management unit 222 requests the management server 210 to re-synthesize new circuit information that avoids the failed block.

  The circuit information storage unit 223 stores circuit information of a logic circuit that processes a task and operation check data of the task. The circuit information writing unit 224 reads circuit information of a logic circuit that processes the task requested to be executed from the circuit information storage unit 223 and writes the circuit information to the FPGA circuit unit 225. The FPGA circuit unit 225 has a plurality of logic programmable blocks, changes the circuit configuration of the programmable blocks in accordance with the written circuit information, and executes the requested task. The execution result storage unit 226 stores the execution result of the task executed by the FPGA circuit unit 225.

  The FPGA circuit monitoring unit 227 monitors the state of the FPGA circuit unit 225 and notifies the task management unit 221 and the circuit information management unit 222 of the monitoring result. The FPGA circuit monitoring unit 227 detects whether the FPGA circuit unit 225 is operating normally by performing error detection by CRC or the like of the written circuit information or detecting the output of the FPGA circuit unit 225. Check regularly. When a circuit failure occurs in the FPGA circuit unit 225, the FPGA circuit monitoring unit 227 determines whether the failure is a soft error or a hard error, and notifies the failure. To notify.

  Next, the operation will be described. The process at the time of normal operation will be described with reference to FIG. 3, and the process at the time of failure will be described with reference to FIGS. 4 (A) and 4 (B).

FIG. 3 is a diagram illustrating an example of the flow of processing during normal operation in the present embodiment.
When the task control unit 211 of the management server 210 receives a task processing execution request from the client server (301), the task control unit 211 inquires of each FPGA server 220 whether the requested task processing can be executed (302). Upon receiving the inquiry from the management server 210, the task management unit 221 of the FPGA server 220 determines whether or not the task processing can be executed and returns a response to the management server 210 as to whether or not the execution is possible (303). The task control unit 211 of the management server 210 determines the FPGA server 220 to which a task is assigned based on the answer from each FPGA server 220, and sends a task execution request to the FPGA server 220 (304).

  Upon receiving a task execution request from the management server 210, the task management unit 221 of the FPGA server 220 performs control for causing the FPGA circuit unit 225 to execute the task. For example, when the circuit information of the logic circuit that processes the requested task is not written in the FPGA circuit unit 225, the circuit information is read from the circuit information storage unit 223, and the circuit information writing unit 224 stores the circuit information in the FPGA circuit unit 225. Let it be written. When the writing of the circuit information to the FPGA circuit unit 225 is completed, the FPGA circuit monitoring unit 227 confirms that the circuit operates correctly using the task operation check data.

  When it is confirmed that the circuit operates correctly, the FPGA circuit unit 225 of the FPGA server 220 executes the task requested to be executed and stores the execution result in the execution result storage unit 226. The task management unit 221 of the FPGA server 220 appropriately acquires the execution result from the execution result storage unit 226 and sends it to the management server 210 (305, 306, 307). Here, the FPGA circuit monitoring unit 227 of the FPGA server 220 periodically checks that the FPGA circuit unit 225 is operating normally during the execution of the task. When it is confirmed that the FPGA circuit unit 225 is operating normally, intermediate data for task processing may be stored in a storage unit or the like as a recovery point when the task is interrupted.

  When the execution of the requested task is completed, the task management unit 221 of the FPGA server 220 notifies the management server 210 of the completion of the task execution (308). Upon receiving the task execution completion notification from the FPGA server 220, the task control unit 211 of the management server 210 returns the task execution result to the client server (309) and ends the process.

  FIG. 4A and FIG. 4B are diagrams illustrating an example of a processing flow when a failure occurs in the present embodiment. FIG. 4A shows a case where the circuit failure is a soft error, and FIG. 4B shows a case where the circuit failure is a hard error.

  As shown in FIGS. 4A and 4B, when the task control unit 211 of the management server 210 receives a task process execution request from the client server (401), whether or not the requested task process can be executed. Is inquired of each FPGA server 220 (402). In response to the inquiry from the management server 210, the task management unit 221 of the FPGA server 220 determines whether or not the task processing can be executed and returns a response to the management server 210 as to whether or not the execution is possible (403). The task control unit 211 of the management server 210 determines an FPGA server 220 to which a task is assigned based on the answer from each FPGA server 220, and sends a task execution request to the FPGA server 220 (404).

  Upon receiving a task execution request from the management server 210, the task management unit 221 of the FPGA server 220 performs control for causing the FPGA circuit unit 225 to execute the task. For example, when the circuit information of the logic circuit that processes the requested task is not written in the FPGA circuit unit 225, the circuit information is read from the circuit information storage unit 223, and the circuit information writing unit 224 stores the circuit information in the FPGA circuit unit 225. Let it be written. When the writing of the circuit information to the FPGA circuit unit 225 is completed, the FPGA circuit monitoring unit 227 confirms that the circuit operates correctly using the task operation check data.

  When it is confirmed that the circuit operates correctly, the FPGA circuit unit 225 of the FPGA server 220 executes the task requested to be executed and stores the execution result in the execution result storage unit 226. Here, the FPGA circuit monitoring unit 227 of the FPGA server 220 periodically checks that the FPGA circuit unit 225 is operating normally during the execution of the task. When it is confirmed that the FPGA circuit unit 225 is operating normally, intermediate data for task processing may be stored in a storage unit or the like as a recovery point when the task is interrupted.

  In this example, in the FPGA server 220, the normal operation of the FPGA circuit unit 225 is confirmed by the FPGA circuit monitoring unit 227 (405), and the task management unit 221 of the FPGA server 220 acquires the execution result from the execution result storage unit 226. To the management server 210 (406). Thereafter, during the execution of the task, the FPGA circuit monitoring unit 227 of the FPGA server 220 finds a circuit failure in the FPGA circuit unit 225 and notifies the task management unit 221 (407), and the task management unit 221 fails to execute the task. Is notified to the management server 210 (408).

  Upon receiving notification of task execution failure, the task control unit 211 of the management server 210 requests the FPGA server 220 that has executed the task to acquire intermediate data during normal operation, and the execution result during normal operation Intermediate data is acquired (409). Then, the task control unit 211 of the management server 210 requests the other FPGA server to execute the task that has become impossible to execute due to a circuit failure, for example, by providing the acquired intermediate data, and continues the task execution ( 410). When the execution of the task by the other FPGA server is completed, the management server 210 returns the execution result of the task to the client server (411).

  In addition, in the FPGA server 220 in which a circuit failure is found, a checking circuit (diagnostic circuit) is written and operated in a block in which a circuit in which a circuit failure is found in the FPGA circuit unit 225 is written, and the FPGA circuit monitoring unit 227 performs the operation. Identify the faulty block. The checking circuit is a circuit that can identify a failed block when a hardware error occurs. As the checking circuit, for example, a circuit that can obtain information indicating a failure location by detecting a data pattern output when a certain data pattern is input is applicable.

  When a normal operation is confirmed in the checking circuit as a result of writing and operating the checking circuit in the block in which the circuit in which the circuit failure is found is written (shown in FIG. 4A), it is shown in FIG. As described above, the FPGA circuit monitoring unit 227 determines that the circuit failure is a soft error. In this case, the FPGA server 220 in which a circuit failure is found can be restored by countermeasures against soft errors in which the original circuit information is rewritten in the FPGA circuit unit 225.

  Further, when a failure block is identified as a result of writing and operating a checking circuit in a block in which a circuit in which a circuit failure is found is written, as shown in FIG. 4B, the FPGA circuit monitoring unit 227 It is determined that the circuit failure is a hard error (421, 422, 423). In this case, the FPGA circuit monitoring unit 227 notifies the circuit information management unit 222 of the failure block identified as the discovered circuit failure being a hard error.

  The circuit information management unit 222 that has been notified that the circuit failure is a hard error searches the circuit information stored in the circuit information storage unit 223 for circuit information that uses the specified failure block and deletes it. . In addition, the circuit information management unit 222 notifies the management server 210 of the task being executed and the failed block, and synthesizes new circuit information that avoids the failed block (does not use the failed block). (424).

  In the management server 210 that has received a request to synthesize new circuit information that avoids the failed block, the circuit information synthesis unit 213 re-synthesizes circuit information that avoids the failed block based on the notified task and the failed block. (425). When the circuit information combining unit 213 of the management server 210 completes the resynthesis of the circuit information avoiding the failed block, the circuit information combining unit 213 sends the recombined circuit information to the FPGA server 220 (426). The re-synthesized circuit information is stored in the circuit information storage unit 223 of the FPGA server 220. Thereby, the FPGA server 220 can execute a task that cannot be executed due to a circuit failure using another block.

  Next, processing related to circuit information when a failure occurs (when a hardware error occurs) in this embodiment will be described. FIG. 5A to FIG. 5F are diagrams for explaining processing related to circuit information when a failure occurs in the present embodiment. As shown in FIG. 5A, the circuit information storage unit 223 of the FPGA server 220 stores circuit information 521 of a logic circuit that processes task A, circuit information 522 of a logic circuit that processes task B, and task C. It is assumed that circuit information 523 and 524 of the logic circuit to be processed is stored.

  First, as shown in FIG. 5A, circuit information 524 of a logic circuit that processes task C is written in the FPGA circuit unit 225 of the FPGA server 220, and the FPGA circuit unit 225 executes the task C by the circuit 511. It shall be. When the management server 210 requests the FPGA server 220 to execute the task A, as shown in FIG. 5B, circuit information 521 of the logic circuit that processes the task A is written in the FPGA circuit unit 225, and the FPGA The circuit unit 225 starts execution of task A by the circuit 512.

  When the FPGA circuit unit 225 executes the task C by the circuit 511 and executes the task A by the circuit 512, a hard error occurs in the block in the circuit 512 that executes the task A as shown in FIG. Suppose that it was detected. At this time, the circuit information management unit 222 of the FPGA server 220 searches the circuit information 521 to 524 stored in the circuit information storage unit 223 for circuit information using the failed block in which the hard error is detected. . In this example, the circuit information 521 of the logic circuit that processes the task A and the circuit information 523 of the logic circuit that processes the task C are circuit information using the failed block in which the hard error is detected.

  Then, as shown in FIG. 5D, the circuit information management unit 222 deletes the circuit information 521 and 523 from the circuit information storage unit 223 and processes the task A written in the FPGA circuit unit 225. The circuit information 521 of the circuit is deleted. In addition, the circuit information management unit 222 requests the circuit information synthesis unit 213 of the management server 210 to synthesize new circuit information that does not use the failure block for the logic circuit that processes the task A. As a result, as shown in FIG. 5E, circuit information 525 of the logic circuit that processes task A is newly stored in the circuit information storage unit 223. Therefore, as shown in FIG. 5F, the circuit information 525 of the logic circuit that processes the task A is written in the FPGA circuit unit 225, so that the FPGA circuit unit 225 can execute the task A by the circuit 513. .

  As described above, when the FPGA server 220 detects a hardware error (hardware failure) of the FPGA circuit unit 225, the FPGA server 220 identifies the failed block and deletes the circuit information using the identified failed block from the circuit information storage unit 223. To do. Further, the management server 210 re-synthesizes circuit information that avoids the specified failure block in response to a request from the FPGA server 220 and provides the circuit information to the FPGA server 220. As a result, even if a hardware error in the FPGA circuit unit 225 is detected, it is possible to normally operate a circuit that does not use the failed block by specifying the block in which the hardware has failed. Also, by re-synthesizing the circuit information that avoids the specified failure block, it is possible to reconfigure the circuit that avoids the failure block without preparing multiple pieces of circuit information in advance. Tasks that cannot be executed by writing information can be executed.

  In the above-described example, when a circuit failure is detected during task execution, the task is requested to be continued from another FPGA server without trying to continue task execution. As described above, in the case of a soft error, the task may be continuously executed. 6A and 6B are diagrams illustrating another example of a processing flow when a failure occurs in the present embodiment. FIG. 6A shows a case where the circuit failure is a soft error, and FIG. 6B shows a case where the circuit failure is a hard error.

6A and 6B, processes 601 to 607 are the same as the processes 401 to 407 shown in FIGS. 4A and 4B, and thus the description thereof is omitted.
When a circuit failure in the FPGA circuit unit 225 is notified to the task management unit 221, the FPGA server 220 adds a checking circuit (diagnostic circuit) to the block in which the circuit where the circuit failure is found in the FPGA circuit unit 225 is written. The operation is performed by writing, and the failure block is specified by the FPGA circuit monitoring unit 227.

  As a result of writing and operating the checking circuit, if the normal operation is confirmed in the checking circuit (not indicating a block failure), the FPGA circuit monitoring unit 227, as shown in FIG. Is a soft error. In this case, the FPGA server 220 restores the logic circuit that executes the task requested to be executed by the software error countermeasure that rewrites the original circuit information in the FPGA circuit unit 225 (608).

  Thereafter, the task is continuously executed from the continuation of the previous normal operation (for example, from the recovery point storing the intermediate data during the normal operation) (609). Then, the FPGA circuit monitoring unit 227 appropriately checks the normal operation of the FPGA circuit unit 225 (610), and the task management unit 221 acquires the execution result from the execution result storage unit 226 and sends it to the management server 210 (611). When the task execution is completed, the management server 210 returns the task execution result to the client server (612). By controlling in this way, when the circuit failure is a soft error, the task processing can be continuously executed without requesting another FPGA server.

  Further, as a result of writing and operating the checking circuit, if normal operation cannot be confirmed by the checking circuit, the FPGA circuit monitoring unit 227 determines that the circuit failure is a hard error as shown in FIG. 6B. (621, 622). In this case, the FPGA circuit monitoring unit 227 notifies the task management unit 221 and the circuit information management unit 222 that the circuit failure is a hard error, and the task management unit 221 notifies the management server 210 of the task execution failure. (623).

  Upon receiving notification of task execution failure, the task control unit 211 of the management server 210 requests the FPGA server 220 that has executed the task to acquire intermediate data during normal operation, and the execution result during normal operation Intermediate data is acquired (624). Then, the task control unit 211 of the management server 210 requests the other FPGA server to execute the task that has become unexecutable by providing the acquired intermediate data or the like, and continues the task execution (625). When the execution of the task by the other FPGA server is completed, the management server 210 returns the execution result of the task to the client server (626).

  In addition, the FPGA server 220 in which the hardware error is found identifies the failed block using the checking circuit written in the FPGA circuit unit 225 (627). When the failed block is specified, the FPGA circuit monitoring unit 227 notifies the circuit information management unit 222 of the specified failed block. The circuit information management unit 222 searches for and deletes circuit information that uses the specified failure block from the circuit information stored in the circuit information storage unit 223. Further, the circuit information management unit 222 notifies the management server 210 of the task being executed and the failed block, and requests the management server 210 to synthesize new circuit information that avoids the failed block (628).

  In the management server 210 that has received a request to synthesize new circuit information that avoids the failed block, the circuit information synthesis unit 213 re-synthesizes circuit information that avoids the failed block based on the notified task and the failed block. (629). When the circuit information combining unit 213 of the management server 210 completes the resynthesis of the circuit information avoiding the failed block, the circuit information combining unit 213 sends the recombined circuit information to the FPGA server 220 (630). The re-synthesized circuit information is stored in the circuit information storage unit 223 of the FPGA server 220. Thereby, the FPGA server 220 can execute a task that cannot be executed due to a circuit failure using another block.

  In the example described above, in the processing shown in FIGS. 4B and 6B, the processing of the task that has become impossible to execute is requested to another FPGA server, but a circuit failure occurs. In the FPGA server, the circuit information that does not use the failed block may be written in the FPGA circuit unit 225 and the processing of the task that cannot be executed may be continuously executed. For example, in the case where a circuit failure has occurred in the FPGA server in which a circuit failure has occurred when the processing of a task that has become unexecutable cannot be requested to another FPGA server because circuit resources (resources) are not available in another FPGA server. Circuit information that is not used may be written in the FPGA circuit unit 225 to continue the processing of the task that has become impossible to execute.

  In the above-described example, a management server is provided to allocate tasks requested from the client server and to synthesize circuit information of circuits that process the tasks. As shown in FIG. 7, the same operation as that of the above-described embodiment can be realized by providing the FPGA server with a function of synthesizing circuit information of a circuit that processes a task. FIG. 7 is a diagram illustrating another functional configuration example of the FPGA server according to the present embodiment.

  The FPGA server 710 includes a task management unit 711, a circuit source storage unit 712, a circuit information synthesis unit 713, a circuit information management unit 714, a circuit information storage unit 715, a circuit information writing unit 716, an FPGA circuit unit 717, and an execution result storage unit 718. , And an FPGA circuit monitoring unit 719. The task management unit 711 is an example of a control unit, the circuit information synthesis unit 713 is an example of a synthesis unit, the circuit information management unit 714 is an example of a management unit, and the circuit information storage unit 715 is an example of a storage unit. The FPGA circuit unit 717 is an example of a reconstruction device, and the FPGA circuit monitoring unit 719 is an example of a detection unit.

  The task management unit 711, the circuit information synthesis unit 713, the circuit information management unit 714, the circuit information writing unit 716, and the FPGA circuit monitoring unit 719 are realized by, for example, the CPU 21 of the FPGA server reading and executing a program from the storage unit 22. Is done. In addition, the circuit source storage unit 712, the circuit information storage unit 715, and the execution result storage unit 718 are realized by the storage unit 22 of the FPGA server, for example, and the FPGA circuit unit 717 is realized by the FPGA 23 of the FPGA server, for example.

  The task management unit 711 receives a task processing execution request from the client server, and writes circuit information of a logic circuit that processes the task into the FPGA circuit unit 717 by the circuit information writing unit 716 and performs control to execute the task. Also, the task management unit 711 returns the task execution result stored in the execution result storage unit 718 to the client server.

  The circuit source storage unit 712 stores the source code of the logic circuit that processes each task. The circuit information synthesis unit 713 synthesizes circuit information from the logic circuit source code stored in the circuit source storage unit 712 and provides the circuit information management unit 714 with the circuit information. In addition, when the circuit information synthesis unit 713 receives a request for re-synthesis of new circuit information avoiding the failed block from the circuit information management unit 714, the circuit information composing the logic circuit while avoiding the failed block is stored in the circuit source. Based on the source code stored in the unit 712, it is re-synthesized and provided to the circuit information management unit 714.

  The circuit information management unit 714 stores the circuit information provided from the circuit information synthesis unit 713 in the circuit information storage unit 715. When the FPGA circuit monitoring unit 719 detects a hardware error in the FPGA circuit unit 717 and notifies a failure block, the circuit information management unit 714 detects the failure from the circuit information stored in the circuit information storage unit 715. Delete the circuit information that uses the block. The circuit information management unit 714 requests the circuit information synthesis unit 713 to re-synthesize new circuit information that avoids the failed block.

  Each of the circuit information storage unit 715, the circuit information writing unit 716, the FPGA circuit unit 717, the execution result storage unit 718, and the FPGA circuit monitoring unit 719 includes the circuit information storage unit 223, the circuit information writing unit 224, Since this is the same as the FPGA circuit unit 225, the execution result storage unit 226, and the FPGA circuit monitoring unit 227, description thereof is omitted.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
The following additional notes are disclosed with respect to the above-described embodiment.

(Appendix 1)
A reconfigurable device having a plurality of logic programmable blocks, the circuit configuration being changeable by reconfiguring the blocks based on circuit information;
A synthesis unit that synthesizes the circuit information from the source code of the circuit that processes the task;
A detection unit for detecting a failure of the reconfigurable device,
When the detection unit detects a hardware failure of the reconfigurable device, the detection unit identifies the block having the hardware failure,
The information processing apparatus characterized in that the combining unit combines the circuit information avoiding the identified hardware-failed block.
(Appendix 2)
When a hardware failure of the reconfigurable device is detected, the synthesis unit synthesizes the circuit information of a circuit that processes a task executed in the identified hardware-failed block. The information processing apparatus according to attachment 1.
(Appendix 3)
A storage unit for storing the circuit information synthesized by the synthesis unit;
And a management unit that deletes, from the storage unit, the circuit information that uses the identified hardware-failed block when a hardware failure of the reconfigurable device is detected. The information processing apparatus described.
(Appendix 4)
A control unit that performs control related to a task executed by the reconfigurable device;
When a hardware failure of the reconfigurable device is detected, the control unit requests another information processing apparatus to process a task that has been executed in the identified hardware-failed block. The information processing apparatus according to any one of appendices 1 to 3.
(Appendix 5)
A control unit that performs control related to a task executed by the reconfigurable device;
When a hardware failure of the reconfigurable device is detected, the control unit continues the processing of the task executed in the block by using the circuit information that does not use the identified hardware-failed block The information processing apparatus according to any one of appendices 1 to 3, wherein:
(Appendix 6)
A first server having a synthesis unit that synthesizes circuit information from the source code of the circuit that processes the task;
A reconfigurable device having a plurality of logic programmable blocks and reconfiguring the block based on the circuit information; and a detector for detecting a failure of the reconfigurable device. And a second server capable of communicating with the first server,
When the detection unit detects a hardware failure of the reconfigurable device, the second server identifies the block having the hardware failure by the detection unit and synthesizes the circuit information that avoids the block. Ask the first server,
In response to a request from the second server, the first server synthesizes the circuit information avoiding the identified hardware-failed block by the synthesizer and provides the synthesizer with the circuit information. An information processing system characterized by this.
(Appendix 7)
When a hardware failure of the reconfigurable device is detected, the first server synthesizes the circuit information of a circuit that processes a task executed in the identified hardware-failed block by the synthesizer. The information processing system according to appendix 6, wherein the information processing system is provided to the second server.
(Appendix 8)
The second server is
A storage unit for storing the circuit information provided from the first server;
Appendix 6 or 7 further comprising: a management unit that deletes the circuit information that uses the identified hardware-failed block from the storage unit when a hardware failure of the reconfigurable device is detected. The information processing system described.
(Appendix 9)
An information processing method for an information processing apparatus having a reconfigurable device having a plurality of logic programmable blocks and reconfiguring the block by reconfiguring the block based on circuit information,
When the detection unit of the information processing apparatus detects a hardware failure of the reconfigurable device, the hardware failure block is identified,
A synthesizing unit of the information processing apparatus synthesizes the circuit information avoiding the identified hardware-failed block from source code of a circuit that processes a task.
(Appendix 10)
The information processing apparatus includes a storage unit that stores the circuit information combined by the combining unit.
The information processing method according to claim 9, wherein when a hardware failure of the reconfigurable device is detected, the circuit information that uses the identified hardware-failed block is deleted from the storage unit.
(Appendix 11)
A computer of an information processing apparatus having a reconfigurable device having a plurality of logic programmable blocks and reconfiguring the blocks by reconfiguring the blocks based on circuit information.
When the failure of the reconfigurable device is detected and a hardware failure of the reconfigurable device is detected, a process of specifying the hardware-failed block;
A program for executing, from a source code of a circuit that processes a task, a process of synthesizing the circuit information that avoids the identified hardware-failed block.
(Appendix 12)
A computer of an information processing apparatus having a reconfigurable device having a plurality of logic programmable blocks and reconfiguring the blocks by reconfiguring the blocks based on circuit information.
When the failure of the reconfigurable device is detected and a hardware failure of the reconfigurable device is detected, a process of specifying the hardware-failed block;
A computer-readable recording medium having recorded thereon a program for executing processing for synthesizing the circuit information avoiding the identified hardware-failed block from source code of a circuit for processing a task .

10 Management server 20 FPGA server 11, 21 CPU
12, 22 Storage unit 23 FPGA (reconfiguration device)
210 management server 211 task control unit 212, 712 circuit source storage unit 213, 713 circuit information synthesis unit 220, 710 FPGA server 221, 711 task management unit 222, 714 circuit information management unit 223, 715 circuit information storage unit 224, 716 circuit Information writing unit 225, 717 FPGA circuit unit 226, 718 Execution result storage unit 227, 719 FPGA circuit monitoring unit

Claims (8)

A reconfigurable device having a plurality of logic programmable blocks, the circuit configuration being changeable by reconfiguring the blocks based on circuit information;
A synthesis unit that synthesizes the circuit information from the source code of the circuit that processes the task;
A detection unit for detecting a failure of the reconfigurable device,
When the detection unit detects a hardware failure of the reconfigurable device, the detection unit identifies the block having the hardware failure,
The information processing apparatus characterized in that the combining unit combines the circuit information avoiding the identified hardware-failed block.   When a hardware failure of the reconfigurable device is detected, the synthesis unit synthesizes the circuit information of a circuit that processes a task executed in the identified hardware-failed block. The information processing apparatus according to claim 1. A storage unit for storing the circuit information synthesized by the synthesis unit;
The management unit that deletes the circuit information that uses the identified hardware-failed block from the storage unit when a hardware failure of the reconfigurable device is detected. 2. The information processing apparatus according to 2. A control unit that performs control related to a task executed by the reconfigurable device;
When a hardware failure of the reconfigurable device is detected, the control unit requests another information processing apparatus to process a task that has been executed in the identified hardware-failed block. The information processing apparatus according to any one of claims 1 to 3. A control unit that performs control related to a task executed by the reconfigurable device;
When a hardware failure of the reconfigurable device is detected, the control unit continues the processing of the task executed in the block by using the circuit information that does not use the identified hardware-failed block The information processing apparatus according to any one of claims 1 to 3, wherein the information processing apparatus is used. An information processing method for an information processing apparatus having a reconfigurable device having a plurality of logic programmable blocks and reconfiguring the block by reconfiguring the block based on circuit information,
When the detection unit of the information processing apparatus detects a hardware failure of the reconfigurable device, the hardware failure block is identified,
A synthesizing unit of the information processing apparatus synthesizes the circuit information avoiding the identified hardware-failed block from source code of a circuit that processes a task. The information processing apparatus includes a storage unit that stores the circuit information combined by the combining unit.
The information processing method according to claim 6, wherein when a hardware failure of the reconfigurable device is detected, the circuit information that uses the identified hardware-failed block is deleted from the storage unit. A computer of an information processing apparatus having a reconfigurable device having a plurality of logic programmable blocks and reconfiguring the blocks by reconfiguring the blocks based on circuit information.
When the failure of the reconfigurable device is detected and a hardware failure of the reconfigurable device is detected, a process of specifying the hardware-failed block;
A program for executing, from a source code of a circuit that processes a task, a process of synthesizing the circuit information that avoids the identified hardware-failed block.

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