JP2016170629A - Image processor, and control method and program thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a reconfiguration time in the case of performing the reconfiguration of a plurality of partial reconfiguration parts, in an image processor having a dynamic part reconfiguration circuit and using a reconfigurable circuit while partially reconfiguring the reconfigurable circuit.SOLUTION: The image processor includes means for generating reconfigurable circuit configuration information for a plurality of partial reconfiguration parts from circuit configuration information corresponding to each partial reconfiguration part in the case of reconfiguring a plurality of partial reconfiguration parts having the same unit for performing a partial reconfiguration, and a partial reconfiguration is executed on the basis of the generated circuit configuration information.SELECTED DRAWING: Figure 7

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a program, and more particularly to an image processing apparatus using a reconfigurable circuit, a control method thereof, and a program.

  Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) capable of changing the internal logic circuit configuration are well known. Generally, PLDs and FPGAs switch internal logic blocks by writing logic circuit configuration information stored in a non-volatile memory such as ROM to a configuration memory (configuration memory) that is an internal volatile memory at startup. . In addition, the writing time to the configuration memory is shortened by expanding the logic circuit configuration information stored in the non-volatile memory such as ROM into the memory such as DRAM that can be read before writing to the configuration memory. Sometimes.

Some FPGAs can rewrite a specific area, not the entire chip, and such rewriting is called partial reconfiguration. In particular, performing partial reconfiguration without stopping other operating circuits is called dynamic partial reconfiguration. In dynamic partial reconfiguration, the entire configuration memory is not rewritten at the time of dynamic reconfiguration, but only a part of the configuration memory area is rewritten to realize partial reconfiguration of the logic block inside the FPGA. Is possible. As a technology using this dynamic partial reconfiguration, in pipeline configuration processing, circuit configuration information is read sequentially from the nonvolatile memory, and data processing is performed by reconfiguring the reconfigurable circuit sequentially from the partial circuit at the top of the pipeline. A technique is disclosed. (For example, refer to Patent Document 1.)
Recent image processing devices such as MFP (Multi Function Printer) can select multiple processes (copy job, print job, SEND job, etc.) according to user requests. Realized by hardware or software. When a reconfigurable circuit such as an FPGA is applied as image processing hardware of the image processing apparatus, the circuit configuration can be dynamically and partially switched for each function as described above. As a result, various image processing functions can be realized with few hardware resources.

JP 2011-186981 A

  When reconfiguring a logic circuit for multiple partial reconfiguration areas when performing dynamic partial reconfiguration, clear the logic circuit information and set new logic circuit configuration information for each partial reconfiguration area. There is a need to. Therefore, when reconstructing a plurality of partial reconstruction areas, it takes time for the number of partial reconstruction areas to be reconstructed.

  The present invention has been made in view of the above-described problems. In an image processing apparatus capable of dynamic partial reconfiguration, the logic circuits of a plurality of partial reconfiguration units are reconfigured while maintaining flexible rewriting performance. The object is to reduce the time required for dynamic partial reconfiguration when configuring.

  In order to achieve the above object, the present invention has the following configuration.

An image processing apparatus having a reconfigurable circuit that can be reconfigured in a predetermined reconfiguration unit by rewriting circuit configuration data stored in a configuration memory,
Storage means for storing circuit configuration data corresponding to a circuit configured in the reconstruction area for each reconstruction area to be reconfigured;
In the case where a plurality of reconstruction areas are included in the reconstruction unit, a synthesis unit that synthesizes rewriting data including the circuit configuration data according to a circuit configured in each reconstruction area;
Rewriting means for rewriting the circuit configuration data of the configuration memory in the reconfiguration unit with the rewriting data after synthesis by the synthesizing means.

  According to the present invention, in an image processing apparatus capable of dynamic partial reconfiguration, it is possible to simultaneously switch the logic circuit configuration for a plurality of partial reconfiguration regions, and the time required for partial reconfiguration of a plurality of regions Can be shortened. In addition, the configuration data prepared in advance is not different from the conventional configuration data and does not increase resources for storage.

It is a block diagram which shows an example of a structure of an image processing apparatus. It is a block diagram which shows the structure in connection with a dynamic partial reconstruction in an image processing apparatus. It is a figure which shows an example of the storage method of the circuit information comprised by the partial reconstruction part. It is a figure which shows the example of a design of a partial reconstruction part. It is a figure for demonstrating in detail the structure of configuration data. It is a figure which shows the storage image of the configuration data stored in RAM It is a flowchart which shows job execution process control. It is a flowchart which shows the production | generation process of the configuration data with respect to a some partial reconstruction part.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
[Configuration of image processing device]
FIG. 1 is a block diagram illustrating the configuration of an image processing apparatus according to an embodiment of the present invention. The image processing apparatus 100 according to the present embodiment includes an operation unit 103 for a user using the image processing apparatus 100 to perform various operations, a scanner unit 109 that reads image information in accordance with instructions from the operation unit 103, and image data. And a printer unit 107 that prints on paper. The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp (not shown), a scanning mirror, and the like for reading a document. The printer unit 107 includes a CPU (not shown) that controls the printer unit 107, a photoconductor drum (not shown) and a fixing device (not shown) that perform image formation and fixing. The operation unit 103 is connected to the bus 120 via the operation unit I / F 113.

In addition, the image processing apparatus 100 includes a CPU 101 that comprehensively controls the operation of the image processing apparatus 100, and executes control software for controlling each unit of the image processing apparatus. The image processing apparatus 100 also includes a ROM 104 that stores a program executed by the CPU 101. The image processing apparatus 100 also includes an HDD 116 connected via an HDD I / F 115 for storing a spool of image processing data and all configuration data used by the image processing apparatus 100. The configuration data is also called circuit configuration data or yellow configuration information. The image processing apparatus 100 is a system work memory for operating the CPU 101, is also an image memory for temporarily storing image data, and has a RAM 111 for temporarily storing configuration data. By copying the configuration data from the HDD 116 having a low access speed to the RAM 111 having a high access speed in advance and temporarily holding the configuration data, the configuration data can be read from the RAM 111 at a high speed. Such a method is called preloading. Note that the high-speed memory used for preloading is not limited to the RAM 111 that is the work memory of the system. Other preload memories include a dedicated preload memory having a plurality of BANKs as used in a block RAM inside the FPGA, a dynamic reconfigurable processor (DRP), and the like. The image processing apparatus 100 also includes a RAM 111 and a memory controller 110 that controls writing and reading operations to the RAM 111. The memory controller 110 is connected to the system bus 120 and the image bus 121 and controls access to the RAM 111.
The image processing apparatus 100 includes an FPGA 140 that constitutes an image processing circuit or the like as a reconfigurable device. In this embodiment, an FPGA is described as an example of a reconfigurable device. However, a configuration in which a reconfigurable device other than an FPGA is connected may be used.
The image processing apparatus 100 includes a configuration controller 130 that controls the circuit configuration (configuration) of the FPGA under the control of the CPU 101.

  The FPGA 140 is dynamically rewritable and partially rewritable. That is, while a circuit configured as a part of the reconfiguration unit of the FPGA 140 is operating, another circuit can be reconfigured in another part that does not overlap with the part occupied by the circuit.

  The image processing apparatus 100 also includes a scanner I / F 108 that receives image data from the scanner unit 109 and a printer I / F 106 that outputs image data to the printer unit 107. The FPGA 140, the scanner I / F 108, and the printer I / F 106 are connected to an image bus 121 for transferring image data to be processed.

  The image processing apparatus 100 communicates (transmits / receives) with a general-purpose computer (not shown) on the network via the network I / F 102 as a communication unit. The image processing apparatus 100 communicates (transmits / receives) with a general-purpose computer (not shown) connected to the image processing apparatus 100 via the USB I / F 114. The image processing apparatus 100 includes a ROM I / F 112 that controls a program executed by the CPU 101 and writing / reading operations to / from the ROM 104. The image processing apparatus 100 also includes a system bus 120 that connects the CPU 101, the network I / F 102, the operation unit 103, the ROM I / F 112, the configuration controller 130, and the FPGA 140 to each other. The CPU 101 performs parameter settings for the FPGA 140, the scanner I / F 108, and the printer I / F 106 via the system bus 120.

  In this embodiment, the configuration data is stored in the HDD 116, and is copied and stored in advance in the RAM 111 by the CPU 101 before the image processing apparatus 100 starts processing. The storage location of the configuration data is not limited to the inside of the image processing apparatus 100. For example, the configuration data may be downloaded from an external server via the network as needed and stored in the RAM 111.

[Configuration related to partial reconfiguration]
Next, a configuration relating to partial reconstruction in the image processing apparatus according to the present embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration particularly related to the partial reconstruction of the image processing apparatus 100.

  The CPU 101, configuration controller 130, RAM 111, HDD 116, and FPGA 140 are as described above with reference to FIG. The FPGA 140 further includes a partial reconstruction unit (PR1) 201, a partial reconstruction unit (PR2) 202, a partial reconstruction unit (PR3) 203, and a partial reconstruction unit (PR4) 204 therein. Each partial reconstruction unit can dynamically rewrite an image processing circuit or the like. Dynamic rewriting means, for example, that the partial reconfiguration unit to be rewritten can be rewritten while operating other circuits.

  In this embodiment, an example in which a circuit having an image processing function is configured in the partial reconstruction unit has been described. Needless to say, a circuit other than the image processing function can be configured in the partial reconstruction unit. .

  The configuration controller 130 has a function of managing partial reconfiguration of each partial reconfiguration unit 201, 202, 203, 204. For example, the availability of each partial reconfiguration unit is managed, such as whether each partial reconfiguration unit 201, 202, 203, 204 is currently used for processing. Then, it is determined whether or not each partial reconstruction unit can be rewritten. The CPU 101 instructs the configuration controller 130 to start configuration data transfer with reference to the determination whether each partial reconfiguration unit can be rewritten based on the information managed by the configuration controller 130. The configuration controller 130 reads necessary configuration data from the RAM 111 under the instruction of the CPU 101 and writes the configuration data to the partial reconfiguration units 201, 202, 203, 204.

[Configuration data configuration]
Next, a general method for storing configuration data configured in the partial reconfiguration units 201 to 204 of the FPGA 140 will be described with reference to FIG. FIG. 3 is an example of configuration data configured in each of the partial reconfiguration units 201 to 204 of the FPGA 140 stored in the HDD 116.

  The HDD 116 stores a plurality of configuration data necessary for partial reconfiguration. The configuration data 300 for PR1 represents configuration data that can be configured in the partial reconfiguration unit (PR1) 201. FIG. 3 shows an example in which there are four functions A, B, C, and D that can be configured in the partial reconfiguration unit (PR1) 201. The configuration data 301 is configuration data for configuring a function A circuit in PR1. Similarly, the configuration data 302 represents the function B circuit configuration in PR1, the configuration data 303 represents the function C circuit configuration in PR1, and the configuration data 304 represents the configuration data for configuring the function D circuit configuration in PR1. .

  The configuration data 310 for PR2 represents configuration data that can be configured in the partial reconfiguration unit (PR2) 202. The configuration data 310 for PR2 also stores configuration data for four functions A, B, C, and D, and the partial reconfiguration unit (PR2) 202 can be configured by switching the four functions. Is possible.

  The configuration data 320 for PR3 represents configuration data that can be configured in the partial reconfiguration unit (PR3) 203. The configuration data 320 for PR3 also stores configuration data for four functions A, B, C, and D, and the partial reconfiguration unit (PR3) 203 can be configured by switching the four functions. Is possible.

  The configuration data 330 for PR4 represents configuration data that can be configured in the partial reconfiguration unit (PR4) 204. The configuration data 330 for PR4 also stores configuration data for the four functions A, B, C, and D, and the partial reconfiguration unit (PR4) 204 can be configured by switching the four functions. Is possible.

  As described above, it is necessary to prepare configuration data for each partial reconfiguration unit. For example, in order to configure the circuit configuration of the function A into the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202, the same function is realized such as the function A301 for PR1 and the function B302 for PR2. Even in this case, it is necessary to prepare different configuration data depending on the configuration location.

  In the above description, the FPGA 140 has four partial reconfiguration units, and the functions configured in the partial reconfiguration unit have been described by taking four cases of A, B, C, and D as an example. The reason for limiting the number of areas for partial reconstruction and the number of functions configured there to 4 is only to make the explanation easy to understand. The number of areas for partial reconstruction and the number of functions configured there are limited to four. Of course there is no need to be done.

[Description of configuration data for partial reconfiguration]
An object of the present embodiment is to reduce the time required for partial reconfiguration and to reduce the configuration data capacity for partial reconfiguration. Therefore, in describing the method according to the present embodiment, the configuration of the configuration data for partial reconfiguration will be described in detail with reference to FIGS. 4 and 5.

  First, a design example of the partial reconfiguration unit of the FPGA 140 will be described with reference to FIG. FIG. 4 is a diagram illustrating a design example of the partial reconfiguration unit in the FPGA of the image processing apparatus according to the present embodiment. In general, when performing partial reconfiguration of an FPGA, it is determined which area inside the FPGA is used as a partial reconfiguration unit. Specifically, the size of the partial reconstruction unit, the number of partial reconstruction units, and in which area of the FPGA the partial reconstruction unit is laid out are determined. The size of the partial reconstruction unit, the number of partial reconstruction units, and the layout of the partial reconstruction unit described above can be freely designed. In the following description, the parts indicated by the partial reconstruction unit (PR1) 201, partial reconstruction unit (PR2) 202, partial reconstruction unit (PR3) 203, and partial reconstruction unit (PR4) 204 in FIG. A region that is configured and a region that is not partially reconfigured is called a fixed portion (or fixed region) 410.

  The partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202 are located in the same column (row), and the partial reconstruction unit (PR3) 203 and the partial reconstruction unit (PR4) 204 are in the same column (column). Column). As described above, when performing partial reconfiguration, it is necessary to have configuration data for partial reconfiguration. When performing partial reconfiguration, the circuit configuration of the partial reconfiguration unit is reconfigured by reading the configuration data from the RAM and writing it to the configuration memory inside the FPGA. However, when performing partial reconfiguration, the configuration memory inside the FPGA cannot be rewritten in a free unit, and there is a device that has a minimum unit for rewriting the configuration memory. In this example, the column corresponds to a region obtained by dividing the FPGA, which is a reconfigurable circuit, into strips having a predetermined width.

  For example, there are devices in which an FPGA column (row) is a minimum unit of rewriting (also referred to as a reconstruction unit), and there are devices in which a row (row) or a specific square area is a minimum unit of rewriting. In the present embodiment, a column (row) is a minimum unit for rewriting, and is an FPGA configured by a minimum rewriting unit 400 (400a to 400h) divided into eight in the column (row) direction. In other words, the FPGA is reconfigured for a region to be partially reconfigured included in each of the columns 400a to 400h or a combination thereof.

  When the FPGA column 400 is the minimum rewrite unit, it is not possible to rewrite only the configuration memory unit that determines the circuit configuration of the partial reconfiguration units 201 to 204. When rewriting the partial reconstruction unit (PR1) 201 or the partial reconstruction unit (PR2) 202, the minimum rewrite in the same column (column) as the partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202 It is necessary to rewrite the PR1PR2 reconstruction area 401 composed of the units 400b, 400c, and 400d. That is, when rewriting the circuit configuration of the partial reconfiguration unit (PR1) 201, not only the circuit information of the partial reconfiguration unit (PR1) 201 but also the corresponding PR1PR2 reconfiguration of the fixed unit 410 in the PR1PR2 reconfiguration area 401 Data to be written to the configuration memory unit that determines the circuit configuration of the region fixing unit 411 and the partial reconfiguration unit (PR2) 202 is also required.

  FIG. 5A is a diagram for explaining in detail the structure of the configuration data necessary for reconfiguring only the partial reconfiguration unit (PR1) 201. Here, the case where the minimum rewrite unit of the configuration memory (configuration memory) for partial reconfiguration is a column will be described as an example.

  The configuration data 500 is configuration data necessary for configuring a circuit having a specific function in the partial reconfiguration unit (PR1) 201, and is hereinafter referred to as configuration data 500 for PR1.

  The configuration data 501 is a part of the PR1 configuration data 500, and is hereinafter referred to as PR1 AND configuration data 501. The logical product configuration data 501 for PR1 is clear data for selectively clearing the configuration memory (configuration memory) corresponding to the partial reconfiguration unit to be reconfigured. The configuration data 502 is a part of the logical product configuration data 501 for PR1, and indicates data to be written in the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201. In the sense that it is data for logical product, it is called intra-PR1 logical product configuration data 502. The intra-PR1 logical product configuration data 502 corresponds to PR1 and is data for clearing PR1 to 0 by logical product operation. The configuration data 503 is a part of the logical product configuration data 501 for PR1, and indicates data to be written in the configuration memory unit that determines the circuit configuration other than the partial reconfiguration unit (PR1) 201. This is called configuration data 503. The PR1 extra logical AND configuration data 503 corresponds to an area obtained by removing PR1 from the PR1PR2 reconfiguration area 401, and is data for leaving the area as it is even by the logical product operation.

  The configuration data 511 is a part of the PR1 configuration data 500, and is hereinafter referred to as PR1 OR configuration data 511. The PR1 OR configuration data 511 is circuit configuration data for selectively rewriting a configuration memory (configuration memory) corresponding to a partial reconfiguration unit to be reconfigured. The configuration data 512 is a part of the OR configuration data 511 for PR1, and indicates data to be written in the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201. This is called data 512. The intra-PR1 logical sum configuration data 512 corresponds to PR1 and is new configuration data reconfigured to PR1 by a logical sum operation. The configuration data 513 is a part of the OR configuration data 511 for PR1, and indicates data to be written in the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201. This is called data 513. The PR1 extra-OR configuration data 513 corresponds to an area obtained by removing PR1 from the PR1PR2 reconfiguration area 401, and is data for leaving the area as it is even by an OR operation.

  The partial reconfiguration unit (PR1) 201 is reconfigured by transmitting the above-described PR1 AND configuration data 501 and PR1 OR configuration data 511 to the FPGA.

  The operation of partial reconstruction will be described below. First, the logical product configuration data 501 for PR1 and the data already written in the configuration memory unit for determining the circuit configuration of the PR1PR2 reconfiguration area 401 are obtained, and the data obtained by the logical product is the configuration memory. Is written to. Thereby, only the data of the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201 is cleared to 0, and the configuration memory that determines the circuit configuration of the area other than the partial reconfiguration unit (PR1) 201 In this case, the same data as the data that has already been written is written, and the circuit configuration is not changed.

  Next, the logical OR configuration data 511 for PR1 and the data already written in the configuration memory unit for determining the circuit configuration of the PR1PR2 reconfiguration area 401 are logically summed, and the data obtained by the logical sum is configured. Written to memory. As a result, the desired circuit configuration is written in the partial reconfiguration unit (PR1) 201, and the data already written in the configuration memory that determines the circuit configuration in the area other than the partial reconfiguration unit (PR1) 201 The same data is written, and the circuit configuration is not changed.

  According to the procedure described above, it is possible to rewrite the circuit configuration of only the partial reconstruction unit (PR1) 201 without stopping the circuit operation in the area other than the partial reconstruction unit (PR1) 201.

  FIG. 5B is a diagram for explaining in detail the structure of configuration data necessary to reconfigure the partial reconfiguration unit (PR2) 202 in the image processing apparatus according to the embodiment of the present invention. . Similar to the procedure described in FIG. 5A, the partial reconfiguration unit (PR2) 202 only is rewritten by sequentially writing the PR2 logical product configuration data 521 and the PR2 logical sum configuration data 531 into the configuration memory. Configuration is possible.

  That is, when partial reconstruction of the partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202 is performed, as described with reference to FIGS. It is necessary to write a total of four times of configuration data: logical product configuration data 501, logical sum configuration data 511 for PR1, logical product configuration data 521 for PR2, and logical sum configuration data 531 for PR2.

  FIG. 5C is a diagram for explaining the configuration of the PR1PR2 configuration data 540 for simultaneously rewriting the partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202 according to the present embodiment.

  The PR1PR2 configuration data 540 includes PR1PR2 logical product configuration data 541 and PR1PR2 logical sum configuration data 551.

  The logical product configuration data 541 for PR1PR2 includes the logical product configuration data 501 for PR1, which is configuration data for clearing the data of the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201 to 0, It is generated by logical product with PR2 logical product configuration data 521 which is configuration data for clearing the data in the configuration memory unit that determines the circuit configuration of the reconfiguration unit (PR2) 202 to zero. That is, the logical product configuration data 541 for PR1PR2 can clear only the data in the configuration memory unit that determines the circuit configuration of both the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202 to 0. it can. Further, the logical product configuration data 541 for PR1PR2 is generated from the logical product of the configuration data for clearing the circuit configuration by taking the logical product with the data already written in the configuration memory unit. The order in which the bit data within does not change.

  The logical product configuration data 551 for PR1PR2 is the logical OR configuration data 511 for PR1, which is configuration data for setting a desired circuit configuration in the data of the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR1) 201. And the logical sum configuration data 531 for PR2, which is configuration data for setting a desired circuit configuration in the data of the configuration memory unit that determines the circuit configuration of the partial reconfiguration unit (PR2) 202. The In other words, the logical product configuration data 541 for PR1PR2 rewrites the data in the configuration memory unit that determines the circuit configurations of both the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202 to a desired circuit configuration. Can do. Also, the logical OR configuration data 551 for PR1PR2 is generated from the logical OR of the configuration data for setting the circuit configuration by taking the logical OR with the data already written in the configuration memory unit. The order in which the bit data within does not change. Thus, the PR1PR2 configuration data 540 is the combined configuration data obtained by combining the PR1 configuration data 500 and the PR2 configuration data 520.

  By using the logical product configuration data 541 for PR1PR2 and the logical sum configuration data 551 for PR1PR2, the circuit operation in the area other than the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202 is stopped without stopping. The reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202 can be partially reconfigured at the same time.

  4 and 5, the case where there are two partial reconstruction units has been described as an example. However, the number of partial reconstruction units is not limited to two, and two or more partial reconstruction units are used. Of course, it is possible to have it, and it is not limited to two.

  Note that the configuration data is also used as rewriting data because it is data used for rewriting in units of columns of the configuration memory. The logical product configuration data is also referred to as clearing data because it is used to clear a partial reconfiguration unit, that is, a reconfiguration area, to be reconfigured. The logical sum configuration data is also referred to simply as circuit configuration data because it is used to configure circuit configuration data in the reconstruction area.

  FIG. 6 is a diagram showing a storage image of circuit information stored in the RAM 111 in the image processing apparatus according to the embodiment of the present invention. Configuration data read from the hard disk 116 is temporarily loaded into the RAM 111 and used for reconfiguration.

  The configuration data 601 is configuration data necessary for configuring the circuit having the function A in the partial reconfiguration unit (PR1) 201, and is stored in the RAM 111 at addresses 0x0000_0000 to 0x0000_1FFF. The PR1 configuration data (function A) 601 includes the PR1 logical product configuration data 501 and the PR1 logical product configuration data 511 described in FIG. 5A, and starts from addresses 0x0000_0100 and 0x0000_0200, respectively. Stored in the area.

The configuration data 602 to 604 are configuration data necessary for configuring the circuit having the function B to the function D in the partial reconfiguration unit (PR1) 201. Similarly to the function A, the configuration data 602 to 604 are used in the PR1 area. The configuration data 611 to 614 includes configuration data necessary for configuring the circuit having the functions A to D in the partial reconfiguration unit (PR2) 202. It is. The PR2 AND configuration data 521 and the PR2 OR configuration data 531 described in FIG. 5B relating to the present embodiment are a part of the PR2 configuration data (function B) 612.

  The configuration data 601 to 614 are data obtained by loading the data stored in the hard disk 116 into the RAM 111. On the other hand, the configuration data 612 is data after synthesis that is synthesized from the configuration data 601 and the configuration data 612 in the manner shown in FIG. The addresses 0x1000_000 to 0x1000_1FFF of the RAM 111 are areas for storing configuration data 612 used when the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202 are partially reconfigured at the same time. This area stores the PR1 configuration data 540 generated from the PR1 configuration data and the PR2 configuration data described in FIG. 5C. The configuration data 540 for PR1PR2 includes the logical product configuration data 541 for PR1PR2 and the logical product configuration data 551 for PR1PR2 described with reference to FIG. .

  FIG. 6 shows an example in which there are four functions A, B, C, and D that can be configured in the partial reconstruction unit (PR1) 201 and the partial reconstruction unit (PR2) 202. The present invention is applicable even when the above functions are provided.

[Explanation of flow during partial reconfiguration]
FIG. 7 is a flowchart showing job execution processing control of the image processing apparatus according to the embodiment of the present invention. 7 is executed by the CPU 101 and the configuration controller 130.

  The flow of partial reconstruction related to the embodiment of the present invention will be described using this flowchart. First, in step S701, the image processing apparatus 100 waits for job reception. If the image processing apparatus 100 receives a job in step S701, the process proceeds to step S702.

  In step S <b> 702, the CPU 101 identifies a function and its area that need to configure a circuit in the FPGA 140 when executing the received job. For example, it is necessary to configure the function A in the partial reconfiguration unit (PR1) 201 and the function B in the partial reconfiguration unit (PR2) 202 for the received job processing. At this time, if a plurality of functions are configured, the plurality of partial reconfiguration units may be determined so that the plurality of partial reconfiguration units configuring the functions share the same column if possible. .

  In step S703, the CPU 101 determines whether the function configured in the FPGA 140 identified in step S702 is for a plurality of partial reconfiguration units on the same column. In step S703, if the function configured in the FPGA 140 is for a plurality of partial reconfiguration units on the same column, the process proceeds to step S704. If the function is other than the above, the process proceeds to step S706.

  In step S704, the CPU 101 determines whether the functions already configured in the plurality of partial reconfiguration units on the same column for received job processing are for a single job. If it is determined in step S704 that the job is for a single job, the process proceeds to step S705. If it is determined that the job is not for a single job, the process proceeds to step S706. If this is not a circuit for a single job, the multiple reconfiguration areas that are the targets of reconfiguration are used by different jobs. This is because it is more reasonable to do this separately. However, even if it is determined that the job is not for a single job, the configuration data may be synthesized by proceeding to step S705. In this case, it is waited until the use of all the plurality of reconstruction areas is completed, but partial reconstruction can be performed. That is, the determination in step S704 is optional.

  In step S <b> 705, the CPU 101 creates configuration data for configuring a plurality of partial reconfiguration units on the same column in the FPGA 140 with functions that need to be configured in the FPGA 140 identified in step S <b> 702. Details of the configuration data creation processing in step S705 will be described later with reference to FIG.

  In step S706, the CPU 101 determines whether processing other than the received job is performed in the partial reconfiguration unit necessary for executing the job received in step S701, and waits until the processing ends.

  In step S707, in order to clear the partial reconfiguration unit, the CPU 101 notifies the configuration controller 130 of the reconfiguration unit logical product configuration data. The reconfiguration unit logical configuration data includes the address and size of the configuration data stored in the RAM 111. For example, in the case of PR1 AND configuration data 501 when the function A is configured in the partial reconfiguration unit (PR1) 201, the address is 0x0000 — 0100 as described in FIG. Further, if the configuration of the function A to the partial reconfiguration unit (PR1) 201 and the configuration of the function B to the partial reconfiguration unit (PR2) 202 are performed simultaneously, the address is the logical product configuration data 541 for PR1PR2. 0x1000_0100.

  Under the instruction of the CPU 101, the configuration controller 130 reads the configuration data for logical product from the RAM 111 and transmits the read data to the FPGA 140. The data transmitted to the FPGA 140 is ANDed with the data already written in the configuration memory inside the FPGA, and the data is written in the configuration memory.

  In step S708, the CPU 101 notifies the configuration controller 130 of the OR configuration data information for the reconfiguration unit in order to configure a circuit in the partial reconfiguration unit. The reconfiguration unit OR configuration data information includes the address and size of configuration data stored in the RAM 111. For example, in the case of PR1 OR configuration data 511 when the function A is configured in the partial reconfiguration unit (PR1) 201, the address is 0x000 — 0200 as described with reference to FIG. Under the instruction of the CPU 101, the configuration controller 130 reads the logical OR configuration data from the RAM 111 and transmits the read data to the FPGA 140. The data transmitted to the FPGA 140 is ORed with the data already written in the configuration memory inside the FPGA, and the data is written in the configuration memory.

  In step S709, the CPU 101 determines whether or not the configuration of the partial reconstruction unit corresponding to the function necessary for job execution received in step S702 is completed. If not completed, the process returns to step S707. Terminates the process of partial reconstruction execution.

  FIG. 8 is a flowchart showing configuration data generation processing (S 705) for a plurality of partial reconfiguration units on the same column, and each procedure is executed by the CPU 101. 8, in the image processing apparatus according to the embodiment of the present invention, the configuration of the function A to the partial reconstruction unit (PR1) 201 and the function to the partial reconstruction unit (PR2) 202 on the same column. A configuration data generation process for simultaneously performing the configuration of B will be described.

  In step S <b> 801, the CPU 101 reads PR1 AND configuration data 501 and PR2 AND configuration data 521 stored in the RAM 111.

  In step S802, the CPU 101 generates a PR1PR2 logical product configuration data 541 by taking the logical product of the PR1 logical product configuration data 501 and the PR2 logical product configuration data 521 read in step S801.

  In step S803, the CPU 101 writes the generated PR1PR2 AND configuration data 541 in the PR1PR2 AND configuration data area (address 0x1000_0100) of the RAM 111.

  In step S804, the CPU 1010 reads the PR1 logical sum configuration data 511 and the PR2 logical sum configuration data 531 stored in the RAM 111.

  In step S805, the CPU 101 calculates the logical sum of the PR1 logical sum configuration data 511 and the PR2 logical sum configuration data 531 read in step S804, and generates PR1PR2 logical sum configuration data 551.

  In step S806, the generated PR1PR2 logical sum configuration data 551 is written in the PR1PR2 logical sum configuration data area (address 0x1000 — 0200) of the RAM 111.

  Through the above processing, configuration data capable of simultaneously reconfiguring the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202 is created.

  As described with reference to FIGS. 7 and 8, in the image processing apparatus capable of partial reconstruction by performing the above control, when reconfiguring a plurality of partial reconstruction units on the same column, a plurality of parts By performing configuration after generating configuration data for reconfiguring the reconfiguration unit at a time, it is possible to reduce the time required for reconfiguration. In addition, in order to generate the configuration data required when reconfiguring the partial reconfiguration unit on the same column, all combinations of the number of partial reconfiguration units and the number of functions configured in each partial reconfiguration are provided. The capacity of the configuration data stored in the memory can be reduced.

[Other Examples]
In the above example, the case where the reconstruction unit is cleared by 0 has been described as an example, but the same method and configuration can be applied when the reconstruction unit is cleared by 1. However, when clearing with 0, the logical product operation of 0 and the area to be cleared is performed, and the portion where the circuit is left is cleared with 1, whereas the logical product operation with 1 is performed. In this case, a logical OR operation is performed on 1 and the area to be cleared, and a logical OR operation is performed on 0 for the portion where the circuit remains. Further, with respect to a part constituting a new circuit, a logical product operation between the data of the circuit and the target area is performed.

  Further, the logical operation used in the description of the above embodiment may be any operation as long as it is a logical operation that brings about the same result as the above embodiment. That is, the present invention is not limited to the above example as long as it is a logical operation that leaves configuration data to be left, clears configuration data to be cleared, and writes configuration data to be newly written.

  In the present invention, a program that realizes one or more functions of the above-described embodiments is supplied to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read the program. It can also be realized by processing to be executed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

501 PR1 AND configuration data, 511 PR1 OR configuration data, 521 PR2 AND configuration data, 531 PR2 OR configuration data, 541 PR1PR2 AND configuration data, 551 PR1PR2 OR configuration data

Claims (11)

An image processing apparatus having a reconfigurable circuit that can be reconfigured in a predetermined reconfiguration unit by rewriting circuit configuration data stored in a configuration memory,
Storage means for storing circuit configuration data corresponding to a circuit configured in the reconstruction area for each reconstruction area to be reconfigured;
In the case where a plurality of reconstruction areas are included in the reconstruction unit, a synthesis unit that synthesizes rewriting data including the circuit configuration data according to a circuit configured in each reconstruction area;
An image processing apparatus comprising: rewriting means for rewriting circuit configuration data of the configuration memory in the reconfiguration unit by rewriting data after combining by the combining means. The rewriting data includes clear data for selectively clearing the reconstruction area included in the reconstruction unit, and a circuit for selectively rewriting the reconstruction area included in the reconstruction unit. Configuration data,
The rewriting means selectively clears the reconstruction area included in the reconstruction unit with the clearing data, and selectively selects the reconstruction area included in the reconstruction unit with the circuit configuration data. The image processing apparatus according to claim 1, wherein the image processing apparatus is rewritten. The reconstruction unit includes the reconstruction area and a fixed area that is not a target of reconstruction,
The clearing data is data for selectively clearing the reconfiguration area by selectively applying a predetermined logical operation to the reconfiguration unit of the configuration memory and selectively leaving the fixed area. Yes,
The circuit configuration data is data for selectively rewriting the reconfiguration area and selectively leaving the fixed area by applying a predetermined logical operation to the reconfiguration unit of the configuration memory. The image processing apparatus according to claim 2.   The image processing apparatus according to claim 1, wherein the reconstruction unit corresponds to a region obtained by dividing the reconfigurable circuit into a band having a predetermined width. The reconfigurable circuit is used for job processing;
Even if a plurality of reconstruction areas are included in the reconstruction unit, the combining means does not use a circuit already configured in the plurality of reconstruction areas for one job. 5. The image processing apparatus according to claim 1, wherein the circuit configuration data is not synthesized. The clearing data is data having a value corresponding to the reconstruction area of 0 and a value corresponding to the fixed area of 1,
The circuit configuration data is data in which a value corresponding to the reconfiguration area is a value corresponding to a circuit to be configured, and a value corresponding to the fixed area is 0.
The synthesizing unit synthesizes the clearing data by an operation corresponding to a logical product of the clearing data in each of the plurality of reconstruction areas, and corresponds to a logical sum of the circuit configuration data in each of the plurality of reconstruction areas. The circuit configuration data is synthesized by the operation
The rewriting means rewrites the circuit configuration data of the reconfiguration unit of the configuration memory with a value corresponding to a logical product of the data of the reconfiguration unit and the clearing data, and then reconfigures the configuration memory. 4. The image processing apparatus according to claim 3, wherein the unit circuit configuration data is rewritten with a value corresponding to a logical sum of the reconstruction unit data and the circuit configuration data.   The image processing apparatus according to claim 1, wherein the reconfigurable circuit includes at least a part of an image processing circuit that processes image data. The image processing apparatus further includes a printer unit,
The image processing apparatus according to claim 7, wherein the printer unit outputs image data processed by the image processing circuit. The image processing apparatus further includes at least one of a scanner unit and a communication unit,
The image processing apparatus according to claim 7, wherein the image processing circuit processes image data input by the scanner unit or the communication unit.   The program for functioning a computer as an image processing apparatus as described in any one of Claims 1 thru | or 6. A method of controlling an image processing apparatus having a reconfigurable circuit that can be reconfigured in a predetermined reconfiguration unit by rewriting circuit configuration data stored in a configuration memory,
The image processing apparatus has storage means for storing circuit configuration data corresponding to a circuit configured in the reconstruction area for each reconstruction area to be reconstructed.
The control method is:
When a plurality of reconstruction areas are included in the reconstruction unit, a synthesizing step of synthesizing rewriting data including the circuit configuration data according to the circuit configured in each reconstruction area;
A control method for an image processing apparatus, comprising: a rewriting step of rewriting circuit configuration data of the configuration memory in the reconfiguration unit by rewriting data after combining in the combining step.

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