JP6401071B2 - Programmable controller - Google Patents

Description

  The present invention relates to a data memory access method in a programmable controller.

The programmable controller has a register for handling external input / output data and a register used for ladder calculation. Hereinafter, this ladder calculation register is simply referred to as an “internal register”.
Usually, the internal register is arranged in a static random access memory (static RAM, hereinafter abbreviated as “S-RAM”) that can be accessed at high speed or medium speed. The microcomputer accesses this internal register to perform ladder calculation. As a result, the processing speed of the ladder calculation is increased.

  However, since the S-RAM that can be accessed at high speed is a volatile memory, when the power of the programmable controller is turned off, the data value of the internal register becomes an indefinite value. In normal operation, after the power is turned on next time, the value of the internal register is initialized to 0 value, and the ladder calculation is started.

  On the other hand, depending on the user, there is an application where it is desired to execute a ladder operation while retaining the value when the power is turned off without initializing the value of the internal register when the power is turned on. In that case, it is configured to have an S-RAM that can be backed up by battery as hardware, and the internal register is arranged in the S-RAM that can be backed up by battery, thereby realizing retention of the data value of the internal register.

  Further, as a prior art document, Patent Document 1 (Japanese Patent No. 4143925) discloses user data by writing user data to a nonvolatile backup memory when changing user data stored in an execution memory of a programmable controller. In the memory backup method for performing backup, the storage area of the backup memory has a storage area and a write area, and when the user data stored in the execution memory is changed, the execution memory When the user data stored in the write area is written into the write area and the write process is time-sliced, a backup process is executed in the background. For saving space With switching on frequency, technology and enables the write state area used as an area for storage before switching switch in the area for writing is disclosed.

Japanese Patent No. 4143952

In the method shown in the above background art (programmable controller in which the storage memory of the internal register is arranged in an S-RAM capable of battery backup), power supply from a battery (battery) is required as the power source of the S-RAM. For this reason, when the capacity of the battery (battery) is exhausted, the data value of the internal register cannot be held and may become an indefinite value. In order to avoid this, the user must periodically replace the battery.
Also, many S-RAMs that can be backed up by battery are generally medium or low speed, which may cause a bottleneck to perform ladder calculation at high speed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable controller capable of holding a data value of an internal register used for ladder calculation even when the power is turned off while enabling high-speed ladder calculation.

  In addition, the technique disclosed in Patent Document 1 discloses that data to be backed up from a non-volatile backup memory is user data stored in an execution memory (data that is changed by downloading or online editing). Therefore, it is data corresponding to the user program), and is not a technique for backing up the data of the internal register at the time of ladder calculation, and there is no description suggesting it. The backup process uses a technique that is executed in the background by time slicing.

The present invention provides an arithmetic processing unit in which a programmable controller executes a ladder operation, a static RAM having a first internal register used when executing a ladder operation by the arithmetic processing unit, and a nonvolatile RAM having a second internal register. At least, the arithmetic processing unit executes a ladder operation and copies the data value of the first internal register to the second internal register at a scan end of the ladder operation.
The present invention

  According to the present invention, there is provided a programmable controller capable of maintaining a data value of an internal register used for ladder calculation without requiring a battery while maintaining a high ladder calculation speed.

FIG. 1 is a hardware configuration diagram around a CPU (microcomputer) of a programmable controller. FIG. 2 is a diagram illustrating an arrangement of internal registers on the memory and an access route according to the first embodiment. FIG. 3 is a diagram showing an example of a ladder diagram notation and an instruction word notation for a ladder program. FIG. 4 is a diagram illustrating a data holding area setting screen in the internal register according to the second embodiment. FIG. 5 is a diagram illustrating an access route when the access at the time of ladder calculation is executed only by the nonvolatile RAM according to the third embodiment.

Hereinafter, as embodiments of the present invention, Examples 1 to 3 will be described in order with reference to the drawings.
FIG. 1 is a hardware configuration diagram around an arithmetic processing unit (CPU unit) of a programmable controller according to each embodiment of the present invention. In FIG. 1, the arithmetic processing unit (CPU unit) is a microcomputer having a built-in flash and S-RAM memory.

  The programmable controller according to each embodiment of the present invention includes, as a hardware configuration, a microcomputer 10 that implements a ladder operation, a large-capacity nonvolatile memory 11 that stores a system program and a ladder program (a typical flash memory in FIG. 1). A high-speed S-RAM 12 for disposing a system work area and an internal register 14 used for execution of arithmetic processing by a microcomputer, and a medium-speed nonvolatile RAM 13 for disposing a mirrored internal register 15. In some cases, a high-speed DRAM is also used in order to perform arithmetic processing of the microcomputer.

  FIG. 2 is a diagram illustrating an arrangement of internal registers on the memory and an access route according to the first embodiment. The first embodiment corresponds to a case where all the internal registers are used as those requiring data value retention, and the operation function thereof will be described below. In FIG. 2, the internal register 14 arranged in the high-speed S-RAM 12 is described as “for ladder calculation”, and the internal register 15 arranged in the medium-speed nonvolatile RAM 13 is described as “for data value holding”.

  The programmable controller starts operation, and the microcomputer 10 executes ladder calculation. For example, assume that the ladder program shown in FIG. 3 is executed. At this time, since it is necessary to read and refer to the values of R0 and R1 of the internal register, the microcomputer 10 reads the data value from the storage area of R0 and R1 of the internal register 14 arranged in the high-speed S-RAM 12, Perform the operation.

As a process of writing a value to the R100 of the internal register from the result of the ladder calculation, the microcomputer 10 writes the calculation result to the storage area of R100 of the internal register 14 arranged in the high-speed S-RAM 12.
The access processing 21 at the time of ladder calculation is performed between the microcomputer 10 and the high-speed S-RAM 12, and since the access speed is high, the ladder calculation speed is also increased and the scan time of the ladder program is shortened.

Ladder calculation is executed by the above method. At the end of the scan, which is the last of the ladder calculation, the microcomputer 10 executes a transfer process 22 for copying the data value of the internal register 14 on the high-speed S-RAM 12 to the data value holding internal register 15 on the medium-speed nonvolatile RAM 13. To do.
Since the internal register 15 on the medium-speed nonvolatile RAM 13 is nonvolatile even when the power of the programmable controller is turned off, the data value is retained.

Next, an operation when the power supply of the programmable controller is turned on again from the off state will be described.
As an initial process when the power source of the programmable controller is turned on, the microcomputer 10 copies the data value of the data value holding internal register 15 on the medium speed nonvolatile RAM 13 to the internal register 15 on the high speed S-RAM 12. After the copying is completed, the microcomputer 10 starts ladder calculation.

  In the first embodiment, as described above, it is necessary to hold the data values of all the internal registers. By the way, it is not necessary for some users to hold the data values of all the internal registers. Rather, only the data values of specific internal registers are held, and other internal registers are initialized when the programmable controller is turned on. An operation may be performed. This may depend on different operation methods depending on the manufacturer of the programmable controller.

  In one case, for the internal register, there is a case in which a holding area for holding a data value and a non-holding area for which a data value is not to be held are fixed and a user cannot set. In this case, if an internal register corresponding to the non-holding area is arranged on the medium-speed nonvolatile memory 13, it is possible to hold the data value, but this is disadvantageous for speeding up the ladder calculation.

  The programmable controller according to the second embodiment makes it possible for the user to set the internal register separately into a holding area in which a data value is to be held and a non-holding area that is not to be held. An example of the setting method is shown in FIG. That is, the data value of only the holding area of the internal register set by the user is held, and the other internal register areas (non-holding areas) are initialized when the programmable controller is turned on and used for the ladder calculation.

The second embodiment corresponds to the case where only a part of the internal register area on the high-speed S-RAM 12 is used as the data holding area 41, as shown in FIG.
Similar to the first embodiment, the data value of the internal register 14 on the high-speed S-RAM 12 is used during the ladder calculation. At the end of the scan, which is the last of the ladder calculation, the microcomputer 10 outputs only the data value in the holding area for holding the data value set in FIG. 4 in the area of the internal register 14 on the high-speed S-RAM 12 to the medium speed. A transfer process for copying to the internal register 15 on the nonvolatile RAM 13 is executed. This process is different from the process according to the first embodiment.

  The feature of the second embodiment is that if the capacity allocated to the data holding area in the internal register 14 is small, the data value of the internal register 14 on the high-speed S-RAM 12 is transferred to the medium-speed nonvolatile RAM 13 at the end of the scan that is the last of the ladder operation Since the amount of data to be copied to the internal register 15 is naturally small, the copy processing time is shortened.

  The third embodiment appropriately copes with the case where the number of internal registers used in the ladder program is small and the area set in the internal register for holding data values is small. This is a method aimed at shortening.

  Here, for example, the allocation area of the internal register used in the ladder program is 1,024 bits (M0 to M3FF), and the allocation area of the internal register used to hold the data value is 32,768 bits (M0 to M7FFF). ). Further, it is assumed that the access speed of the high-speed S-RAM is 10 nS and the access speed of the medium-speed nonvolatile RAM is 55 nS.

  In the following, in order to simplify the description, only the time relating to each access to the internal register used in the ladder program and the internal register that accepts the data value copy is simply calculated.

For example, in the processing mode according to the first embodiment,
(1) The access time to the high-speed S-RAM 12 during the ladder calculation is
1,024 bits × 10 nS = 10,240 nS
(2) Copy time from the high-speed S-RAM 12 to the medium-speed non-volatile RAM 13 executed at the scan end is as follows:
32,768 bits / 16 bits × 55 nS = 112,640 nS
That is, the processing time is the total time of (1) and (2).
10,240nS + 112,640nS = 122,880nS
Will take longer to access.

As shown in FIG. 5, the third embodiment does not use the high-speed S-RAM 12 as an internal register to be accessed at the time of ladder calculation, but uses the internal register 15 on the medium-speed nonvolatile RAM 13 for ladder calculation and data value holding. This is a method of providing a processing mode for executing computation using only the processing mode and using it together with the processing mode of the first embodiment.
Therefore, in the processing mode shown in FIG. 5, a transfer process for copying the data value of the internal register 14 on the high-speed S-RAM 12 to the internal register 15 on the medium-speed nonvolatile RAM 13 is necessary at the end of the scan of the ladder operation. Will not be executed.

In the processing mode shown in FIG.
(3) The access time to the medium-speed nonvolatile RAM 13 during the ladder calculation is
1,024 bits × 55nS = 56,320nS
(4) Since the copy time from the high-speed S-RAM 12 to the medium-speed nonvolatile RAM 13 executed at the end of the scan does not perform the copy process,
0nS
That is, the processing time is the total time of (3) and (4).
56,320 nS + 0 nS = 56,320 nS
Will take longer to access.

  As described above, depending on the specifications of the memory to be used (that is, the high-speed S-RAM and the medium-speed non-volatile RAM), the number of internal registers used in the ladder program, and the capacity of the internal registers used for holding the data value The method shown in FIG. 5 can be effective because the access time can be shortened compared to the first embodiment.

  In short, in the third embodiment, the specifications of the memory to be used (that is, the high-speed S-RAM and the medium-speed nonvolatile RAM), the number of internal registers used in the ladder program, and the internal register used for holding the data value are described. In this method, the processing time in the processing mode according to the first embodiment is compared with the processing time in the processing mode shown in FIG. 5 based on the capacity, and the processing with the shorter processing time is selected. This selection can be performed automatically by an arithmetic processing unit (CPU unit) or manually by user judgment.

  In the above, the third embodiment has been described as a method in which the first embodiment and the processing mode shown in FIG. 5 are used together. However, it is needless to say that a method in which the second embodiment and the processing mode shown in FIG. is there.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. In addition, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  A hard disk, USB memory, SSD (Solid State Drive) or the like may be used as a memory for realizing the functions of the above embodiments. Further, as the arithmetic processing unit (CPU unit), an FPGA may be used instead of the microcomputer.

10 microcomputer, 11 large capacity non-volatile (flash) memory, 12 high-speed S-RAM, 13 medium-speed non-volatile RAM, 14 internal register (for ladder calculation), 15 internal register (for data value holding or ladder calculation and data value holding) for)

Claims (3)

An arithmetic processing unit that executes ladder arithmetic;
A first internal register located in the static RAM;
At least a second internal register disposed in the non-volatile RAM ;
The process of the arithmetic processing unit to copy the data value of said first internal register when the scan end executed the ladder calculation ladder operation on said second internal register to the first processing mode,
The processing unit executes a ladder operation using only the second internal register as a second processing mode,
Based on the specifications of the static RAM and the nonvolatile RAM, the number of the first internal registers, and the capacity of the second internal registers, the processing time according to the first processing mode and the second processing mode A programmable controller, characterized by comparing a processing time and selecting a processing mode with a short processing time . The programmable controller according to claim 1,
The first internal register is divided into a holding area that requires holding a data value and a non-holding area that does not need to be set,
The programmable controller according to claim 1, wherein the data value copied to the second internal register in the first processing mode is only the data value of the holding area of the first internal register . The programmable controller according to claim 1 or 2,
The programmable controller according to claim 1, wherein the selection of the first or second processing mode is automatically performed by the arithmetic processing unit or manually by a user's judgment .