JP2011081641A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller capable of resolving shortening of a memory life and a delay of a storing operation. <P>SOLUTION: The memory controller includes a nonvolatile memory wherein a plurality of logical pages to which a plurality of tables as storage areas divided for every predetermined capacity belong are formed respectively, a control unit for recording and reproducing data in units of logical pages for each of the logical pages in the nonvolatile memory, and a volatile memory for temporarily storing the data in the nonvolatile memory. The control unit includes a deferred update unit for reading the data stored in the logical page onto the volatile memory to update data in the table belonging to the logical page on the volatile memory at the time of updating data stored in the logical page, and writing the logical page on the volatile memory to which the updated table belongs onto the nonvolatile memory with an elapse of a predetermined time after one of the tables belonging to the logical page is initially updated. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a memory control device, and more particularly to a memory control device that executes data writing to a memory in a predetermined storage capacity unit.

  As a storage device used for information processing devices, NOR-type flash memory is sometimes used for storing programs that require random access and system setting data. Increasingly, NAND flash memory with a low bit unit price is used. However, the NAND flash memory can only be written in units of a plurality of bits (page units) called a page, and has a limited number of rewrites (erase). For this reason, a block that has reached the rewrite limit becomes a bad block and cannot be used, resulting in a problem that usable blocks are reduced.

  Here, in the example shown in FIG. 1, when handling nonvolatile data such as system settings, every time T 1, T + t 0, T + T 1 elapses on the RAM 105, a logical page (Page A) is included. The case where the data in each data table to which it belongs is updated is shown. In such a case, as each table in Page A is updated (see reference numerals 151, 152, and 153), rewriting to the NAND flash memory 104 is executed as indicated by the arrows (reference numerals 141 and 142). , 143). Then, the number of times of rewriting increases with respect to the NAND flash memory 104, resulting in a problem that the chip life is shortened.

  On the other hand, Patent Document 1 discloses a technique for reducing the number of times of writing to a memory. In the technique disclosed in Patent Document 1, first, data to be written in a predetermined block of the nonvolatile memory is written in the volatile memory together with identification information indicating the block. Then, using the identification information written in the volatile memory, the data written in the same block is identified from the data written in the volatile memory, and the identified data is collectively stored in the block to be written. And writing the data.

JP 2007-34431 A

  However, in the technique disclosed in Patent Document 1 described above, data written in a specific block is specified, and the specified data is written in a lump. Therefore, it takes time to specify the data, and the storage operation is performed. The problem arises that is delayed. In addition, when a write instruction event occurs as a write timing to the nonvolatile memory, for example, an instruction to start a power saving mode or a power-off of a host device is given. If it is opened, the capacity of the volatile memory becomes full, causing a problem that a delay occurs in the storage operation.

  Therefore, an object of the present invention is to solve the above-mentioned problems “shortening of memory life” and “delay of storage operation”.

In order to achieve this object, a memory control device according to one aspect of the present invention is provided.
A nonvolatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the logical page in the nonvolatile memory. And a volatile memory that temporarily stores data in the nonvolatile memory.
Then, when the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory and belongs to the logical page on the volatile memory. The data in the table is updated and the volatile memory on the volatile memory to which the updated table belongs after a predetermined time elapses after any of the tables belonging to the logical page is updated for the first time. A delay update unit for writing a logical page to the nonvolatile memory;
The configuration is as follows.

Moreover, the program which is the other form of this invention is:
A nonvolatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the logical page in the nonvolatile memory. In the control unit of the information processing apparatus including the control unit to perform and the volatile memory that temporarily stores the data in the nonvolatile memory,
When updating the data stored in the logical page, the data stored in the logical page is read onto the volatile memory, and the data in the table belonging to the logical page is updated on the volatile memory. In addition, the logical page on the volatile memory to which the updated table belongs after the preset time has elapsed since any one of the tables belonging to the logical page is first updated is the nonvolatile memory. A delayed updater that writes to
It is a program for realizing.

In addition, a memory control method according to another aspect of the present invention includes:
A nonvolatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the logical page in the nonvolatile memory. In an information processing apparatus comprising a control unit that performs and a volatile memory that temporarily stores data in the nonvolatile memory,
When the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory, and the table belonging to the logical page on the volatile memory. The logical page on the volatile memory to which the updated table belongs after a preset time has elapsed since any of the tables belonging to the logical page is updated for the first time. To the non-volatile memory,
The configuration is as follows.

  With the configuration as described above, the present invention can extend the memory life while suppressing the delay of the storage operation.

It is a figure which shows the data update operation | movement relevant to this invention. It is a figure which shows the data update operation | movement in this invention. 1 is a diagram illustrating a configuration of a memory control device in Embodiment 1. FIG. 4 is a flowchart illustrating an operation of the memory control device disclosed in FIG. 3. It is a figure which shows the structure of the memory control apparatus in Embodiment 2. 6 is a flowchart illustrating an operation of the memory control device disclosed in FIG. 5. 6 is a flowchart illustrating an operation of the memory control device disclosed in FIG. 5. It is a figure which shows the structure of the memory control apparatus in Embodiment 2.

<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing a data update operation in the present invention. FIG. 3 is a diagram illustrating a configuration of the memory control device according to the present embodiment. FIG. 4 is a flowchart showing the operation of the memory control device disclosed in FIG.

[Constitution]
FIG. 3 is a block diagram illustrating a configuration of a memory control device that constitutes a part of the information processing apparatus according to the present embodiment. As shown in this figure, the memory control device includes a CPU (Central Processing Unit) 1 that is an arithmetic device that controls the entire device, a NAND flash memory 4 and a RAM (Random Access Memory) 5 that are storage devices, and the NAND. And a memory control unit 3 for writing, reading, and erasing data in response to a command from the CPU 1 with respect to the flash memory 4.

  Specifically, the NAND flash memory 4 is a nonvolatile memory in which nonvolatile data such as program data, user data, and setting values other than the program code are stored. The NAND flash memory 4 is managed by being divided into data tables that are storage areas for each predetermined capacity (every arbitrary number of bytes), and a plurality of logical pages to which a plurality of the data tables belong are formed. For example, as shown in FIG. 2, in the NAND flash memory 4, a logical page “Page A” to which tables “Table 0” to “Table Y” as a plurality of storage areas belong is formed, although not shown. A plurality of such logical pages are formed. Data is written to the NAND flash memory 4 in units of logical pages.

  The RAM 5 is a temporary memory for performing predetermined data processing, that is, work, and is a volatile memory. In this embodiment, as will be described later, the nonvolatile data recorded in the NAND flash memory 4 is expanded on the RAM 5, and data update or the like is temporarily executed on the RAM 5. Then, after the nonvolatile data is updated on the RAM 5, the updated nonvolatile data is reflected in the NAND flash memory 4.

  The RAM 5 has a page update management table and a data storage area table for managing the state of the NAND flash memory 4. The page update management table (not shown) has a flag that is set (set) when any data table in the logical page managed on the RAM 5 is updated. In addition, a data storage area table (not shown) stores information indicating which physical page in which block each latest logical page is stored.

  The page update management table and the data storage area table are normally recorded in the NAND flash memory 4. However, processing such as writing to the data stored in the NAND flash memory 4 such as activation of the memory control device is performed. When it is executed, it is automatically read into the RAM 5. Then, the page update management table and the data storage area table developed on the RAM 5 are updated each time writing to the NAND flash memory 4 is performed.

  The CPU 1 includes a delay update unit 2 constructed by incorporating a program stored in advance in the NAND flash memory 4 or the like. First, the delay update unit 2 reads the data stored in the logical page onto the RAM 5 when updating the data stored in the logical page in the NAND flash memory 4. Then, the data in the data table belonging to the logical page is updated on the RAM 5. At this time, in particular, the logical page of the RAM 5 to which the updated data table belongs after the elapse of a preset time (for example, Z seconds) after any data table in the logical page is updated for the first time, Write to the NAND flash memory 4 at once. The specific function of the delay update unit 2 will be described in detail in the following operation description.

  As described above, the “preset time (Z seconds)” for determining the write timing of the logical page from the RAM 5 to the NAND flash memory 4 may be set to a predetermined value in advance. It can be changed to an arbitrary value by being changed by an operator who operates the information processing apparatus in which the control device is incorporated.

[Operation]
Next, the operation of the memory control device will be described with reference to the flowchart of FIG. 4 and FIG. Here, the non-volatile data stored in the NAND flash memory 4 is managed by being divided into X byte tables in each logical page. In this embodiment, the setting value of the write timer is set to Z seconds (arbitrary), and each table Table0, TableY, Data is updated in the order of Table1.

  First, the CPU 1 reads the logical page “Page A” from the NAND flash memory 4 onto the RAM 5 (step S1). At this time, the page update management table and the data storage area table relating to the logical page “Page A” are read from the NAND flash memory 4 onto the RAM 5.

  Then, when the data of the logical page “Page A” is updated, the CPU 1 first updates the “Page A” on the RAM 5. That is, the data table “Table 0” belonging to the logical page “Page A” expanded on the RAM 5 is updated on the RAM 5 (see step S2, reference numeral 51 in FIG. 2). At this time, the update flag of the page update management data table of “Page A” to which the data table “Table 0” updated on the RAM 5 belongs is set to “ON” (step S3), and “Page A” is updated. Remember that there is.

  At the same time, when the timer set for the logical page “Page A” is not operating, that is, when the data table belonging to the logical page “Page A” is updated for the first time, the logical page “ Counting by the timer set corresponding to “Page A”, that is, time measurement is started (step S4). The timer is set for each logical page, and starts counting (time measurement) when a data table belonging to each logical page is updated on the RAM 5 for the first time.

  Subsequently, as described above, it is assumed that the data tables “Table Y” and “Table 1” belonging to the logical page “Page A” are updated while the timer corresponding to the logical page “Page A” is operating (step S5). Yes). If the timer set corresponding to the logical page “Page A” is operating, the data tables “Table Y” and “Table 1” are updated on the RAM 5 (step S6). In other words, after the data table “Table 0” is first updated in the logical page “Page A” on the RAM 5 (see reference numeral 51 in FIG. 2), there is another time until Z seconds, which is a preset time, elapses. When the data table is updated, the data tables “Table Y” and “Table 1” are continuously updated on the RAM 5 (see reference numerals 52 and 53 in FIG. 2). At this time, in the logical page where the data table has been updated, whether or not counting by the timer has already been started may be determined by examining the operation of the timer corresponding to the logical page. The determination may be made by confirming that the update flag corresponding to the logical page is set.

  Thereafter, when Z seconds elapse in the timer (Yes in step S7), page data write processing for reflecting the update data on the RAM 5 to the NAND flash memory 4 is performed (step S8). At this time, the page data writing process confirms the update flag of the logical page whose timer has passed Z seconds, and if there is an update, the logical page “Page A” on the RAM 5 belongs to the logical page “Page A”. All the data tables that are currently stored are written in a new physical page in the NAND flash memory 4. Then, the physical page in which the old data is written is invalidated, and the data storage area table is updated so that the new physical page is valid.

  In this embodiment, since logical page A is updated, a new page A is written to an unused physical page in the NAND flash memory 4, a physical page with an old page A is invalidated, and a newly written physical page is written. Update the data storage area table so that is valid. When the writing to the NAND flash memory 4 is completed, the update flag of the page update management data table is set to OFF (released) (step S9).

  As described above, according to the memory control device of the present invention, in the case of a plurality of related data tables that are continuously updated in a short time, there is a high possibility that they are arranged in the same logical page. Multiple tables can be updated with a single write to the NAND flash memory. Therefore, as compared with the method of writing a logical page for each table update disclosed in FIG. 1, the number of times of writing to the NAND flash memory can be reduced, and shortening of the memory life can be suppressed and the life can be extended. Further, by adopting a configuration in which the delay time of the delayed update is arbitrarily set, the delay time can be properly used according to the system state and the data to be handled, and the reduction in the number of writing can be optimized.

<Embodiment 2>
A second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a diagram illustrating a configuration of the memory control device according to the present embodiment. 6 to 7 are flowcharts showing the operation of the memory control device.

[Constitution]
The memory control device according to the present embodiment has substantially the same configuration as that of the first embodiment described above. In addition to this, the present embodiment includes an immediate update unit 6 constructed by incorporating a program into the CPU 1. The immediate update unit 6 operates to immediately reflect the logical data of the NAND flash memory 4 developed on the RAM 5 in the NAND flash memory 4 when the logical data is updated on the RAM 5.

  The immediate update unit 6 operates when the content of the update mode data that designates the update timing of data set in advance for the memory control device is “immediate update mode”. Further, when the content of the update mode data is “delay update mode”, the delay update unit 2 described above operates. Here, the update mode data for designating the data update timing is stored in the NAND flash memory 4 functioning as the update mode storage means, and is read out together with the logical page to the RAM 5. Then, the CPU 1 determines an update mode for designating the write timing to the NAND flash memory 4 for the logical page read to the RAM 5 according to the read update mode data. That is, when the update mode data is “delayed update mode”, the delay update unit 2 is activated and the logical page is stored in the NAND flash memory 4 after a predetermined time has elapsed on the RAM 5, or the update mode When the data is in the “immediate update mode”, when the immediate update unit 6 operates and is updated on the RAM 5, it is immediately reflected in the NAND flash memory 4.

  The setting of the update mode based on the update mode data (whether the delayed update unit 2 operates or the immediate update unit 6 operates) is valid for all data stored in the NAND flash memory 4. Alternatively, it may be set for each logical page and valid for each logical page. For example, the delay update unit 2 operates for the logical page “Page A” and the immediate update unit 6 operates for the other logical pages. The update mode data can be changed and set by the operator.

[Operation]
Next, the operation of the above-described memory control device will be described with reference to FIGS. First, as described above, the logical page “Page A” is read from the NAND flash memory 4 onto the RAM 5 (step S11). At this time, the page update management table and data storage area table regarding the logical page “Page A” and the update mode data are read from the NAND flash memory 4 onto the RAM 5.

  When the data of the logical page “Page A” is updated, the “Page A” is updated on the RAM 5. For example, as indicated by reference numeral 51 in FIG. 2, the data table “Table 0” belonging to the logical page “Page A” expanded on the RAM 5 is updated on the RAM 5 (step S12).

  At this time, the setting of the update mode data is checked, and if the logical page to which the updated data table belongs is set to perform immediate update, or the update setting itself is set to perform immediate update in the entire system. If it is (Yes in Step S13), if the update flag of the page update management data table is set to “ON” (Yes in Step S14), it is set to “OFF” (Step S15). If the delay update is already in progress, the process waits until the delay update is completed (Yes in step S16).

  If the delayed update is not being performed or if the delayed update is completed (No in step S16), the immediate updating flag is set to “ON” (step S17). Thereafter, the logical page “Page A” to which the data table updated on the RAM 5 belongs is written into the NAND flash memory 5 from the RAM 5 (step S18), and the immediate updating flag is set to “OFF” (step S18). S19). As described above, in the case of immediate update, when logical data is updated on the RAM 5, the logical data is immediately reflected on the NAND flash memory 5.

  On the other hand, if the update mode data is set so that the logical page to which the updated data table belongs is set to perform delayed update, or the system update setting itself is set to perform delayed update (step First, the update flag of the page update management data table is set to “ON” (step S20). After that, the operation is almost the same as that in the first embodiment described above.

  Specifically, the update flag of the page update management data table of “Page A” to which the data table “Table 0” updated on the RAM 5 belongs is set to “ON” (step S20), and “Page A” is updated. Remember that it was done. At the same time, if the timer set for the logical page “Page A” is not running, that is, if any of the data tables belonging to the logical page “Page A” is updated for the first time, the logical page Counting by the timer set corresponding to “Page A”, that is, time measurement is started (step S21).

  At this time, if immediate update is in progress, the process waits until the immediate update ends (Yes in step S22). If immediate update is not in progress or if immediate update ends (No in step S22), the delayed update flag is set to “ON”. "(Step S23).

  As described above, when the timer corresponding to the logical page “Page A” is operating and the delayed update flag is “ON”, the data table “Table Y” belonging to the logical page “Page A” , "Table 1" is updated (Yes in step S24). Then, when the timer set corresponding to the logical page “Page A” is operating, the data tables “Table Y” and “Table 1” are updated on the RAM 5 (step S25). In other words, after the data table “Table 0” is first updated in the logical page “Page A” on the RAM 5 (see reference numeral 51 in FIG. 2), there is another time until Z seconds, which is a preset time, elapses. When the data table is updated, the data tables “Table Y” and “Table 1” are continuously updated on the RAM 5 (see reference numerals 52 and 53 in FIG. 2).

  Thereafter, when Z seconds elapse in the timer (Yes in step S26), page data write processing for reflecting the update data on the RAM 5 to the NAND flash memory 4 is performed (step S27). At this time, the page data writing process confirms the update flag of the logical page whose timer has passed Z seconds, and if there is an update, the logical page “Page A” on the RAM 5 is replaced with a new physical page in the NAND flash memory 4. Write to. Then, the data storage area table is updated so that the physical page in which the old data is written is invalidated and the new physical page is validated. When the writing to the NAND flash memory 4 is completed, the update flag of the page update management data table is set to “OFF” (step S28), and the delayed update flag is also set to “OFF” (step S29).

  As described above, according to the memory control device of this embodiment, the immediate update mode and the delayed update mode can be used properly, and the reduction in the number of times of writing to the memory can be optimized according to the system state and the data handled. . As a result, the memory life can be extended. Further, as described above, by providing the immediate update in-progress flag and the delayed update in-progress flag, it is possible to avoid contention between immediate update and delayed update processing.

<Embodiment 3>
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a functional block diagram showing the configuration of the memory control device according to this embodiment. In the present embodiment, an outline of the configuration of the memory control device will be described.

As shown in FIG. 8, the memory control device in this embodiment is
A nonvolatile memory 13 in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction in units of the logical pages with respect to the logical pages in the nonvolatile memory And a volatile memory 14 that temporarily stores data in the nonvolatile memory.
Then, when updating the data stored in the logical page, the control unit 11 reads the data stored in the logical page onto the volatile memory, and stores the data on the logical page on the volatile memory. Update the data in the table to which the table belongs, and after the preset time has elapsed since any of the tables belonging to the logical page is updated for the first time on the volatile memory to which the updated table belongs A delay update unit 12 for writing the logical page to the nonvolatile memory;
The structure is taken.

In the memory control device,
The delayed update unit updates data in the table belonging to the logical page for a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. On the volatile memory,
The configuration is as follows.

In the memory control device,
The delayed update unit counts a timer set corresponding to the logical page to which the updated table belongs when any of the tables belonging to the logical page is first updated on the volatile memory. And when the timer count reaches a preset value, the logical page on the volatile memory is written to the nonvolatile memory.
The configuration is as follows.

In the memory control device,
The delayed update unit sets a flag provided corresponding to the logical page to which the updated table belongs when any of the tables belonging to the logical page is first updated on the volatile memory. And start counting the timer set corresponding to the logical page, and after the logical page on the volatile memory is written to the non-volatile memory, cancel the setting of the flag.
The configuration is as follows.

In the memory control device,
The control unit reads the data stored in the logical page onto the volatile memory and updates the table belonging to the logical page on the volatile memory when updating the data stored in the logical page. An immediate update unit that writes the logical page on the volatile memory to which the updated table belongs to the nonvolatile memory when the data in the table is updated;
Update mode storage means for storing an update mode for designating update timing of data for the nonvolatile memory;
One of the delayed update unit and the immediate update unit operates according to the designated update mode stored in the update mode storage unit.
The configuration is as follows.

In the memory control device,
The update mode storage means stores the update mode for designating data update timing for each logical page,
The delayed update unit and the immediate update unit operate either when storing data for each logical page according to the update mode stored for each logical page stored in the update mode storage unit.
The configuration is as follows.

Further, the above-described memory control device can be realized by incorporating a program in the control unit of the information processing device.
Specifically, the program which is another embodiment of the present invention is:
A nonvolatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the logical page in the nonvolatile memory. In the control unit of the information processing apparatus including the control unit to perform and the volatile memory that temporarily stores the data in the nonvolatile memory,
When updating the data stored in the logical page, the data stored in the logical page is read onto the volatile memory, and the data in the table belonging to the logical page is updated on the volatile memory. In addition, the logical page on the volatile memory to which the updated table belongs after the preset time has elapsed since any one of the tables belonging to the logical page is first updated is the nonvolatile memory. A delayed updater that writes to
It is a program for realizing.

And in the above program,
The delayed update unit updates data in the table belonging to the logical page for a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. On the volatile memory,
The configuration is as follows.

In addition, a memory control method according to another embodiment of the present invention, which is executed when the memory control device described above operates,
A nonvolatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the logical page in the nonvolatile memory. In an information processing apparatus comprising a control unit that performs and a volatile memory that temporarily stores data in the nonvolatile memory,
When the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory, and the table belonging to the logical page on the volatile memory. The logical page on the volatile memory to which the updated table belongs after a preset time has elapsed since any of the tables belonging to the logical page is updated for the first time. To the non-volatile memory,
The configuration is as follows.

In the memory control method,
At the time of updating the data stored in the logical page, the table belonging to the logical page is set within a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. Update the data in the table on the volatile memory,
The configuration is as follows.

  Even the invention of the program or the memory control method having the above-described configuration can achieve the above-described object of the present invention because it has the same operation as the above-described memory control device.

  INDUSTRIAL APPLICABILITY The present invention can be used as a memory control device that performs write control on a NAND flash memory equipped in an information processing device, and has industrial applicability.

1 CPU
2 Delay update unit 3 Memory control unit 4 NAND flash memory 5 RAM
6 Instant Update Unit 11 Control Unit 12 Delay Update Unit 13 Nonvolatile Memory 14 Volatile Memory

Claims (10)

A non-volatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the non-volatile memory in the logical page unit. A control unit for performing, and a volatile memory for temporarily storing data in the nonvolatile memory,
When the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory, and the table belonging to the logical page on the volatile memory. The logical page on the volatile memory to which the updated table belongs after a preset time has elapsed since any of the tables belonging to the logical page is updated for the first time. Including a delay update unit for writing to the nonvolatile memory,
Memory controller. The memory control device according to claim 1,
The delayed update unit updates data in the table belonging to the logical page for a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. On the volatile memory,
Memory controller. The memory control device according to claim 1 or 2,
The delay update unit counts a timer set corresponding to the logical page to which the updated table belongs when any of the tables belonging to the logical page is first updated on the volatile memory. And when the timer count reaches a preset value, write the logical page on the volatile memory to the nonvolatile memory.
Memory controller. The memory control device according to claim 3,
The delayed update unit sets a flag provided corresponding to the logical page to which the updated table belongs when any of the tables belonging to the logical page is first updated on the volatile memory. And start counting the timer set corresponding to the logical page, and cancel the setting of the flag after writing the logical page on the volatile memory to the nonvolatile memory.
Memory controller. The memory control device according to any one of claims 1 to 4,
When the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory, and the table belonging to the logical page on the volatile memory. An update unit that writes the logical page in the volatile memory to which the updated table belongs to the nonvolatile memory when the data in the table is updated;
Update mode storage means for storing an update mode for designating update timing of data in the nonvolatile memory;
One of the delayed update unit and the immediate update unit operates according to the designated update mode stored in the update mode storage unit,
Memory controller. The memory control device according to claim 5,
The update mode storage means stores the update mode for designating data update timing for each logical page,
The delayed update unit and the immediate update unit operate either when storing data for each logical page, according to the update mode stored for each logical page stored in the update mode storage unit.
Memory controller. A non-volatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction for each logical page in the non-volatile memory in the logical page unit. In the control unit of the information processing apparatus comprising: a control unit that performs; and a volatile memory that temporarily stores data in the nonvolatile memory;
When updating the data stored in the logical page, the data stored in the logical page is read onto the volatile memory, and the data in the table belonging to the logical page is updated on the volatile memory. And the non-volatile memory stores the logical page on the volatile memory to which the updated table belongs after a preset time has elapsed since any one of the tables belonging to the logical page is first updated. A delayed updater that writes to
A program to realize The program according to claim 7,
The delayed update unit updates data in the table belonging to the logical page for a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. On the volatile memory,
program. A non-volatile memory in which a plurality of logical pages to which a plurality of tables as storage areas divided by a predetermined capacity belong is formed, and data recording / reproduction is performed in units of the logical pages with respect to the logical pages in the non-volatile memory. In an information processing apparatus comprising a control unit that performs, and a volatile memory that temporarily stores data in the nonvolatile memory,
When the data stored in the logical page is updated, the control unit reads the data stored in the logical page onto the volatile memory, and the table belonging to the logical page on the volatile memory. The logical page on the volatile memory to which the updated table belongs after a preset time has elapsed since any of the tables belonging to the logical page is updated for the first time. To the non-volatile memory,
Memory control method. The memory control method according to claim 1, comprising:
When updating the data stored in the logical page, the table belonging to the logical page is set within a preset time after any of the tables belonging to the logical page is first updated on the volatile memory. Updating the data in the table on the volatile memory;
Memory control method.

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