JP2017059009A - Control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control device capable of obtaining expected performance in a fixed cycle application which operates in a predetermined cycle without deteriorating reading performance even when there is no read data on a cache.SOLUTION: A control device comprises: a volatile memory 60 which stores a holding variable; a nonvolatile memory 20 which copies and stores the holding variable stored in the volatile memory; volatile memory data update control means 50 for performing control to initialize the holding variable stored in the volatile memory when a power supply is turned on; fixed cycle operation control means 10 for controlling the operation of the whole device in a predetermined cycle and reading the holding variable from the volatile memory or writing it into the volatile memory in the predetermined cycle; and nonvolatile memory data update control means l70 for performing control to copy and store the holding variable lastly updated and stored in the volatile memory by the fixed cycle operation control means, in the nonvolatile memory.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a control device, and more particularly to speeding up access to retained data.

  In general, a control device used in a control system often operates a fixed-cycle application that operates at a predetermined cycle.

  FIG. 6 is a configuration block diagram showing an example of a control device conventionally used in a control system. In FIG. 6, a fixed cycle operation control unit 10 controls the operation of the entire apparatus at a predetermined drive cycle (for example, 100 ms). The nonvolatile memory 20 functions as a holding variable storage unit, and writing / reading of holding variables is performed based on a predetermined driving cycle of the fixed cycle operation control unit 10.

  Here, paying attention to the access speed of the nonvolatile memory 20, it is slower than the volatile memory. The access speed of the non-volatile memory 20 slower than the volatile memory becomes a bottleneck when determining the drive period of the fixed-cycle operation control unit 10.

  In order to eliminate such a bottleneck, a non-volatile cache memory 30 is also provided between the fixed-cycle operation control unit 10 and the non-volatile memory 20 as shown in FIG.

  By providing the non-volatile cache memory 30 between the fixed cycle operation control unit 10 and the non-volatile memory 20, the access speed of the non-volatile memory 20 can be increased.

  However, when the non-volatile cache memory 30 is used, a cache miss hit may occasionally occur. When a cache miss hit occurs, the data processing function deteriorates.

  In addition, since the fixed cycle operation control unit 10 is required to operate based on a certain predetermined drive cycle, the fixed cycle operation control unit 10 has a predetermined operation on the premise that the data processing function is reduced due to the occurrence of a cache miss. The driving cycle must be set.

  As a result, although the cache memory 30 is used to increase the access speed of the nonvolatile memory 20, the access speed of the nonvolatile memory 20 that should be originally obtained by using the cache memory 30 is reduced. There is also a problem that the speed-up effect cannot be obtained sufficiently.

  Japanese Patent Application Laid-Open No. 2004-151561 describes a technique that allows a specific process of a control program to be moved at high speed regardless of the usage rate and appearance frequency.

  Patent Document 2 describes a technique for realizing stable control cycle control by loading and locking a user application in a cache memory.

  Non-Patent Document 1 describes problems and solutions related to writing data to the cache memory.

JP 2013-73344 A JP 2011-253267 A

Mynavi News [Column] “Computer Architecture Story 142 Write-Through and Write-Back” Hisa Ando [December 15, 2008] [Search August 21, 2015] Internet <URL: http://news.mynavi.jp / column / architecture / 142 / ＞

  As described in Non-Patent Document 1, when data is written to the cache, the data on the cache line is different from the data on the main memory at the written address. Otherwise, you will not know which data is correct.

  As a solution to this problem, there is a write-through method in which the same data is written to the main memory simultaneously with writing to the cache.

  In the write-through method, when writing to the cache, it is only necessary to control so that a write request is simultaneously issued to the main memory, and the control can be performed relatively easily.

  In the write-through method, since writing to the main memory occurs every time a store instruction is executed, the performance is limited by the writing time to the main memory.

  Taking advantage of this simple control, many processors use the write-through method for the primary data cache and the write-back method described below for the secondary cache.

  The write-back method is one of the methods for reducing the frequency of writing to the lower level cache such as the main memory and the secondary cache. The writing is performed only on the cache line, and when the eviction becomes necessary, the cache line Is written back to the main memory. In the case of the write back method, the contents are not reflected in the main memory at the time of writing.

  Focusing on the writing to the cache line until the eviction occurs in the write-back method, it is reflected in the main memory in a single write. Compared with the write-through method, the number of times of writing to the main memory is reduced, so that the writing performance of the main memory is not limited and the performance is easily improved.

  However, in these write-through method and write-back method, read data is not always on the cache. If the read data is not in the cache, the read performance deteriorates, and it is difficult to guarantee a constant performance in a fixed cycle application that operates at a predetermined cycle.

  The present invention solves such a problem, and its purpose is not to deteriorate the read performance even if there is no read data on the cache, and is intended for a fixed-cycle application that operates at a predetermined cycle. The purpose is to realize a control device capable of obtaining performance.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
Volatile memory for storing retention variables;
A non-volatile memory for copying and storing a holding variable stored in the volatile memory;
Volatile memory data update control means for controlling to initialize a holding variable stored in the volatile memory when the power is turned on;
A periodic operation control means for controlling the entire apparatus to operate at a predetermined cycle, and reading / writing the retained variable to / from the volatile memory at a predetermined cycle;
Non-volatile memory data update control means for controlling to copy and store the storage variable last updated and stored in the volatile memory by the fixed cycle operation control means;
It is comprised by these.

The invention according to claim 2 is the control apparatus according to claim 1,
The fixed cycle operation control means includes a function of the nonvolatile memory data update control means.

The invention described in claim 3
Volatile memory for storing retention variables;
A non-volatile memory for copying and storing a holding variable stored in the volatile memory;
Volatile memory data update control means for controlling to initialize a holding variable stored in the volatile memory when the power is turned on;
A periodic operation control means for controlling the entire apparatus to operate at a predetermined cycle, and reading / writing the retained variable to / from the volatile memory at a predetermined cycle;
Non-volatile memory data update control means for controlling to store the storage variable last updated and stored in the volatile memory by the fixed cycle operation control means, and to store it in the non-volatile memory;
Volatile memory data monitoring means for monitoring a holding variable that is sequentially written and stored in the volatile memory by the fixed cycle operation control means, and outputting a holding variable updated at the end of the fixed cycle processing to the nonvolatile memory,
It is comprised by these.

According to a fourth aspect of the present invention, in the control device according to the third aspect,
The fixed cycle operation control means includes a function of the nonvolatile memory data update control means.

A fifth aspect of the present invention provides the control device according to any one of the first to fourth aspects,
The fixed period operation control means operates a fixed period application that operates at a predetermined period.

  According to such a configuration, a constant read performance can be obtained even when there is no read data on the cache, and the write operation is executed only at a predetermined cycle, so that the write load can be reduced.

  And even if the device is inferior to the read performance, the expected performance can be achieved in a fixed-cycle application that operates at a predetermined cycle by enabling high-speed read processing and the minimum necessary write processing. The resulting control device can be realized.

It is a block diagram showing a specific example of a control device based on the present invention. It is a flowchart explaining the flow of operation | movement of FIG. FIG. 3 is an operation explanatory diagram of a data update check in the flowchart of FIG. 2. It is a block diagram which shows the other Example of this invention. 5 is a flowchart for explaining the flow of operations in FIG. 4. It is a block diagram which shows an example of the control apparatus conventionally used with the control system. It is a block diagram which shows the other example of the control apparatus conventionally used with the control system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a specific example of a control device according to the present invention. Components common to those in FIGS. 6 and 7 are given the same reference numerals.

  In FIG. 1, a power supply unit 40 supplies predetermined drive power to each unit of the control device.

  When the data initial unit 50 detects that the power unit 40 is turned on, the data initial unit 50 initializes the data stored in the volatile memory 60.

  The volatile memory 60 is constituted by, for example, a DRAM, and is controlled based on the fixed-cycle operation control unit 10 after the data is initialized by the data initial unit 50, and in a predetermined drive cycle (for example, 100 ms). A holding variable to be read / written from / to the nonvolatile memory 20 is temporarily held.

  The non-volatile memory data update control unit 70 monitors changes / differences of holding variables that are sequentially updated by the periodic operation control unit 10 and stored in the volatile memory 60, and is updated and stored in the volatile memory 60 at the end. When the stored variable is confirmed, the stored variable is written and updated in the nonvolatile memory 20.

  FIG. 2 is a flowchart for explaining the flow of operation of the control device configured as shown in FIG. In FIG. 2, when the power source 40 is turned on (step S1), the data stored in the volatile memory 60 is initialized by the data initial unit 50 (step S2).

  After the power is turned on, it is controlled to operate at a predetermined cycle based on the fixed cycle operation control unit 10 as described above (step S3), and the volatile memory 60 is operated in a predetermined cycle by the fixed cycle operation control unit 10. The base data is sequentially updated and stored (step S4).

  The nonvolatile memory data update control unit 70 monitors a holding variable transferred from the fixed cycle operation control unit 10 to the nonvolatile memory 20 via the volatile memory 60. When it is confirmed that the data output from the fixed cycle operation control unit 10 is a holding variable updated from the previous cycle, the updated holding variable is output to the nonvolatile memory 20 (step S5). After the data in the memory 20 is updated (step S6) and the data in the nonvolatile memory 20 is updated, the monitoring operation after step S3 is repeatedly executed. When it is confirmed in step S5 that there is no data updated from the previous cycle, the monitoring operation after step S3 is repeatedly executed.

  FIG. 3 is an operation explanatory diagram of the data update check of “Is there data updated from the previous cycle?” In step S5 of FIG. (A) shows the holding variables V1 to V9 stored in the table 1 after executing the predetermined process in the previous cycle, and (b) is stored in the table 2 after executing the predetermined process in the current cycle. The holding variables V1 to V9 are shown.

  The nonvolatile memory data update control unit 70 compares the table 1 and the table 2 after the predetermined processing is executed by the fixed cycle operation control unit 10 in the current cycle, and extracts the updated holding variable. In the example of FIG. 3, V1, V6, and V9 are extracted as updated holding variables.

  Based on these extraction results, the nonvolatile memory data update control unit 70 sets the values of the holding variables V1, V6, and V9 stored in the nonvolatile memory 20 to V1 ′, V6 ′, and V9 ′, respectively. Update.

  As is apparent from the description of FIG. 1 and FIG. 2, according to the configuration of FIG. 1, the access to the holding variable is executed with respect to the volatile memory 60, so that the read performance can be made constant and nonvolatile data can be stored. Speeding up of access processing can be realized.

  And since all the holding variables are stored and held in the volatile memory 60, there is no occurrence of a cache miss hit as in the prior art, and the data processing function does not deteriorate. In executing the processing, the desired performance can be obtained in a stable state.

  Further, since the write operation is performed only in a predetermined drive cycle, the write load can be reduced.

  For devices with extremely poor write performance compared to read performance, high-speed read processing and minimum write processing are performed to maximize overall performance by combining read and write operations. Can be planned.

  Note that the holding variable targeted in the present invention is not limited to the control data targeted for control by the control device, and may be, for example, log information for recording the operating state of the control device.

  FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. Components common to those in FIG. 4 differs from FIG. 4 in that a volatile memory data monitoring unit 80 is provided between the volatile memory 60 and the nonvolatile memory 20 in FIG. Instead, a nonvolatile memory control unit 90 is provided.

  The volatile memory data monitoring unit 80 receives a holding variable that is sequentially written and stored in the volatile memory 60 from the fixed cycle operation control unit 10 and is also transferred from the volatile memory 60 to the nonvolatile memory 20. Is also entered.

  The volatile memory data monitoring unit 80 separates the function of monitoring the change of the holding variable stored in the volatile memory 60 from the functions of the nonvolatile memory data update control unit 70 of FIG. It has been made.

  When the volatile memory data monitoring unit 80 confirms that the holding variable has been last updated from the fixed cycle operation control unit 10 and stored in the volatile memory 60, the check result is notified to the fixed cycle operation control unit 10. At the same time, the holding variable stored in the volatile memory 60 is output to the nonvolatile memory 20.

  The non-volatile memory control unit 90 is obtained by separating and removing the function of monitoring changes in the holding variables stored in the volatile memory 60 from the non-volatile memory data update control unit 70 of FIG. The holding variable output from the volatile memory 60 to the nonvolatile memory 20 via the unit 80 is written and updated in the nonvolatile memory 20 based on the control of the fixed cycle operation control unit 10.

  FIG. 5 is a flowchart for explaining the flow of operation of the control device configured as shown in FIG. In FIG. 4, when the power supply unit 40 is turned on (step S1), the data stored in the volatile memory 60 is initialized by the data initial unit 50 (step S2).

  After the power is turned on, the operation is controlled based on the fixed cycle operation control unit 10 (step S3), and data based on the operation of the fixed cycle operation control unit 10 is sequentially updated and stored in the volatile memory 60 (step S3). S4).

  The volatile memory data monitoring unit 80 monitors a change / difference of a holding variable that is sequentially updated by the fixed cycle operation control unit 10 and stored in the volatile memory 60.

  When it is confirmed that the data output from the fixed cycle operation control unit 10 is a holding variable updated from the previous cycle and stored in the volatile memory 60 (step S5), the difference data is extracted ( Step S6) and output to the non-volatile memory controller 90 (Step S7).

  The nonvolatile memory control unit 90 writes and updates the holding variable output from the volatile memory 60 to the nonvolatile memory 20 via the volatile memory data monitoring unit 80 (step S8). After the writing update of the nonvolatile memory 20, the monitoring operation after step S3 is repeatedly executed.

  According to the configuration of FIG. 4, the function of the nonvolatile memory data update control unit 70 configuring FIG. 1 includes the volatile memory data monitoring unit 80 that monitors changes in the holding variables stored in the volatile memory 60 and the nonvolatile memory data. Since the nonvolatile memory control unit 90 that controls the volatile memory 20 is provided separately, the inspection and adjustment of the volatile memory data monitoring unit 80 and the nonvolatile memory control unit 90 can be performed individually and efficiently. it can.

  As described above, according to the present invention, there is provided a control device capable of obtaining desired performance in a fixed-cycle application that operates at a predetermined cycle without causing a decrease in read performance even if there is no read data on the cache. It can be realized and is suitable as a control device used in various control systems.

DESCRIPTION OF SYMBOLS 10 Fixed-cycle operation control part 20 Non-volatile memory 40 Power supply part 50 Data initial part 60 Volatile memory 70 Non-volatile memory data update control part 80 Volatile memory data monitoring part 90 Non-volatile memory control part

Claims (5)

Volatile memory for storing retention variables;
A non-volatile memory for copying and storing a holding variable stored in the volatile memory;
Volatile memory data update control means for controlling to initialize a holding variable stored in the volatile memory when the power is turned on;
A periodic operation control means for controlling the entire apparatus to operate at a predetermined cycle, and reading / writing the retained variable to / from the volatile memory at a predetermined cycle;
Non-volatile memory data update control means for controlling to copy and store the storage variable last updated and stored in the volatile memory by the fixed cycle operation control means;
And a control device characterized by comprising:   2. The control apparatus according to claim 1, wherein the fixed cycle operation control means includes a function of the nonvolatile memory data update control means. Volatile memory for storing retention variables;
A non-volatile memory for copying and storing a holding variable stored in the volatile memory;
Volatile memory data update control means for controlling to initialize a holding variable stored in the volatile memory when the power is turned on;
A periodic operation control means for controlling the entire apparatus to operate at a predetermined cycle, and reading / writing the retained variable to / from the volatile memory at a predetermined cycle;
Non-volatile memory data update control means for controlling to store the storage variable last updated and stored in the volatile memory by the fixed cycle operation control means, and to store it in the non-volatile memory;
Volatile memory data monitoring means for monitoring a holding variable that is sequentially written and stored in the volatile memory by the fixed cycle operation control means, and outputting a holding variable updated at the end of the fixed cycle processing to the nonvolatile memory,
And a control device characterized by comprising:   4. The control apparatus according to claim 3, wherein the fixed cycle operation control means includes a function of the nonvolatile memory data update control means.   The control apparatus according to claim 1, wherein the fixed-cycle operation control unit operates a fixed-cycle application that operates at a predetermined cycle.

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