JP2013152636A - Information processing device and task scheduling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device capable of prohibiting a task having lower necessity for execution from being executed.SOLUTION: An information processing device 100 allocates a task to a resource in the order of priority when there is a conflict among execution timings of a plurality of tasks, and includes a task registration table 33 and scheduling control means 32. In the task registration table 33, for each data shared by a cycle start task and a conflict task having a higher priority than the cycle start task, a set thereof is registered in advance. When there is a conflict in an execution timing between the cycle start task and the conflict task registered in the task registration table in association with the cycle start task, the scheduling control means 32 executes the conflict task in preference to the cycle start task to prohibit execution of the cycle start task in a conflict period.

Description

  The present invention relates to an information processing apparatus that assigns, to resources, high tasks that are executed in order of priority when execution timings of a plurality of tasks compete.

  Multitask processing is known in which a plurality of tasks and threads (hereinafter simply referred to as tasks) are assigned to a CPU and executed on one microcomputer. This allocation control is mainly performed by an OS (Operating System) scheduler or the like. The task has a description of priority, and the scheduler assigns the task to the CPU in principle from the task with the highest priority. Here, the task assignment method of the scheduler includes non-preemptive and preemptive. In non-preemptive allocation, when a task waiting for execution occurs for a task that is already being executed by the CPU, the scheduler waits for the task being executed to end. In preemptive assignment, if the priority of a task waiting to be executed is higher than the priority of the task being executed, the scheduler forcibly terminates the task that is executing and causes the task waiting for execution to be sent to the CPU. assign. In preemptive multitasking, the priority relationship can be maintained, so that real-time performance can be easily guaranteed.

  However, in preemptive multitasking, context switching processing required for task switching may be an overhead. Therefore, a technique for reducing overhead has been conventionally considered (see, for example, Patent Document 1). In Patent Document 1, a dedicated register is prepared for a plurality of competing periodic driving tasks. When a task conflicts, a period in which this task is allocated to the CPU by high priority task information stored in the dedicated register. A driving task execution device is disclosed.

JP 2010-102567 A

  However, although there is a possibility that the overhead can be reduced in Patent Document 1, since a task with a low priority is eventually executed after the execution of a task with a high priority, the CPU load is increased. is there. Further, Patent Document 1 has a problem that a dedicated register is required.

  FIG. 1 is an example for explaining an increase in load due to execution of a low priority task. Task A is a task that is periodically executed by a timer interrupt, for example, and task B is a task that is executed by occurrence of an event, for example. Here, it is assumed that the priority of task B> the priority of task A. Note that ISR (Interrupt Service Routine) is a service that performs interrupt processing, and performs processing that executes tasks corresponding to interrupts. Sometimes called an interrupt handler.

  Task A performs, for example, data acquisition from a sensor, calculation, and writing to a shared memory. Task B reads data from the shared memory and controls the in-vehicle device. Thus, task A and task B have data dependency. As task B, it is preferable to read out (new) data updated by task A.

  Since the priority of task B> priority of task A, if the execution timing conflicts as in the second cycle, the scheduler assigns the task B to the CPU with priority over the task A (in the circle in the figure). . Therefore, in this cycle, task A cannot update the data in the shared memory, and task B reads the data one cycle before from the shared memory. After the task B ends, the scheduler assigns the task A to the CPU, so the task A updates the data in the shared memory.

  Since the cycle of task A does not change, task A updates the data in the shared memory when the next cycle (the third cycle in the figure) arrives. Therefore, the data update cycle is shortened, and the data updated after the task B is executed is updated without being read by the task B. For this reason, assignment of task A to the CPU (assignment of the second cycle) is wasted, and there is a problem that the CPU load is unnecessarily increased.

  In view of the above problems, an object of the present invention is to provide an information processing apparatus that can prohibit execution of a task that is less necessary to be executed.

  In the information processing apparatus that assigns tasks to resources in order of priority when the execution timings of a plurality of tasks compete, the present invention shares data that is shared by the periodically activated task and the competing task having a higher priority than the periodically activated task Each time, a task registration table in which a set of a cyclic start task and the competing task is registered in advance, the cyclic start task, and an execution timing of the competing task registered in the task registration table in association with the cyclic start task Scheduling control means for preferentially executing the competing task and prohibiting the execution of the periodic activation task in the conflicting period when there is a conflict.

  It is possible to provide an information processing apparatus that can prohibit execution of a task that is less necessary to be executed.

It is an example explaining the increase in load by execution of a low priority task. It is an example of the figure explaining task assignment by an information processor. It is an example of the hardware block diagram of the information processing apparatus mounted in a vehicle. It is an example of the figure explaining scheduling of a task. It is an example of the figure explaining the process of a task, and its competition. It is an example of the figure explaining the timing which the task A and the task B compete. It is a figure which shows an example of the functional block diagram of a scheduler, and a task exclusive registration table. FIG. 10 is an example of a flowchart illustrating a procedure in which a scheduling control unit prohibits execution of a low priority task. (Example 2) which is a function block diagram of a scheduler, a task exclusive registration table, and an example of a task activation management data recording unit. FIG. 10 is an example of a flowchart illustrating a procedure in which a scheduling control unit prohibits execution of a low priority task (second embodiment). (Example 3) which is a functional block diagram of a scheduler, a task exclusive registration table, a task activation management data recording unit, and an interpolation data recording unit. FIG. 10 is an example of a flowchart illustrating a procedure in which a scheduling control unit prohibits execution of a low priority task (third embodiment). It is an example of the flowchart figure which shows the operation | movement procedure of the task A and an interpolation data control part. (Example 4) which is a functional block diagram of a scheduler, a task exclusive registration table, a task activation management data recording unit, and an interpolation data recording unit. FIG. 10 is an example of a flowchart illustrating a procedure in which a scheduling control unit prohibits execution of a low priority task (Example 4).

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 2 is an example of a diagram illustrating task assignment by the information processing apparatus 100 according to the present embodiment. The scheduling control unit 32 is a function of a scheduler and OS described later, and controls assignment of tasks to the CPU.

  Task A performs data acquisition from the sensor, calculation, and writing to the shared memory. Task B reads data from the shared memory and controls the in-vehicle device. Thus, task A and task B have data dependency. Task A is a task that is periodically executed by a timer interrupt, for example. For example, task B is a task that is executed when an event occurs, but task B may also be a task that is executed at regular intervals.

  When the execution timings of task A and task B conflict, the scheduling control unit 32 refers to the exclusive registration table and determines whether it is necessary to control task A allocation. In the exclusive registration table, tasks having data dependency are registered in association with each other. In the example in the figure, task A is registered as a control target for competing task B. The task to be controlled is a task whose execution is prohibited when it conflicts with a competing task.

  When the execution timings of task A and task B overlap in the same period, the scheduling control unit 32 refers to the exclusive registration table and determines that it is not necessary to execute task A. Then, the scheduling control unit 32 prohibits execution of the task A. That is, as shown in the figure, task A is not executed in the conflicting period when the execution timing of the fixed period arrives. Therefore, conventionally, the task A is executed after the task B. However, since it is not executed in the present embodiment, it is possible to prevent wasteful use of resources such as the CPU.

[Configuration example]
FIG. 3 is an example of a hardware configuration diagram of the information processing apparatus 100 mounted on the vehicle. The information processing apparatus 100 is assumed to be mounted on an ECU (Electronic Control Unit), but its application is not limited to a vehicle. There are various types of ECUs mounted on the vehicle, such as an engine ECU, a brake ECU, a body ECU, a navigation ECU (AV / information processing ECU), and a gateway ECU, depending on main functions. The information processing apparatus 100 according to the present embodiment can be mounted without being influenced by the difference in the functions of the ECU. Further, the information processing apparatus 100 may be mounted on an ECU in which a plurality of functions are integrated into one.

  The information processing apparatus 100 includes a CPU 11, a RAM 12, a ROM 13, an INTC 14, a WDT 15, a DMAC 16, and a bridge 17 connected to a main bus 21. The bridge 17 has an ADC (Analog to Digital Converter) via a peripheral bus 22. 19 and a CAN controller 20 are connected.

  The CPU 11 has one or more cores 1 to n. That is, each of the cores 1 to n has a general arithmetic function (for example, an arithmetic device such as an ALU, an instruction buffer, an instruction decoder, a register set, etc.). Instead of the CPU 11 having a plurality of cores 1 to n on one chip, a plurality of CPUs 11 may be independently connected to the main bus 21.

  The ROM 13 is a non-volatile memory such as a flash memory, and stores a program 30 executed by the CPU 11, initial values, parameters, and the like.

  The INTC 14 has an interrupt register such as a timer in which a flag is set in response to various interrupt requests. The INTC 14 arbitrates based on the priority of the peripheral device and notifies the CPU 11 of a reception interrupt such as a timer and I / O 18 and an interrupt request input from the peripheral device via other interrupt terminals. As a result, the CPU 11 reads an instruction at an address determined according to the interrupted peripheral device from the ROM 13 and executes the process. In this embodiment, the ISR 30 is activated to perform interrupt processing. If the count value is not cleared before the count value overflows, the WDT 15 performs fail-safe such as resetting the information processing apparatus.

  The RAM 12 is a work area for the CPU 11 to execute the program 30. The CPU 11 reads the program 30 from the ROM 13 and, if necessary, reads data from the RAM 12 via the main bus 21 and executes the program 30. The DMAC 16 transmits data from the RAM 12 to the peripheral device via the bridge 17 according to an instruction from the CPU 11. In response to an instruction from the CPU 11 interrupted by the peripheral device, the data is received from the peripheral device via the bridge 17 and written to the RAM 12.

  The bridge 17 absorbs a difference in frequency between the main bus 21 and the peripheral bus 22, and transfers data between the main bus side circuit and the peripheral bus side circuit to each other. The bridge 17 is a multiplexer, a bridge circuit, or the like, and is connected to each of one or more I / O 18, ADC 19, and CAN controller 20 for each channel, and transmits / receives data to / from these peripheral devices.

  The I / O 18 is an input / output interface for serial communication, for example, and is used to communicate with actuators, switches, monitoring circuits, and other microcomputers. As communication standards, I2C, UART, and the like are known. The ADC 19 converts analog signals detected by various sensors into digital signals. The ADC 19 notifies the CPU 11 of the end of conversion via the INTC 14. The CAN controller 20 is a communication device for communicating with other ECUs connected via an in-vehicle network. When receiving a communication data transmission request from the CPU 11, the CAN controller 20 stores the CAN ID and data in each field of the frame and outputs them to the CAN bus. Further, when the CAN controller 20 detects the communication data of the CAN ID to be received, the CAN controller 20 captures it and interrupts it to the CPU 11 via the INTC 14 to notify it.

[About scheduling]
FIG. 4 is an example of a diagram explaining task scheduling. A task is obtained by extracting several functions included in one program (for example, the Main function as one program) for each function. The developer can design what function is one task. Specifically, a function, a subroutine, and the like in the Main function correspond. A function executed by an interrupt or the like is also a task.

  In general, a task goes through a dormant state, an executable state, an executing state, and a waiting state. The dormant state is the state of a task that has just been created or has completed execution. The execution state refers to the state of the task currently being executed by the core. There are less than the number of cores in the running state. The executable state refers to a task state in which input / output of peripheral devices is completed and ready for execution. The transition from the sleep state to the executable state is called wake-up. The task in the executable state is assigned (dispatched) to the core according to the priority described later when the core finishes the task in the execution state (if the core is free). The wait state is a state of a task that is waiting until a necessary condition for execution is satisfied, such as a peripheral device completing input / output.

  For example, a program such as the Main function generates a task by using a system call mechanism using the task ID, address, priority, etc. of the task corresponding to the type of interrupt as arguments. As a result, the scheduler 31 is called, and the scheduler 31 creates a task control block (TCB) 38 (an ISR may create a TCB). The TCB 38 includes, for example, information such as a task ID, a task (function) start address, an end address, a context (for example, a general-purpose register, a program counter, a stack pointer, a status flag status), and a status indicating a status. . As a result, the task is in a dormant state.

  When the ISR 30 corresponding to the interrupt (or common regardless of the type of interrupt) is executed due to the occurrence of the interrupt, the ISR 30 makes a system call to wake up the task using, for example, the task ID as an argument. As a result, the scheduler 31 changes the status of the TCB 38 so that the task can be executed. Thereafter, the scheduler 31 performs preemptive priority control.

The scheduler 31 manages a ready queue for each priority. In the ready queue, tasks are arranged in order of execution for each priority. The order of tasks at the same priority is the order in which the tasks are ready to be executed. The ready queue is, for example, a structure in which task IDs are arranged in a queue structure. The scheduler 31 selects a ready queue in accordance with the priority of a task that has become executable, and registers a task ID at the end of the ready queue. Then, for example, the scheduler 31 determines a task to be assigned to a resource such as the CPU 11 as follows.
-Search for the task with the highest priority ready queue. If there are tasks, it is determined that the tasks are assigned in the order of arrangement in the queue.
If there is no task in the ready queue with the highest priority, the task of the ready queue with the next highest priority is searched. If there are tasks in this ready queue, it is determined that the tasks are assigned in the order in the queue.

  As described above, the scheduler 31 determines that tasks are assigned in order from the task having the highest priority to the plurality of tasks having the same priority in an executable state. In addition, when only the priority is considered in this way, a task that is not executed for a long time is generated. Therefore, the scheduler 31 exceptionally uses a round robin method such as executing a task of priority 2 when a task of priority 1 is executed for a predetermined time.

  Allocation to resources such as the CPU 11 is performed by a dispatcher. The dispatcher allocates a task to the CPU 11 by referring to the start address of the TCB 38 and placing it on a PC (program counter). In the case of a task that has already waited, the context is reset in a register or the like in order to reproduce the previous execution state.

  The task in the execution state disappears by a system call at the end of the task, and enters a dormant state by a system call waiting for waking up. Also, if necessary, such as waiting for data from a peripheral device (detecting the state of the semaphore), a system call for entering the wait state is executed. As a result, the scheduler 31 sets the status of the TCB 38 of this task in a waiting state, and assigns the task to be assigned next by the dispatcher to the CPU or the like. Note that the scheduler 31 monitors the semaphore that has caused the wait state, and when the semaphore changes, automatically changes the waiting task to an executable state.

  In this embodiment, the ISR uses the CPU before the task, and the task is ready to be executed when the ISR wakes up the task. Contention timing conflicts between multiple tasks can occur if either ISR is executed. Therefore, hereinafter, “task interruption occurs”, which is the trigger of ISR, will be described as a trigger of conflict of execution timing. The execution timing conflict will be described later.

[Example of task conflict]
FIG. 5A is an example of a diagram illustrating task processing and its competition.
Task A: Periodic start task B: Event start task (occurs periodically)
Priority of task B> priority of task A Task A performs data acquisition from the sensor, calculation, and writing to the shared memory. Task B reads data from the shared memory and controls the in-vehicle device. In the second cycle, an interrupt for task B occurs while an ISR for task A is being executed. Task A may be in the execution state.

  The scheduler 31 assigns the task B to the CPU 11 with priority over the task A. Therefore, in this cycle, task A cannot update the data in the shared memory, and task B reads the data one cycle before from the shared memory. Thereafter, even if task A enters the execution state, the data updated by task A is updated without being read out by task B.

  Therefore, the scheduling control unit 32 described later prohibits execution of the task A. By doing so, it is possible to prevent the task A from being unnecessarily assigned to the CPU 11.

  Note that the tasks A and B compete as shown in FIG. 5A when the CPU 11 is a single core having only one core. When the CPU 11 is multi-core, the core 1 does not need to interrupt the task A and the task B does not need to be prioritized only by the priority level. In order to maintain the data dependency of two multi-core tasks, for example, the task A can be executed first by waiting for the task A to update the data of the task A using a semaphore.

  However, in the present embodiment, priority is given to the task B being executed without delay rather than data consistency, so the task B is given priority regardless of whether it is a single core or a multi-core. Due to data dependency, tasks that compete with each other are registered in the task exclusive registration table 33. Therefore, the task control of this embodiment can be realized regardless of whether the CPU 11 is a single core or a multi-core.

  FIG. 5B is an example of a diagram illustrating competition between task A and task B (C). Task A is executed, for example, when a timer interrupt occurs at a cycle of 2 milliseconds. Task B is executed by the occurrence of an event interrupt that the crank angle is 45 degrees. Task C is executed by the occurrence of an event interrupt that the crank angle is 60 degrees. Therefore, for example, in the figure, a conflict between task A and task B occurs in 4 milliseconds, and a conflict between task A and task C occurs in 14 milliseconds.

  According to the present embodiment, the scheduling control unit does not execute the task A in 4 milliseconds and 14 milliseconds, so that the CPU load can be reduced. In the vehicle control including the crank angle, the higher the vehicle speed and the engine speed, the more frequently the task for the control is executed. In order to cope with such a situation, it is necessary to increase the function of the CPU 11 (increase the cost). However, in this embodiment, the task A is not executed even if it competes, so the function of the CPU 11 is increased. There is no need.

[About execution timing conflicts]
The timing when task A and task B compete with each other will be described with reference to FIG.
(I) When an interruption of task B occurs before task A, task B having a higher priority is executed as it is (without context switch). Although task A is executed after task B, since task B does not refer to the data updated by task A, execution of task A is wasted. For this reason, it is preferable that the scheduling control unit 32 does not execute the task A.
(Ii) When task B and task A interrupts occur simultaneously, task B is executed first according to priority. Therefore, this case is the same as the case where the task B is in an executable state before the task A.
(Iii) When task B interrupt occurs after task A (same as above)
Task B interrupt occurs during task A ISR30 or task A execution. Task A is canceled by preemption, and task B is assigned to the CPU 11. After this, even if task A is assigned to CPU 11, task B does not refer to the data updated by task A, so execution of task A is wasted. For this reason, the scheduling control unit 32 does not execute the task A.

  Therefore, execution of task A should be prohibited when task B interrupt occurs between task A interrupt and task A termination, or task B interrupt occurs. This is a case where an interruption of task A occurs between task B and the end of task B. Therefore, in all cases (i) to (iii), the scheduling control unit 32 prohibits the execution of the task A.

  In the case of (iii), the task B may be interrupted after the ISR ends and the task A enters the execution state. In this case, the execution of task A can be completed without context switching from task A to task B. This is because when the execution time of task A is short, the load is reduced if context switching is not performed.

[Scheduler function examples]
FIG. 7 is a functional block diagram of the scheduler and an example of the task exclusive registration table 33. The scheduler 31 has a scheduling control unit 32, and a task exclusive registration table 33 is stored in the RAM 12.

  In the task exclusion registration table 33, the priority of a task in which data conflict occurs is registered. The task exclusive registration table 33 is described in advance as a part of the scheduler 31 by the developer. The task exclusive registration table 33 has a plurality of sets (sets 1 to n), and the conflicting task and the task to be controlled are registered. A plurality of tasks to be controlled may be registered in one competing task. The conflicting task is a task that is executed with priority, and the controlled object is a task that is prohibited from executing when it competes with the conflicting task. In many cases, the priority of the competing task> the priority of the control target. For example, since it is known to the developer that the tasks competing for the data X are A and B, a set as shown in the figure can be created for various types of competing data.

  The scheduling control unit 32 is one of the functions of the scheduler 31. When the scheduling control unit 32 competes with a competing task, the scheduling control unit 32 detects a control target task from, for example, an executable task and prohibits the execution of the task. That is, when an interrupt of a competing task occurs, the scheduling control unit 32 determines whether or not the control target task associated with the task exclusive registration table 33 is included in an executable state or a dormant task. When a task to be controlled is detected (in the case of (iii) in FIG. 6), the scheduling control unit 32 deletes the TCB 38 and deletes it from the ready queue when it is registered in the ready queue. If not registered in the ready queue, the TCB is deleted without registering in the ready queue. As a result, the task A is prohibited from entering the execution state.

  In addition, when an interrupt of the task A to be controlled occurs, the scheduling control unit 32 determines whether or not the competing task (task B) associated with the task exclusive registration table 33 is included in the executable state task, It is determined whether or not it is in an execution state. Also in this case (in the case of (i) in FIG. 6), since it is less necessary to execute the task A to be controlled, the scheduling control unit 32 deletes the TCB of the task A without registering it in the ready queue, and the TCB 38 Erase.

[Operation procedure]
FIG. 8 is an example of a flowchart illustrating a procedure in which the scheduling control unit 32 prohibits execution of a task having a low priority. The procedure of FIG. 8 starts when, for example, a new interrupt occurs.

  First, the scheduling control unit 32 determines whether or not a task to be controlled is registered in the task exclusive registration table 33 for the interrupted task (S10).

  When the control target task is registered in the task exclusive registration table 33 (Yes in S10), the scheduling control unit 32 determines whether there is a control target task (task A) in the ready queue (S20). ). As a result, it is possible to specify the task A that does not need to be executed by executing the task B in which the interrupt has occurred.

  When there is a task to be controlled in the ready queue (Yes in S20), the scheduling control unit 32 prohibits execution of task A in the ready queue (S30). This prevents the task A from being executed.

  If there is no task to be controlled in the ready queue (No in S20), the scheduler 31 registers task B in the ready queue because there is no need to prohibit execution of the task to be controlled (S60). As a result, task B is executed.

  If the task to be controlled is not registered in the task exclusive registration table 33 (No in S10), the scheduling control unit 32 determines whether there is a competing task in the ready queue as seen from the task that caused the interrupt. (S40). Thereby, it is possible to determine whether or not there is a task B that makes it unnecessary to execute the task A in which the interrupt has occurred.

  If there is a competing task in the ready queue (Yes in S40), the scheduling control unit 32 prohibits execution of the task A that is the control target task in which the interrupt has occurred (S50). That is, task A disappears without being registered in the ready queue.

  If there is no competing task in the ready queue (No in S40), since the task A in which the interrupt has occurred is not a control target task, the scheduler 31 registers the task A in the ready queue (S60). Therefore, task A is executed without being prohibited unless execution timing conflicts with task B (unless task B interrupts thereafter).

  As described above, the information processing apparatus 100 according to the present embodiment prohibits the execution of the task A having a low priority when the execution timings of two tasks having data dependency conflict with each other. Useless use can be prevented.

  In the first embodiment, the execution of the task A is forcibly prohibited. However, if the execution of the task A is prohibited at a high frequency, the reliability of the data used by the task B for the calculation may be reduced. Therefore, in the present embodiment, the information processing apparatus 100 that determines the validity of the prohibition of execution of task A will be described.

  FIG. 9 is a diagram illustrating an example of a functional block diagram of the scheduler 31, a task exclusive registration table 33, and a task activation management data recording unit 34. In FIG. 9, the description of the same part as in FIG. 7 is omitted. In this embodiment, a task activation management data recording unit 34 is provided in the RAM 12. The task activation management data recording unit 34 has fields of “number of times”, “number of activations”, and “threshold value” for each piece of data to be competing. Among these, the “threshold value” is a fixed value, and a developer or the like is described in advance as a part of the scheduler 31 or the like.

  “Number of times” and “Number of activations” are fields that the scheduling control unit 32 updates. The “number of times” is the number of times that the task A is executed without being prohibited and the data X is continuously updated. In other words, the scheduling control unit 32 increases the “number of times” by one every time the task A is completed, and sets the “number of times” to zero when the execution of the task A is prohibited.

  Further, the “number of activations” is the number of times that the scheduling control unit 32 prohibits execution of the task A that is a control target. Therefore, the scheduling control unit 32 increases the “number of activations” by one each time the execution of the task A is prohibited as in the first embodiment.

  The “threshold value” is a value compared with the “number of times”. That is, if the “number of times” is larger than the “threshold value”, the data X is sufficiently updated, and it is considered that there is little trouble for the task B even if the task A is not updated. Further, if the “number of times” is equal to or less than the “threshold value”, the update frequency of the data X is low, and it is considered that the execution of the task A should not be prohibited.

  As described above, the scheduling control unit 32 according to the present embodiment compares the “number of times” with the “threshold value” and determines whether or not the execution of the task A is prohibited.

  Note that the “number of activations” holds the last value unless the RAM 12 is initialized by removing the battery or the like. A large “number of activations” means that the number of data conflicts and the number of execution prohibitions of task A are large, and therefore it is not preferable that the “number of activations” is extremely large. Therefore, in a dealer or the like, a serviceman can connect the scan tool to the in-vehicle network to read the “number of activations” and use it for vehicle inspection. It should be noted that the “number of activations” may be initialized every predetermined period (for example, one trip, every predetermined distance traveling).

  FIG. 10 is an example of a flowchart illustrating a procedure in which the scheduling control unit 32 prohibits execution of a task having a low priority. In this embodiment, in steps S25 and S45, the scheduling control unit 32 determines whether or not “number of times”> “threshold value”.

  That is, when there is a task to be controlled in the ready queue (Yes in S20), the scheduling control unit 32 determines whether or not the “number of times” in the task activation management data recording unit 34 is larger than the “threshold value” (S25). ). The scheduling control unit 32 prohibits execution of the task A in the ready queue only when the “number of times” is larger than the “threshold value” (Yes in S25) (S30). Thereby, when the task A is continuously executed more than the threshold value, the task A can be prohibited from being executed.

  If there is a competing task in the ready queue (Yes in S40), the scheduling control unit 32 determines whether or not the “number of times” in the task activation management data recording unit 34 is larger than the “threshold value” (S45). Only when the “number of times” is larger than the “threshold value” (Yes in S45), the scheduling control unit 32 prohibits execution of the task A to be controlled (S50). That is, task A disappears without being registered in the ready queue only when task A is continuously executed more than the threshold value.

  If the “number of times” is not greater than the “threshold value” in steps S25 and S45 (No in S25 and S45), the process proceeds to step S60, so that the scheduling control unit 32 registers task B in the ready queue and Is registered in the ready queue. Therefore, in this case, task A is executed without being prohibited.

  Thereafter, the scheduling control unit 32 updates the task activation management data recording unit 34 (S70). When the task A is executed, the “number of times” is increased by one, and when the execution of the task A is prohibited, the “number of activations” is increased by one and the “number of times” is initialized to zero.

  According to the information processing apparatus 100 of the present embodiment, in addition to the effects of the first embodiment, only when the execution frequency of the task A is determined and there is no possibility that the reliability of the data used by the task B in the calculation is reduced. The execution of task A can be prohibited.

  In the first and second embodiments, task B, which has a higher priority than task A, uses data that is slightly older in time for calculation because task A does not update data. In the present embodiment, an information processing apparatus 100 that obtains data when task B is executed from this old data by interpolation of past data will be described.

  FIG. 11 is a diagram illustrating an example of a functional block diagram of the scheduler 31, a task exclusive registration table 33, a task activation management data recording unit 34, and an interpolation data recording unit 36. In FIG. 11, the description of the same parts as those in FIG. 9 is omitted. In this embodiment, the scheduler 31 has an interpolation data control unit 35, and the RAM 12 is provided with an interpolation data recording unit 36.

  The interpolation data recording unit 36 records a predetermined number of past data (acquired values) and a predicted value obtained from the past acquired values. In the interpolation data recording unit 36, data written by the task A into the RAM 12 is recorded every 2 milliseconds, which is the task A activation cycle. When execution of task A is prohibited, task B uses this predicted value for control of the in-vehicle device. Specifically, the scheduling control unit 32 reads the predicted value from the interpolation data recording unit 36 and writes it in the RAM 12 instead of the task A. Task B can read out the predicted value from the RAM 12 and use it.

  The interpolation data control unit 35 registers the acquired value read by the task A in the interpolation data recording unit 36. The interpolation data recording unit 36 is a ring buffer. For example, when six pieces of data are recorded, the oldest data is overwritten. When data is newly recorded in the interpolation data recording unit 36, the interpolation data control unit 35 updates the predicted value. That is, the next time task A is executed, the data that task A will write to RAM 12 is predicted and written to the predicted value of interpolation data recording unit 36.

Any prediction algorithm may be used, and since it is often different depending on data, the prediction is performed with an optimal algorithm. For example, if the data increases with time, the interpolation data control unit 35 calculates a difference between several past data, and sets the average of the differences as a predicted value added to the last data.
For example, since the difference in data for 3 to 6 times is “6, 6, 5”, the average is 6 (rounded up). Therefore, the predicted value = 31 + 6 = 37.

  If the data does not change much with time, the interpolation data control unit 35 uses an average value of several past data as a predicted value. For example, the predicted value = 26 from the average of 3 to 6 data.

  The last data may be used as the predicted value (31) as it is. By doing so, the CPU load can be reduced.

  The “timer value” represents the time when the task A processed the data X (calculated or written in the RAM 12). Based on the “timer value”, the scheduling control unit 32 can detect the activation interval of the task A. Naturally, when the execution of task A is prohibited, the interval of the “timer value” increases.

  Further, the task activation management data recording unit 34 has a field “with interpolation”. The field “with interpolation” is a flag for controlling whether or not the interpolation data control unit 35 needs to create the interpolation data recording unit 36. The scheduling control unit 32 is also a flag for controlling whether or not the predicted value is read from the interpolation data recording unit 36 and written to the RAM 12 instead of the task A.

  FIG. 12 is an example of a flowchart illustrating a procedure in which the scheduling control unit 32 prohibits execution of a task with a low priority. In this embodiment, after the execution of task A is prohibited in steps S30 and S50, the scheduling control unit 32 refers to the task activation management data recording unit 34 to determine whether “interpolation” is “present” or not. Determine (S55).

  When “interpolation” is “present” (Yes in S55), the scheduling control unit 32 reads the predicted value from the interpolation data recording unit 36 and writes it in the RAM 12 (S56). Thereafter, since the ready queue is updated and task B is executed, task B can control the in-vehicle device using the predicted value.

  FIG. 13 is an example of a flowchart showing an operation procedure of the task A and the interpolation data control unit 35. When the task B and the execution timing are executed without conflict, or when the task B and the execution timing conflict with each other, the task A reads the sensor value (S101), the calculation (S102), and the calculation result. Writing to the RAM 12 is performed (S103).

  When the scheduling control unit 32 detects the end of the task A by the system call, the “interpolation present” of the task activation management data recording unit 34 is “present”, so that the interpolation data control unit 35 is requested to interpolate the predicted value. To do.

  Thereby, the interpolation data control unit 35 starts the following processing. The interpolation data control unit 35 reads the data X from the RAM 12 (S111), and writes the read data X in the interpolation data recording unit 36 (S112). The data updated in the interpolation data recording unit 36 is the oldest data.

  The interpolation data control unit 35 updates the predicted value using a predetermined number of pieces of data in the interpolation data recording unit (S113). Thereby, when execution of task A is prohibited next time, task B can control the in-vehicle device using the predicted value.

  According to the information processing apparatus 100 of the present embodiment, in addition to the effects of the first and second embodiments, when the task A is not executed, the data of the task A is predicted from the past data. The vehicle-mounted device can be controlled using

  In the present embodiment, the information processing apparatus 100 that prohibits the execution of the task A when the update of the data X is delayed even when the “number of times” of the continuous data update counter is smaller than the “threshold value” will be described. .

  FIG. 14 is a diagram illustrating an example of a functional block diagram of the scheduler 31, a task exclusive registration table 33, a task activation management data recording unit 34, and an interpolation data recording unit 36. In FIG. 14, the description of the same part as in FIG. 11 is omitted. In this embodiment, the task activation management data recording unit 34 is newly provided with fields of “activation period” and “period threshold value”. The “activation period” is an actual activation period of task A. The “start cycle” is data updated by the scheduling control unit 32, and the scheduling control unit 32 refers to the “timer value” of the interpolation data recording unit 36 and sets it to the “start cycle”. Since the ideal activation cycle of task A is known in advance (for example, 2 milliseconds), it is detected to what extent it is delayed from the ideal activation cycle by the “activation cycle”.

  The “periodic threshold value” is a value to be compared with the “activation period”. When “activation period> periodic threshold value”, the scheduling control unit 32 determines that the execution of the task A should be prohibited. For example, if the activation period of task A is delayed because the vehicle speed is high, the update of data that does not stop execution of task A is further delayed. Therefore, when “start cycle> cycle threshold”, the scheduling control unit 32 executes task A even when “number of times (for example, 10 times)” is smaller than “threshold value (for example, 12 times)”. Ban.

  FIG. 15 is an example of a flowchart illustrating a procedure in which the scheduling control unit 32 prohibits execution of a task with a low priority. In the present embodiment, in steps S26 and S46, the scheduling control unit 32 determines whether or not the “start cycle” is larger than the “cycle threshold”.

  That is, when there is a task to be controlled in the ready queue (Yes in S20), the scheduling control unit 32 determines whether or not the “number of times” is larger than the “threshold value” (S25). When the “number of times” is equal to or smaller than the “periodic threshold” (No in S25), the scheduling control unit 32 further determines whether the “activation period” of the task activation management data recording unit 34 is greater than the “periodic threshold”. Determine (S26).

  If the “start cycle” is larger than the “cycle threshold” (Yes in S26), the scheduling control unit 32 prohibits the task A from being executed and advances the process to step S60. As a result, when the activation period of task A seems to be delayed, the execution of task A can be prohibited to prevent an increase in processing delay.

  If there is a competing task in the ready queue (Yes in S40), the scheduling control unit 32 determines whether or not the “number of times” in the task activation management data recording unit 34 is larger than the “threshold value” (S45). When the “number of times” is equal to or less than the “threshold value” (No in S45), the scheduling control unit 32 further determines whether the “start cycle” is larger than the “cycle threshold value” (S46).

  If the “start cycle” is greater than the “cycle threshold” (Yes in S46), the scheduling control unit 32 prohibits execution of the task A and advances the process to step S60. As a result, when the activation period of task A seems to be delayed, the execution of task A can be prohibited to prevent an increase in processing delay.

  According to the present embodiment, in addition to the effects of the first to third embodiments, even when the “number of times” of the continuous data update counter is smaller than the “threshold value”, if the update of the data X is delayed, the task A It is possible to reliably update the data.

11 CPU
12 RAM
31 Scheduler 32 Scheduling Control Unit 33 Task Exclusive Registration Table 34 Task Activation Management Data Recording Unit 35 Interpolation Data Control Unit 36 Interpolation Data Recording Unit 38 TCB
100 Information processing apparatus

Claims (8)

When the execution timings of multiple tasks conflict, in the information processing apparatus that assigns tasks to resources in order of priority,
A task registration table in which a set of a cyclic start task and the competing task is registered in advance for each data that is shared by a cyclic start task and a competing task having a higher priority than the cyclic start task,
When the execution timing of the conflicting task registered in the task registration table in association with the periodic activation task and the periodic activation task conflicts, the competitive task is preferentially executed, and the periodic activation in the conflicting cycle Scheduling control means for prohibiting execution of tasks;
An information processing apparatus comprising: The number of times the execution of the periodic start task is continuously executed without being prohibited, and a start management table in which a lower limit value of the number of times is registered;
The scheduling control means, when the execution timing of the competing task registered in the task registration table in association with the periodic activation task competes, only when the number of times is larger than the lower limit value, Prohibit execution of cyclically activated tasks,
The information processing apparatus according to claim 1. A data registration table in which past data generated by the cyclic start task is registered in time series;
Data writing means for writing the data generated by the periodic start task to the data registration table when the periodic start task is executed,
When the execution timing of the competing task registered in the task registration table in association with the periodic activation task conflicts with the periodic activation task, the scheduling control unit is configured to store the past one registered in the data registration table. Providing predicted values predicted from one or more data to the competing task, and executing the competing task with priority.
The information processing apparatus according to claim 2. The data writing means writes, in the data registration table, cycle information on which the cycle activation task has been executed,
An upper limit value of the activation cycle of the periodic activation task is registered in the activation management table,
The scheduling control means prohibits the execution of the periodic activation task in a conflicting period even when the number of times is equal to or less than the lower limit value when the period information of the data registration table exceeds the upper limit value.
The information processing apparatus according to claim 3. The scheduling control means records in the activation management table the number of times the execution of the periodic activation task in the conflicting period is prohibited;
The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. The scheduling control means has an instruction to interpolate data in the data registration table when the execution timing of the competing task registered in the task registration table in association with the periodic activation task conflicts with the periodic activation task. Only if the prediction value is provided to the competing task,
The information processing apparatus according to claim 3. The periodic start task is a task that is periodically woken up by a timer, performs a calculation on data acquired from a peripheral circuit, and updates data on the memory, and the competing task is woken up by an event signal detected by a sensor, A task to read data and control the device,
The information processing apparatus according to claim 1, wherein: In the task scheduling method of the information processing apparatus that assigns tasks to resources in order of priority when execution timings of a plurality of tasks conflict,
The scheduling control means refers to a task registration table in which a set of the periodic start task and the competing task is registered in advance for each data shared by the periodic start task and the competing task having a higher priority than the periodic start task. And
When the execution timing of the conflicting task registered in the task registration table in association with the periodic activation task and the periodic activation task conflicts, the competitive task is preferentially executed, and the periodic activation in the conflicting cycle Prohibit execution of tasks,
A task scheduling method characterized by the above.

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