JP2007164421A - Parallel processors, parallel processing method and parallel processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To process interruptions to be processed by respective OSes without discrepancy in a multi-OS system wherein a guest OS is operated as one of the tasks of a host OS, and to prevent the task processing of each OS from being affected by the interruption to be processed by the different OS. <P>SOLUTION: When an execution device 901 executes the guest OS 200 and when it executes a host task 110 other than that, an interruption vector rewrite part 323 rewrites the contents of an interruption vector stored by an interruption vector storage part 311. While the execution device 901 executes the OS different from the OS to process the interruption, the interruption vector indicates not an interruption processing program but switching programs 669 and 679. When the switching programs are executed by the interruption and the OS is switched, the interruption vector rewrite part 323 rewrites the interruption vector, the interruption is generated again thereafter, and the interruption processing program is executed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a parallel processing apparatus that performs processing in parallel by switching and executing a plurality of programs. In particular, the present invention relates to a parallel processing apparatus that executes a program that causes a computer to function as a parallel processing apparatus as one of a plurality of programs managed by the parallel processing apparatus.

2. Description of the Related Art Conventionally, there is a technique for operating a plurality of multitasking OSs (hereinafter simply referred to as “OSs”) in parallel on a computer having a single CPU (Central Processing Unit).
For example, there is a multi-OS system in which two OSs coexist by operating one guest OS as a host OS, the other OS as a guest OS, and the guest OS as a task on the host OS.
In a multi-OS system, when an interrupt from hardware occurs, the interrupt cannot be processed correctly unless the OS that manages the task that should handle the interrupt is operating.
Therefore, for example, the host OS determines the OS that should process the interrupt, and if the guest OS is an interrupt that should be processed, a flag indicating that there was an interrupt is set, and then the guest When switching to the OS, the guest OS checks the flag and calls an interrupt handler of the guest OS (for example, Non-Patent Document 1).

In addition, the OS switching program realizes an OS switching function, an interrupt distribution function, an inter-OS communication function, etc. under the management of the OS switching program without providing a relationship between the host OS and the guest OS. There is also a multi-OS system in which a plurality of OSs coexist (for example, Patent Document 1).
JP 2001-282558 A US Pat. No. 5,995,745

In a multi-OS system provided with a host OS and a guest OS, if each OS sets an interrupt mask individually, inconsistency occurs in the priority of interrupt processing, and interrupts that must be processed preferentially are masked. There is a problem such as end.
In addition, when an OS is to be operated in a multi-OS system in which the OS switching program manages the OS, the OS switching program needs to emulate hardware, resulting in a processing overhead.
Further, when the OS switching program does not emulate hardware, the existing OS cannot be operated as it is, and there is a problem that significant correction is required.

  The present invention has been made to solve the above-described problems, for example, and in a multi-OS system provided with a host OS and a guest OS, interrupt processing can be performed without contradiction, and an existing OS The purpose is to make it possible to use it with a slight modification.

The parallel processing device according to the present invention is:
A guest parallel processing program that manages a plurality of programs as guest tasks, and switches and executes the guest tasks, thereby causing the computer to function as a guest parallel processing device that processes the plurality of programs in parallel, and other programs In a parallel processing device that processes the plurality of programs and the other programs in parallel by managing the host tasks and switching and executing the host tasks,
An execution device for executing the program;
A storage device for storing information;
Interrupts the execution of the program being executed by the execution device and outputs an interrupt signal to the execution device that requests the execution device to execute an interrupt processing program for processing an interrupt. An interrupt signal input device;
Based on a request by an interrupt signal input by the interrupt signal input device, an interrupt vector storage unit that stores information indicating a program executed by the execution device as an interrupt vector using the storage device;
A task selection unit for selecting a host task to be executed by the execution device from the host tasks;
Different interrupt vectors are stored in the interrupt vector when the host task selected by the task selection unit is the other program and when the host task selected by the task selection unit is the guest parallel processing program. Interrupt vector rewriting part to be stored in the part,
It is characterized by having.

  According to the present invention, for example, different interrupt vectors are stored in the interrupt vector storage unit during execution of the guest parallel processing program (guest OS) and in other cases, so that the OS to process the interrupts Even when an interrupt is generated while an OS different from that is executed, the interrupt process is not executed under the different OS, and the confusion of the process due to the occurrence of the interrupt can be avoided. Play.

Embodiment 1 FIG.
The first embodiment will be described with reference to FIGS.
FIG. 1 is a hardware configuration diagram illustrating an example of a hardware configuration of a parallel processing device 900 according to this embodiment.
The parallel processing device 900 includes an execution device 901, a storage device 902, an input device 903, an output device 904, an interrupt signal input device 905, and a clock device 906.

The execution device 901 is, for example, a CPU (Central Processing Unit).
The execution device 901 executes a program stored in the storage device 902 and realizes each functional block described below.
Note that each functional block described below may be realized by hardware or firmware.

The storage device 902 is, for example, an internal storage device such as a ROM (Read Only Memory) or a RAM (Random Access Memory), or an external storage device such as a hard disk device or an SD (Sequential Digital) memory.
In addition to the program executed by the execution device 901, the storage device 902 stores information input from the input device 903, information processed by the execution device 901, information output by the output device 904, and the like.

The input device 903 is, for example, an operation input device such as a keyboard or a mouse, a voice input device such as a microphone, or an image input device such as a scanner or a camera.
The input device 903 inputs various information.
The input device 903 may be, for example, an interface device that is connected to another device, and may be a device that inputs information from another device.

The output device 904 is, for example, an image display device such as a CRT (Cathode Ray Tube) device, an audio output device such as a speaker, or an image printing device such as a printer.
The output device 904 outputs various information.
The output device 904 may be, for example, an interface device that is connected to another device, and may be a device that outputs information to another device.

  The timepiece device 906 is configured from, for example, an oscillation circuit and a counter, and is a device that measures the current time or the elapsed time since receiving a reset signal.

The interrupt signal input device 905 detects that the storage device 902, the input device 903, the output device 904, and the clock device 906 are in a predetermined state, and outputs an interrupt signal to the execution device 901. .
For example, when the input device 903 receives an input from the operator, the output device 904 completes printing of an image, or the time measured by the clock device 906 reaches a predetermined time, an interrupt signal is output. To do.
Note that the interrupt signal input device 905 may be a part of the CPU that is the execution device 901.

FIG. 2 is a conceptual diagram showing an example of the relationship of programs (tasks) executed in the parallel processing device 900 in this embodiment.
The programs executed in the parallel processing device 900 include a host OS 100 (Operating System), a guest OS 200, a task 106 on the host OS, an OS switching task 107, a task 206 on the guest OS, and the like.

The host OS 100 selects a program to be executed from among the programs processed by the parallel processing device 900 and causes the execution device 901 to execute the program. In addition, when the program being executed is interrupted and another program is executed, necessary information (context) is saved so that the program being executed can be resumed later, and restored when the execution is resumed.
The host OS 100 is an example of a parallel processing program.

  The host OS 100 is composed of a plurality of programs. The host OS 100 has programs for performing a scheduler 101, an interrupt process 103, a mask setting process 104, an inter-OS synchronization process 105, and the like, and stores an interrupt vector 102, a mask table 108, and the like using a storage device 902. .

The scheduler 101 is a program that performs processing such as scheduling of the host task 110 (guest OS 200, task 106 on the host OS, OS switching task 107, etc.).
The interrupt processing 103 is a program that is executed by the interrupt signal output from the interrupt signal input device 905 and performs processing corresponding to each interrupt cause.
The interrupt vector 102 is information indicating the interrupt process 103 executed by the interrupt signal output from the interrupt signal input device 905 (for example, an address of a memory (storage device 902) storing the interrupt process 103). .
The mask setting process 104 is a program that sets an interrupt mask for restricting the execution of the interrupt process 103 so that the interrupt process with a low priority is not executed during the execution of a process with a high priority.
The mask table 108 is information on the interrupt mask set in the mask setting process 104.
The inter-OS synchronization processing 105 is a program that processes a message notified from the host task 110 to the guest task 210 (task 206 on the guest OS).

The task 106 on the host OS is a program managed by the host OS 100 and is a program processed in parallel in the parallel processing device 900.
The task 106 on the host OS is an example of another program.

The OS switching task 107 is used when the interrupt processing corresponding to the interrupt signal output from the interrupt signal input device 905 is on the host OS 100 when the execution device 901 is executing the guest task 210. , A program for switching the OS from the guest OS to the host OS.
The OS switching task 107 is an example of another program.

Similar to the host OS 100, the guest OS 200 is a program that selects a program to be executed from a plurality of programs and causes the execution device 901 to execute the program. The difference from the host OS 100 is that the guest task 210 is managed among the programs processed by the parallel processing device 900, and other programs (for example, the task 106 on the host OS, the OS switching task, etc.) are not managed. is there. Another difference is that the guest OS 200 itself is one of the host tasks 110 that are managed by the host OS 100.
The guest OS 200 is an example of a guest parallel processing program.

  The guest OS 200 is composed of a plurality of programs. The guest OS 200 has programs for performing a scheduler 201, an interrupt process 203, a mask setting process 204, an inter-OS synchronization process 205, and the like, and stores an interrupt vector 202 and the like using a storage device 902.

The scheduler 201 is a program that performs processing such as scheduling of the guest task 210.
The interrupt processing 203 is a program that is executed by the interrupt signal output from the interrupt signal input device 905 and performs processing corresponding to each interrupt cause.
The interrupt vector 202 is information indicating an interrupt process 203 executed by the interrupt signal output from the interrupt signal input device 905 (for example, an address of a memory (storage device 902) storing the interrupt process 203). .
The mask setting process 204 is a program that sets an interrupt mask for restricting the execution of the interrupt process 203 so that the interrupt process with a low priority is not executed during the execution of a process with a high priority.
The inter-OS synchronization process 205 is a program that processes a message notified from the host task 110 to the guest task 210.

The task 206 on the guest OS is a program managed by the guest OS 200, and is a program processed in parallel in the parallel processing device 900.
The task 206 on the guest OS is an example of a plurality of programs.

FIG. 3 is a block configuration diagram illustrating an example of a functional block configuration of the parallel processing device 900 according to this embodiment.
The parallel processing device 900 includes an interrupt processing unit 310, a dispatch unit 320, a schedule unit 330, a priority storage unit 391, a context storage unit 392, and the like.

The interrupt processing unit 310 causes the execution device 901 to execute the corresponding interrupt processing 103 and 203 based on the interrupt signal output from the interrupt signal input device 905.
The interrupt processing unit 310 is realized by CPU hardware, for example, but may be realized by other methods.
The interrupt processing unit 310 includes an interrupt vector storage unit 311, an interrupt mask storage unit 312, and an interrupt processing execution unit 313.

  The interrupt vector storage unit 311 stores the interrupt vector 102 or the interrupt vector 202. The interrupt vector storage unit 311 is, for example, a memory (storage device 902) having a predetermined address, and a memory (storage device 902) that stores interrupt processing 103 and 203 at an address corresponding to the number of the interrupt signal. The start address of is stored.

The interrupt mask storage unit 312 stores an interrupt mask. The interrupt mask storage unit 312 is, for example, an interrupt mask register of the CPU, and stores information indicating an interrupt signal permitting interrupt processing as an interrupt mask.
The interrupt mask has, for example, the same number of bits (interrupt mask pattern) as the type of interrupt signal, and by taking the logical product with the interrupt signal, only the interrupt signal that permits interrupt processing is obtained. Extract.
Also, for example, the interrupt mask is an integer value (interrupt mask level) indicating the interrupt level, and the interrupt signal level is lower when the interrupt signal level is compared with the interrupt mask value. In some cases, interrupt processing may not be permitted.

When the interrupt signal input device 905 outputs an interrupt signal permitted by the interrupt mask stored in the interrupt mask storage unit 312, the interrupt processing execution unit 313 executes a program executed by the execution device 901. The execution is interrupted, and the execution device 901 is caused to execute the interrupt processing 103 and 203 indicated by the interrupt vector stored in the interrupt vector storage unit 311.
For example, the current PC (Program Counter) value is saved in the stack, and the interrupt vector value corresponding to the interrupt signal is read into the PC.

The dispatch unit 320 (also referred to as a dispatcher) executes the host task 110 so that the host task 110 executed so far can be resumed later when the host task 110 executed by the execution device 901 is switched (when the task is switched). Information (PC value, register value, stack and temporary variable value stored in the memory (storage device 902), etc., hereinafter referred to as “context”) is stored in the context storage unit 392. When resuming the suspended host task 110, the dispatch unit 320 reads and restores the context stored in the context storage unit 392 so that the continuation before the suspension can be executed.
The dispatch unit 320 is realized by the execution device 901 executing the scheduler 101.

The dispatch unit 320 includes a context rewriting unit 321, an interrupt vector rewriting unit 323, a mask setting unit 324, and the like.
The context rewriting unit 321 stores the context of the host task 110 whose execution is interrupted in the context storage unit 392 and restores the context of the host task 110 whose execution is resumed from the context storage unit 392.

The interrupt vector rewriting unit 323 stores the interrupt vector stored in the interrupt vector storage unit 311 in the context storage unit 392 and restores it when the OS is switched.
Here, “when OS is switched”, among the host tasks 110, the execution of the guest OS 200 is interrupted and the other host tasks 110 (the task 106 on the host OS, the task 107 for OS switching, etc.) are executed. In other words, conversely, the execution of the guest OS 200 is executed by interrupting the execution of other host tasks 110 (the task 106 on the host OS, the OS switching task 107, etc.).
Since each OS manages the interrupt processes 103 and 203, it is necessary to rewrite the interrupt vector stored in the interrupt vector storage unit 311 when switching the OS. Therefore, the interrupt vector rewriting unit 323 saves and restores the interrupt vector stored in the interrupt vector storage unit 311 as the OS context.

The mask setting unit 324 stores and restores the interrupt mask stored in the interrupt mask storage unit 312 in the context storage unit 392 when switching tasks (mask setting process 104).
In this embodiment, the interrupt mask is also saved and restored as part of the task context at the time of task switching.

  The context storage unit 392 uses the storage device 902 to store the context and the interrupt mask for each host task 110. Further, the context storage unit 392 stores an interrupt vector for each OS using the storage device 902.

The priority storage unit 391 stores the priority of the host task 110 using the storage device 902.
“Priority” is information indicating the priority of executing the host task 110. When there are a plurality of host tasks 110 in an executable state, the host task 110 having the highest priority determined based on the priority is executed as a reference for determining which host task 110 is to be executed.

The scheduling unit 330 (also referred to as a scheduler) selects the host task 110 to be executed by the execution device 901 based on the priority stored in the priority storage unit 391.
The schedule unit 330 is realized by the execution device 901 executing the scheduler 101.

  The schedule unit 330 includes an executable determination unit 331, a task selection unit 332, a mask table generation unit 333, a mask table storage unit 334, and the like.

The executable determination unit 331 determines whether the host task 110 is in an executable state.
The “executable state” means that the host task 110 is ready to be executed as soon as all information and resources necessary for executing the task are available and the execution device 901 is available. .
On the other hand, “not ready for execution” means that the host task 110 uses the execution device 901 due to, for example, waiting for input, waiting for output completion, timing adjustment, waiting for processing results of other tasks, or lack of memory. Even if it is possible, it means that it cannot be executed immediately.

  The task selection unit 332 calculates priority based on the priority stored in the priority storage unit 391 for the host task 110 determined to be in an executable state by the executable determination unit 331, and has the highest priority. Select a higher host task 110.

The mask table generation unit 333 generates the mask table 108 based on the priority stored in the priority storage unit 391 and stores it in the mask table storage unit 334.
The mask table storage unit 334 stores the mask table 108 generated by the mask table generation unit 333.

Since the interrupt processes 103 and 203 are executed when the interrupt signal input device 905 outputs an interrupt signal in principle, they are executed outside the management of the schedule unit 330 and the dispatch unit 320, and the concept of priority order is used. Absent.
However, since it is necessary to prevent interrupt processing for interrupts with low urgency during execution of processing with high urgency, the interrupt mask prevents the occurrence of interrupt processing with low urgency. .
Therefore, it can be considered that an interrupt process whose interrupt process is prohibited by the interrupt mask has a lower priority than the host task 110 that sets the interrupt mask.

FIG. 4 is a conceptual diagram showing an example of task priorities in this embodiment.
Interrupt processing tasks 111 to 115 are interrupt processing 103 executed when the interrupt signal input device 905 outputs an interrupt signal. The interrupt processing tasks 111 to 115 are not managed by the scheduling unit 330 and are not “tasks” in a strict sense, but here, priority is considered between the normal task and the interrupt mask. Therefore, it is treated as a kind of host task 110.

The normal processing tasks 121 to 125 are tasks 106 on the host OS and perform normal processing.
The normal processing tasks 121 to 125 have priorities determined on the basis of the priorities stored in the priority storage unit 391. In this figure, the priorities are described as having higher priorities.

  Some of the normal processing tasks 121 to 125 wait for the processing results of the interrupt processing tasks 111 to 115. For example, the normal processing task 121 may not be executable after waiting for the processing result of the interrupt processing task 111. Similarly, the normal processing tasks 122, 123, and 125 wait for the processing results of the interrupt processing tasks 112, 113, and 115, respectively. The normal processing task 124 is a task that does not wait for the processing result of the interrupt processing task.

Since the normal processing task 121 has a higher priority than the normal processing task 122, the task selection unit 332 is in a state where the normal processing task 122 can be executed while the normal processing task 121 is in an executable state. Selects the normal processing task 121 and does not execute the normal processing task 122.
That is, even if the processing of the interrupt processing task 112 for which the normal processing task 122 is waiting for the processing result is completed and the normal processing task 122 becomes executable, the normal processing task 121 is not in an executable state. Until you wait.
Therefore, it is not necessary to immediately execute the interrupt processing task 112 when an interrupt occurs, and it is possible to wait until the normal processing task 121 ends.
Therefore, while the normal processing task 121 is being executed, an interrupt mask is set so that execution of the interrupt processing task 112 is not permitted, so that execution of the normal processing task 121 having a higher priority is not interrupted.
That is, the priority order of the interrupt processing task 112 can be considered to be between the normal processing task 121 and the normal processing task 122.

  As described above, if the priority of each task and the interrupt process that each task waits for are known, an interrupt mask to be set during execution of each task can be calculated.

  In this way, the mask table generation unit 333 generates an interrupt mask for each host task 110.

  The guest OS 200 has priority as one of the host tasks 110. In this example, the priority of the guest OS 200 is set and stored in the priority storage unit 391 on the assumption that the priority is lower than that of the normal processing task 122 and higher than that of the normal processing task 123.

  The OS switching task 107 sets a higher priority than the guest OS 200. It is preferable that there is no host task 110 having a priority between the OS switching task 107 and the guest OS 200.

  The guest task 210 managed by the guest OS 200 includes, for example, interrupt processing tasks 211 to 212, normal processing tasks 221 to 223, and the like. These tasks also have priorities in the management of the guest OS 200. Alternatively, task management in the guest OS 200 may not be based on priority.

  Here, considering the priority order of the host task 110 and the guest task 210 as a whole, the guest OS 200 itself is one of the host tasks 110 managed by the host OS 100. Therefore, the priority order of the guest task 210 as a whole is the guest OS 200. It does not become higher than the OS switching task 107 with higher priority, and does not become lower than the interrupt processing task 113 with lower priority than the guest OS 200.

  Even in the guest task 210 managed by the guest OS 200, the normal processing tasks 221 to 223 may wait for the processing results of the interrupt processing tasks 211 to 212. Therefore, the guest OS 200 may also manage the interrupt processing tasks 211 to 212 and set an interrupt mask.

FIG. 5 is a conceptual diagram showing an example of the relationship between the priority order of the host task 110 and the interrupt priority order in this embodiment.
The priority order of the normal processing tasks is determined by the priority stored in the priority storage unit 391.
The priority order of interrupt processing tasks is determined by the priority order of normal processing tasks waiting for the processing result of each interrupt processing task.

The scheduling unit 330 performs priority control of normal processing tasks.
The priority control of the interrupt processing task is performed by setting an interrupt mask in the interrupt mask storage unit 312.

The mask table generation unit 333 of the scheduler 101 sets the interrupt mask level and task priority according to this relationship when the host task 110 is activated.
The guest OS 200 has a priority Tg.
The interrupt processing task processed by the guest OS 200 has interrupt priorities Ix + 1 to Iy.
The host task 110 executed with a higher priority than the guest OS 200 has a priority of Tg + 1 or higher.
When executing a host task 110 having a priority level Tg + 1 or higher, an interrupt process with a priority level Iy or lower is masked.
Further, in the guest OS 200, when interrupts are masked so that the processing of the guest task 210 does not conflict with the interrupt processing, interrupts having an interrupt priority level Iy or less are masked.

  Here, since priority control of the guest task 210 is performed by the guest OS 200, the host OS 100 is not concerned. However, even when a host task 110 other than the guest OS 200 is being executed, an interrupt signal to be processed by the guest OS 200 may be generated, and therefore it is necessary to control the interrupt task using an interrupt mask.

However, the interrupt control by the guest OS 200 is limited to those related to the interrupt to be processed by the guest OS 200.
Of the interrupts to be processed by the host OS 100, interrupts having a higher priority than the guest OS 200 are always permitted during execution of the guest OS 200. When this is viewed from the guest OS 200, such an interrupt is the same as NMI (No Maskable Interrupt) and is not a control target of the guest OS 200.
Of the interrupts to be processed by the host OS 100, interrupts having a lower priority than the guest OS 200 are always prohibited during execution of the guest OS 200. Seeing this from the guest OS 200, it is the same as not having such an interrupt.

  Therefore, the guest OS 200 need only control the interrupts to be processed by the guest OS 200, and does not need to consider the interrupts to be processed by the host OS 100.

FIG. 6 is a diagram showing an example of the contents of the mask table 108 generated by the mask table generation unit 333 and stored in the mask table storage unit 334 in this embodiment.
The mask table 108 is a table having a task priority 611 and an interrupt mask level 612.
The task priority 611 is the priority of each task. If the task priority stored in the priority storage unit 391 is the same, the interrupt mask level is also the same, so the interrupt mask level is stored for each task priority, not for each host task 110. Note that it may be stored for each host task 110.
The interrupt mask level 612 is an interrupt mask set in the interrupt mask storage unit 312 when executing the host task 110 having the task priority 611.
For example, when executing the host task 110 with the task priority Tm, the interrupt mask Mn is set in the interrupt mask storage unit 312. The interrupt mask Mn indicates an interrupt mask that masks all interrupts having an interrupt priority level In or lower in FIG.
When executing the host task 110 (guest OS 200) with the task priority Tg, an interrupt mask My that masks interrupts with an interrupt priority level Ix or lower and permits interrupts with an interrupt priority level Ix + 1 or higher. Is set in the interrupt mask storage unit 312.

FIG. 7 is a diagram showing an example of an interrupt vector stored in the interrupt vector storage unit 311 in this embodiment.
The interrupt vector stored in the interrupt vector storage unit 311 is stored in the interrupt vector 102 or the interrupt vector 202 by being rewritten by the interrupt vector rewriting unit 323 when the OS is switched.
When the execution device 901 executes the guest OS 200 (or the guest task 210 under the management) of the host tasks 110, the interrupt vector storage unit 311 stores the interrupt vector 202.
When the execution device 901 executes a host task 110 other than the guest OS 200, the interrupt vector storage unit 311 stores the interrupt vector 102.

The interrupt vector is information indicating an interrupt process executed in response to the interrupt signal. In this example, interrupt vectors corresponding to six types of interrupts 621 to 632 are stored.
Of the interrupts 621 to 632, the interrupts 621 to 624 are interrupts to be processed on the host OS 100. Also, interrupts 631 to 632 are interrupts to be processed on the guest OS 200.
In addition, the interrupts 621 to 632 have a higher priority in the order described above in the figure, and the priority is lowered as it goes down.

Of the interrupt vectors 102 when the execution device 901 executes a host task 110 other than the guest OS 200, the interrupt vectors 641 to 644 corresponding to the interrupts 621 to 624 to be processed by the host OS 100 are the respective interrupt vectors. 3 shows interrupt processing programs 661 to 664 for processing the error.
On the other hand, since the interrupts 631 to 632 to be processed by the guest OS 200 cannot be processed unless the guest OS 200 is executing, the interrupt vector 649 is not an interrupt processing program 671 to 672 for processing an interrupt, but a switching program. 669 is shown.

Of the interrupt vectors 202 when the execution device 901 is executing the guest OS 200, the interrupt vectors 651 to 652 corresponding to the interrupts 631 to 632 to be processed by the guest OS 200 are interrupt requests for processing the respective interrupts. The process program 671-672 is shown.
On the other hand, the interrupt vector 659 corresponding to the interrupts 621 to 622 to be processed by the host OS 100 indicates the switching program 679 instead of the interrupt processing programs 661 to 664 for processing the interrupt.
Note that when the execution device 901 is executing the guest OS 200, interrupts 623 to 624 having a low priority are not generated due to the interrupt mask. Therefore, in this example, the interrupt vector corresponding to the interrupts 623 to 624 is left blank. However, the interrupt vector corresponding to the interrupts 623 to 624 may also be set as the interrupt vector 659.

  Next, the operation will be described.

  FIG. 8 is a flowchart showing an example of a task activation process flow of the schedule unit 330 when the host task 110 is activated in this embodiment.

When the host OS 100 generates (starts up) the task 106 and the guest OS 200 on the host OS as the host task 110, the host OS 100 sets a priority and an interrupt mask to be used when executing the task.
In advance, the mask table generation unit 333 generates the mask table 108 and the mask table storage unit 334 stores the mask table 108.

  When the host OS 100 receives a task activation request, it starts task activation processing.

In S <b> 11, the schedule unit 330 calculates the priority of the host task 110 to be activated based on the priority stored in the priority storage unit 391.
Alternatively, the priority of the host task 110 may be designated when the task is activated, and the scheduling unit 330 may store the priority in the priority storage unit 391. In that case, the mask table generation unit 333 may regenerate the mask table 108 as necessary.

  In S12, the schedule unit 330 calculates an interrupt mask from the mask table 108 stored in the mask table storage unit 334 based on the priority calculated in S11.

  In S13, the context storage unit 392 secures a storage area for storing the context of the host task 110 to be activated.

  In S14, the context storage unit 392 stores the interrupt mask calculated in S12 in the storage area secured in S13.

  In S15, the executable determination unit 331 registers the host task 110 to be activated in the executable task list. In addition, processing that is performed when other normal tasks are started is performed.

Actually, when the task selection unit 332 selects the host task 110 and the execution device 901 executes the host task 110, the dispatch unit 320 restores the context. Since the context of the task stored in the context storage unit 392 includes the interrupt mask stored in S <b> 14, the mask setting unit 324 stores the interrupt mask in the interrupt mask storage unit 312.
Therefore, while the host task 110 is being executed, an interrupt mask that prohibits interrupt processing having a lower priority than the host task 110 is set in the interrupt mask storage unit 312.

Here, during execution of the host task 110 having a higher priority (eg, priority Tz) than the guest OS 200 (priority Tg in FIG. 5), the interrupt processing (interrupt priority) to be processed by the guest OS 200 Since the interrupt mask Mz prohibiting the degree Ix + 1 to Iy) is set in the interrupt mask storage unit 312, there is no interrupt to be processed by the guest OS 200.
Therefore, the execution of the host task 110 having a higher priority than the guest OS 200 is not affected by the interrupt process to be processed by the guest OS.

In addition, when changing the interrupt mask in the guest OS 200, interrupts with interrupt priority higher than Iy are always permitted, and interrupts with interrupt priority lower than Ix + 1 are always prohibited. The masks Mx to My are used.
Thereby, even if the guest OS 200 changes the interrupt mask, an interrupt process having a higher priority than the guest OS 200 is not prohibited.

FIG. 9 is a flowchart showing an example of the flow of schedule processing of the schedule unit 330 in this embodiment.
The schedule unit 330 selects the host task 110 having the highest priority from the host tasks 110 in an executable state.

In S21 (executable determination step), the executable determination unit 331 determines the host task 110 in an executable state from the executable task list.
In the executable task list, the activated host tasks 110 are registered, and whether each host task 110 is in an executable state is stored. The executable task list is stored by the executable determination unit 331 using the storage device 902.

  In S22, the task selection unit 332 calculates a priority order for the host task 110 that is determined to be executable by the executable determination unit 331 in S21 based on the priority stored in the priority storage unit 391. .

  In S23 (task selection step), the task selection unit 332 selects the host task 110 having the highest priority calculated in S22.

  In S24, the dispatch unit 320 performs a task switching process. That is, the context of the host task 110 being executed is stored in the context storage unit 392, and the context of the task selected by the task selection unit 332 in S23 is restored from the context storage unit 392.

  In S25, the execution device 901 executes the host task 110 selected by the task selection unit 332 in S23.

  Thereafter, when the running host task 110 is interrupted due to termination or sleep (not in an executable state), the process returns to S21.

FIG. 10 is a flowchart showing an example of the task switching processing flow of the dispatch unit 320 in this embodiment.
This details the contents of the task switching process (S24) in the schedule process.

  In S31, the context storage unit 392 stores the context of the host task 110 being executed (save context). This context also includes the interrupt mask set when the host task 110 is executed.

In S32, the interrupt vector rewriting unit 323 determines whether or not OS switching occurs.
If there is OS switching in S33, the process proceeds to S34. If there is no OS switching, the process proceeds to S37.

In S <b> 34, the dispatch unit 320 prohibits the interrupt so that no interrupt occurs during the rewriting of the interrupt vector.
Note that “interrupt prohibited” here is not prohibited by an interrupt mask, but prohibits all interrupts. For example, the execution device 901 executes an interrupt prohibition instruction.

  In S35, the interrupt vector rewriting unit 323 reads the interrupt vector stored in the interrupt vector storage unit 311 and the context storage unit 392 stores it as the OS context (saving the interrupt vector).

  In S36 (interrupt vector rewriting process), the interrupt vector rewriting unit 323 reads the context of the switching destination OS stored in the context storage unit 392, and the interrupt vector storage unit 311 stores it (restores the interrupt vector). .

  In S <b> 37, the context rewriting unit 321 reads the context of the switching destination host task 110 stored in the context storage unit 392 and restores it. The mask setting unit 324 restores the interrupt mask (context restore).

  In S38, the dispatch unit 320 cancels the prohibition of interrupt. For example, the execution device 901 executes an interrupt prohibition release command.

  Note that the context storage unit 392 stores the interrupt vector not as an OS context but as a task context for each task (all interrupt vectors of the host task 110 other than the guest OS 200 are the same). It is not necessary to determine whether there is OS switching when switching tasks.

  FIG. 11 is a flowchart showing an example of the flow of interrupt processing of the interrupt processing unit 310 when an interrupt signal is input in this embodiment.

  In S <b> 41, the interrupt process execution unit 313 detects the interrupt signal output by the interrupt signal input device 905.

  In S <b> 42, the interrupt process execution unit 313 determines whether the interrupt process corresponding to the interrupt signal is permitted or prohibited based on the interrupt mask stored in the interrupt mask storage unit 312.

  If permitted in S43, the process proceeds to S44. If it is prohibited, the process is terminated.

  In S44, the interrupt process execution unit 313 prohibits interrupts (blocks of interrupts) so that the same interrupts do not occur repeatedly.

  In S45, the execution device 901 executes the program indicated by the interrupt vector stored in the interrupt vector storage unit 311.

  Next, processing contents of the program executed in S45 will be described.

  FIG. 12 is a flowchart showing an example of the interrupt processing flow of the interrupt processing programs 661 to 664 executed when an interrupt signal is input in this embodiment.

  The interrupt processing programs 661 to 664 are programs for processing interrupts to be processed by the host OS 100, and are under the management of the host OS 100.

  In S51, the interrupt signal input device 905 stops outputting the interrupt signal. For example, the execution device 901 executes an interrupt stop instruction and notifies the interrupt signal input device 905 of the start of the interrupt process (interrupt acknowledge). Receiving this, the interrupt signal input device 905 stops outputting the interrupt signal.

If the interrupt process cannot be started because the interrupt is masked or prohibited, if the interrupt signal output is stopped immediately, the interrupt process cannot be performed, causing a problem. Therefore, the interrupt signal input device 905 continues to output the interrupt signal until it is confirmed that the interrupt process has started (assertion of the interrupt signal).
Therefore, it is necessary to notify the interrupt signal input device 905 that the interrupt processing has started and stop the interrupt signal.

In S52, the execution device 901 releases the prohibition of interrupt. Since the interrupt signal input device 905 stops outputting the interrupt signal, there is no need to worry about the same interrupt being duplicated, and if an interrupt with a higher priority occurs, the interrupt can be processed. It is for doing so.
Since the interrupt mask remains unchanged, even if the interrupt prohibition is canceled, an interrupt with a low priority does not occur.

  In S53, the execution device 901 performs processing corresponding to each interrupt.

In S54, the normal processing task waiting for the result of the interrupt processing is woken up (task wakeup).
The normal processing task waiting for the result of the interrupt processing is the host task 110 that cannot be executed without the result of the interrupt processing. Since the executable determination unit 331 registers the host task 110 in the executable task list as not being in an executable state, the host task 110 is rewritten to be in an executable state.

  After completion of the interrupt process, the executable determination unit 331 determines that the normal process task waiting for the result of the interrupt process can be executed (S21). If there is no high host task 110, the task selection unit 332 selects the task (S23), and the task is switched (S24).

  Note that the processing flow of the interrupt processing programs 671 to 672 under the management of the guest OS 200 is the same as that described above, and a description thereof will be omitted here. However, the normal processing task that the interrupt processing program 671 to 672 under the management of the guest OS 200 wakes up is the guest task 210 under the management of the guest OS 200. The executable determination unit 331 or the like is not involved.

FIG. 13 is a flowchart showing an example of the flow of OS switching processing of the switching program 669 executed when an interrupt signal is input in this embodiment.
The switching program 669 is executed when an interrupt to be processed by the guest OS 200 occurs while the execution device 901 executes the host task 110 other than the guest OS 200.

In S61, the switching program 669 wakes up the guest OS 200.
That is, the executable determination unit 331 registers the guest OS 200 in the executable task list as being executable.

While the host task 110 having a higher priority than the guest OS 200 is being executed, an interrupt to be processed by the guest OS 200 is prohibited because of the interrupt mask, and thus does not occur.
Therefore, the switching program 669 is executed when the host task 110 having a lower priority than the guest OS 200 is executed (or when the host OS 100 is in an idle state).

  Therefore, after the interrupt process is completed, the guest OS 200 becomes the host task 110 having the highest priority among the executable host tasks 110, and the task is switched (S24).

Since there is OS switching in the task switching process (S33), the interrupt vector is rewritten to that of the guest OS 200 (S36). Further, the context at the time of executing the guest OS 200 is restored (S37).
Thereafter, the prohibition of interrupt is released (S38).

  At this time, the interrupt signal input device 905 has not stopped outputting the interrupt signal (the processing corresponding to S51 is not performed), so that the interrupt occurs again.

  Although the interrupt signal itself is the same, but the interrupt vector is rewritten, the program to be executed is not the switching program 669 but the interrupt processing programs 671 to 672. Further, since the context at the time of execution of the guest OS 200 is restored, the interrupt process is performed without any trouble.

  Further, when the interrupt mask is rewritten in the guest OS 200, the interrupt mask is restored (S37), and then the prohibition of interrupt is released (S38). If is an interrupt to be masked, the interrupt process is not started.

  Therefore, in any case, the operation as expected by the guest OS 200 is guaranteed.

FIG. 14 is a flowchart showing an example of the flow of OS switching processing of the switching program 679 when an interrupt signal is input in this embodiment.
The switching program 679 is executed when an interrupt to be processed by the host OS 100 occurs while the execution device 901 is executing the guest OS 200.

In S71, the switching program 679 wakes up the OS switching task 107.
That is, the executable determination unit 331 registers the OS switching task 107 in the executable task list as being executable.
Here, since the switching program 679 is under the management of the guest OS 200, the guest task 210 can be woken up, but the OS switching task 107, which is the host task 110, cannot be woken up directly.
However, since the guest OS 200 itself is one of the host tasks 110 under the management of the host OS 100, the OS switching task 107 can be woken up from the guest OS 200.

While the guest OS 200 is being executed, among the interrupts to be processed by the host OS 100, interrupts having a lower priority than the guest OS 200 are prohibited because they are prohibited by the interrupt mask.
Therefore, the switching program 679 is executed only when an interrupt having a higher priority than the guest OS 200 occurs among interrupts to be processed by the host OS 100.

  Further, since the guest OS 200 is being executed, none of the host tasks 110 having higher priority than the guest OS 200 are in an executable state.

  Since the OS switching task 107 has a higher priority than the guest OS 200, the host having the highest priority among the host tasks 110 that can be executed by the OS switching task 107 after the interruption process is completed. Task 110 is reached and the task is switched (S24).

Since there is OS switching in the task switching process (S33), the interrupt vector is rewritten to that of the host OS 100 (S36).
Thereafter, the interrupt prohibition is released. (S38).

  At this time, the interrupt signal input device 905 has not stopped outputting the interrupt signal (the processing corresponding to S51 is not performed), so that the interrupt occurs again.

  Although the interrupt signal itself is the same, the interrupt vector is rewritten, so the program to be executed is not the switching program 679 but the interrupt processing programs 661 to 662. Therefore, the interruption process is performed without any trouble.

In addition, even if the interrupt mask is rewritten in the guest OS 200, interrupts having higher priority than the guest OS 200 among interrupts to be processed by the host OS 100 are not controlled, and interrupts with higher priority are selected. Since the interrupt mask is rewritten only within the permitted range, interrupt processing with a high priority is performed without any trouble.
On the other hand, in the guest OS 200, among the interrupts to be processed by the host OS 100, interrupts having a lower priority than the guest OS 200 are not controlled, and only interrupts within a range in which interrupts having a lower priority are prohibited. Since the interrupt mask is not rewritten, an interrupt with a low priority does not occur.

  Therefore, even if any interrupt signal is generated, the interrupt process can always be performed normally.

FIG. 15 is a flowchart showing an example of the OS switching processing flow of the OS switching task 107 in this embodiment.
The OS switching task 107 is a dummy for causing OS switching, and there is no content to be processed.

  The OS switching task 107 is activated simultaneously with the activation of the guest OS 200.

In step S76, the OS switching task 107 performs a sleep process (task sleep).
The sleep process is waiting for the occurrence of some event, so that a task that is not in an executable state is notified to the OS that the execution device 901 can execute another task.
The sleep process is an example of a process for notifying that the host task is not in an executable state.

Since the OS switching task 107 originally has no contents to be processed, the OS switching task 107 sleeps immediately after activation.
Thereafter, the user is woken up by the switching program 679. Since the OS switching task 107 has been woken up, OS switching has occurred and the purpose has already been achieved, so there is no content to be processed by the OS switching task 107.
Therefore, the process returns to S76, and the OS switching task 107 again sleeps.

FIG. 16 is a flowchart showing an example of a schedule process flow of the guest OS 200 in this embodiment.
Since the guest OS 200 uses the existing OS with slight modifications, many parts are the same as the existing OS.
Therefore, the guest OS 200 has the same block configuration as that of the existing existing OS, and can have various configurations.
Here, as an example, the guest OS 200 will be described as having the same block configuration as the host OS 100 described with reference to FIG.

In S81, the schedule part of the guest OS 200 determines whether or not the guest task 210 can be executed.
If there is an executable guest task 210 in S82, the process proceeds to S83. If there is no executable guest task 210, the process proceeds to S86.

  In S83, the schedule part of the guest OS 200 selects the guest task 210 to be executed from the executable guest tasks 210. As with the host OS 100, the selection method may be based on priority, or may be selected so that the execution times are equal.

  In S84, the dispatch unit of the guest OS 200 saves the context of the guest task 210 that has been executed so far, and restores the context of the selected guest task 210.

  In S85, the execution device 901 executes the selected guest task 210.

  After that, when the executed guest task 210 is interrupted due to termination or sleep, the process returns to S81.

In S86, the guest OS 200 performs a sleep process because there is no guest task 210 that can be executed.
That is, until one of the guest tasks 210 becomes executable, the host OS 100 is notified that the guest OS 200 itself is not in an executable state, so that the execution device 901 can execute another host task 110. .

  By this processing, the host task 110 having a lower priority than the guest OS 200 can also get an opportunity to execute.

  According to the parallel processing device in this embodiment, different interrupt vectors are stored in the interrupt vector storage unit 311 during execution of the guest OS 200 and in other cases. Even if an interrupt occurs while executing a different OS, the interrupt process is not executed under the different OS, and the confusion of the process due to the occurrence of the interrupt can be avoided. Play.

  According to the parallel processing device of this embodiment, when an interrupt occurs while executing an OS different from the OS that should process the interrupt, the OS switching process is performed, and then the interrupt occurs again. There is an effect that the OS that should process the interrupt can appropriately process the interrupt.

  According to the parallel processing device in this embodiment, when the guest OS 200 is not being executed and the interrupt to be processed by the guest OS 200 occurs, the guest OS 200 is woken up and the OS is switched. Originally, the effect that an interruption process can be performed is produced.

  According to the parallel processing device in this embodiment, when an interrupt to be processed by the host OS 100 occurs while the guest OS 200 is being executed, the execution of the guest OS 200 is interrupted and the OS is switched. Originally, the effect that an interruption process can be performed is produced.

  According to the parallel processing device of this embodiment, OS switching processing can be performed by simply starting the OS switching task 107, so that it should be added when the existing OS is used as the host OS 100 and the guest OS 200. There are few changes, the existing OS can be used effectively, and the development cost can be reduced.

  According to the parallel processing device in this embodiment, the interrupt signal input device 905 outputs an interrupt signal until the interrupt processing is started. Therefore, an interrupt is generated again after the OS switching processing, and the interrupt is interrupted. There is an effect that the interrupt processing program to be processed can be executed without any trouble.

  According to the parallel processing device in this embodiment, the switching programs 669 and 679 that are executed when an interrupt occurs while an OS different from the OS that should process the interrupt is not included in the interrupt stop instruction. Therefore, an interrupt occurs again after OS switching, and an interrupt processing program that should process the interrupt can be executed without any trouble.

  According to the parallel processing device of this embodiment, the host task 110 to be executed is selected based on the priority order of the host task 110. Therefore, if a task with a high priority can be executed, a task with a low priority is selected. It is not executed, and there is an effect that it is possible to postpone the execution of the interrupt process waiting for a task with a low priority.

  According to the parallel processing device of this embodiment, priority is given to the interrupt processing based on the priority of the task waiting for the result of the interrupt processing, and the interrupt is processed based on the priority of the interrupt processing. Since the mask control is performed, an interrupt having a low priority is not generated during execution of a process having a high priority, and an interrupt collision can be avoided.

  According to the parallel processing device in this embodiment, the interrupt control performed by the guest OS 200 does not affect the interrupt to be processed by the host OS 100, and therefore is added when the existing OS is used as the guest OS 200. There are few changes to be made, the existing OS can be used effectively, and the development cost can be reduced.

  According to the parallel processing device in this embodiment, since the guest OS 200 does not need to be aware of the interrupt to be processed by the host OS 100, there are few changes to be made when using the existing OS as the guest OS 200, and the existing OS The OS can be used effectively, and the development cost can be reduced.

  According to the parallel processing device in this embodiment, since the range of interrupts controlled by the guest OS 200 is limited, the interrupt control by the guest OS 200 and the interrupt control by the host OS 100 can coexist without contradiction. There is an effect.

  According to the parallel processing device in this embodiment, the interrupt mask to be processed by the guest OS 200 does not occur during execution of the host task 110 having a higher priority than the guest OS 200 due to the interrupt mask. In addition, there is an effect that there is no influence of an interrupt to be processed by the guest OS 200.

  According to the parallel processing device of this embodiment, due to the interrupt mask, interrupts having a lower priority than the guest OS 200 do not occur during execution of the guest OS 200, and the host OS 100 performs processing for the guest OS 200. There is an effect that there is no influence of an interrupt with a low priority.

  According to the parallel processing device of this embodiment, when there is no guest task 210 that can be executed on the guest OS 200, the guest OS 200 itself is in a dormant state. It has the effect of being given the opportunity.

  According to the parallel processing device in this embodiment, when there is no guest task 210 that can be executed on the guest OS 200, the guest OS 200 is notified that the guest OS 200 is not in an executable state. This is advantageous in that the host OS 100 can determine that is in a dormant state.

  According to the parallel processing device in this embodiment, the guest OS 200 is awakened when an interrupt to be processed by the guest OS 200 occurs while the guest OS 200 is sleeping, so that the interrupt can be appropriately processed. Play.

  According to the parallel processing method in this embodiment, different interrupt vectors are stored in the interrupt vector storage unit 311 during execution of the guest OS 200 and in other cases. Even if an interrupt occurs while executing a different OS, the interrupt process is not executed under the different OS, and the confusion of the process due to the occurrence of the interrupt can be avoided. Play.

  According to the parallel processing program in this embodiment, different interrupt vectors are stored in the interrupt vector storage unit 311 during execution of the guest OS 200 and in other cases. A parallel processing device capable of avoiding confusion in processing due to the occurrence of an interrupt, even if an interrupt occurs during execution of a different OS, without interrupt processing being performed under the different OS As 900, there is an effect that the computer can function.

  As described above, when there is no guest task 210 that can be executed by the scheduling unit of the guest OS 200 (when idle), the sleep processing on the host OS 100 is performed and an interrupt to be processed by the guest OS 200 is input. Since the guest OS 200 performs processing (wake-up) for the host OS 100 to wake up, the priority of the guest OS can be other than the lowest.

In addition, when interrupt masking is performed in the guest OS 200, the mask level is set to be equal to or lower than the priority of interrupts handled by the guest OS 200, so that the processing of the host task 110 having a higher priority is delayed by the interrupt mask. There is no.
In addition, during execution of the host task 110 with a higher priority than the guest OS 200, the interrupt processing with a lower priority is masked, so that the processing of the host task 110 with a higher priority is affected by the interrupt processing with a lower priority. Absent.

As a result, even when a real-time OS is used as the host OS 100 and a non-real-time OS is used as the guest OS 200, interrupt consistency can be maintained and the real-time property of the real-time OS can be ensured.
Further, even when the interrupt processing of the non-real-time OS does not consider the time constraint, since the consistency of the interrupt is maintained, the real-time property of the real-time OS can be ensured.

Further, when all the guest tasks 210 managed by the guest OS 200 are in an inexecutable state, the guest OS 200 performs a sleep process (sleep), so that the host task 110 having a lower priority than the guest OS 200 has an opportunity to execute it. Is given. Therefore, the guest OS 200 does not need to have the lowest priority.
As a result, the execution device 901 is occupied by the host task 110 and the processing for the interrupt to be processed by the guest task 210 cannot be executed. It is possible to avoid the occurrence of a failure such as an overflow or underflow of the buffer of the input / output device having the.

Embodiment 2. FIG.
The second embodiment will be described with reference to FIGS.
Since the hardware configuration of the parallel processing apparatus 900 in this embodiment is the same as that described in the first embodiment, the description thereof is omitted here.

FIG. 17 is a block configuration diagram showing an example of a functional block configuration of the parallel processing device 900 according to this embodiment.
In addition, about the block which is common in the functional block demonstrated in Embodiment 1, a common code | symbol is attached | subjected and description is abbreviate | omitted.

  The parallel processing device 900 includes an inter-task message processing unit 341, an inter-OS synchronization data storage unit 393, and the like.

The inter-task message processing unit 341 processes a message that the host task 110 notifies other tasks (the host task 110 or the guest task 210).
For example, when a certain host task 110 generates a message to be notified to another task, the inter-task message processing unit 341 acquires the message.
The inter-task message processing unit 341 rewrites the executable task list stored in the executable determination unit 331 when the host task 110 that is the notification destination of the message is sleeping due to waiting for the message. The host task 110 that has been waiting for the message is woken up by making it executable.
The inter-task message processing unit 341 is realized by the execution device 901 executing the inter-OS synchronization processing 105.

  When the notification task of the message is not the host task 110 but the guest task 210, the guest task 210 is under the management of the guest OS 200, and the executable determination unit 331 does not know whether it can be executed. Therefore, the inter-task message processing unit 341 cannot wake up the guest task 210 that is the notification destination directly.

  Therefore, the guest task 210 that is the notification destination is woken up indirectly using the inter-OS synchronization data.

The inter-OS synchronization data storage unit 393 uses the storage device 902 to store inter-OS synchronization data.
The inter-OS synchronization data storage unit 393 is an example of a notification destination storage unit.
The inter-OS synchronization data is data used to wake up a task under the management of a different OS.

FIG. 18 is a diagram showing an example of the data structure of the inter-OS synchronization data 400 stored in the inter-OS synchronization data storage unit 393 in this embodiment.
The inter-OS synchronization data 400 includes synchronization data 401 and a flag 402 on the guest OS. The inter-OS synchronization data 400 exists for each activated guest task 210 or for each guest task 210 waiting for a message notification. Therefore, when notifying a message to a certain guest task 210, the inter-OS synchronization data 400 corresponding to the guest task 210 that is the notification destination is used.

  The synchronization data 401 on the guest OS is a message exchanged between the guest tasks 210 in the guest OS 200.

The flag 402 indicates whether the guest task 210 is waiting for a message from the host task 110.
Since the guest task 210 waits for a message from the host task 110, the flag 402 is set when the guest task 210 enters a sleep state.
When a message is notified from the host task 110 and the guest task 210 becomes executable, the flag 402 is cleared.

When the guest task 210 exchanges messages, the guest OS 200 can grasp the notification destination of the message and wake up the guest task 210, so the flag 402 is not necessary.
However, when a message is notified from the host task 110 to the guest task 210, the flag 402 is used for the guest OS 200 to grasp the guest task 210 that is the notification destination.

  When the existing OS is modified and used as the guest OS 200, the data structure used by the existing OS for inter-task communication is modified and used as the inter-OS synchronization data 400. In this case, it is only necessary to make a correction to add the flag 402, so that a slight correction can be completed, and the existing OS can be used to the maximum, so that the development cost can be suppressed.

  Next, the operation will be described.

FIG. 19 is a flowchart showing an example of a flow of schedule processing of the guest OS 200 in this embodiment.
Note that steps common to the schedule processing steps of the guest OS 200 described in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

In T21, the schedule part of the guest OS 200 determines the reason why the guest task 210 executed in S85 interrupted execution.
If the reason why the guest task 210 is interrupted at T22 is waiting for a message from the host task 110, the process proceeds to T23. If not waiting for a message from the host task 110, the process returns to S81.

At T23, the schedule unit (inter-OS synchronization processing unit) of the guest OS 200 acquires the flag 402 for the guest task 210 waiting for a message from the inter-OS synchronization data 400 stored in the inter-OS synchronization data storage unit 393.
For example, the guest task 210 specifies the identifier of the OS synchronization data 400 used by the guest task 210, and the OS synchronization processing unit converts the OS synchronization data 400 identified by the specified identifier. The flag 402 is acquired by reading from the data storage unit 393.

  At T24, the schedule unit (inter-OS synchronization processing unit) of the guest OS 200 rewrites the flag 402 acquired at T23 to a content indicating that the host task 110 is in a sleep state waiting for a message from the host task 110, and for synchronization between OSs. The data is stored in the data storage unit 393.

At T25, the scheduling unit of the guest OS 200 stores the guest task 210 waiting for the message whose execution has been suspended in S85 as not being executable (sleeping state) (task sleep on the guest OS).
Thereafter, the process returns to S81.

  Thus, the host OS 100 can determine whether or not the guest task 210 is waiting for a message from the host task 110 by looking at the flag 402.

FIG. 20 is a flowchart showing an example of the flow of schedule processing of the schedule unit 330 in this embodiment.
In addition, about the process which is common with the process of the schedule process of the schedule part 330 demonstrated in Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted here.

In T11, the inter-task message processing unit 341 determines the notification destination of the message notified by the host task 110 executed in S25.
In T12, when the host task 110 executed in S25 has not sent a message to other tasks, the process returns to S21. When the host task 110 executed in S25 notifies the other host task 110 of a message, the process proceeds to T13. When the host task 110 executed in S25 notifies the guest task 210 of a message, the process proceeds to T15.

  In T13, the executable determination unit 331 determines whether or not the host task 110 that is the message notification destination is sleeping to wait for the message. When waiting for the message, the process proceeds to T14. If the user is not sleeping to wait for the message, the process returns to S21.

At T14, the executable determination unit 331 registers the host task 110, which is the message notification destination, in the executable task list as being ready for execution.
Thereafter, the process returns to S21.

At T15, the inter-task message processing unit 341 acquires the flag 402 for the guest task 210 that is the notification destination from the inter-OS synchronization data stored in the inter-OS synchronization data storage unit 393.
For example, the host task 110 designates the same identifier as the identifier of the inter-OS synchronization data 400 designated by the guest task 210 in T23, and the inter-task message processing unit 341 identifies the inter-OS synchronization identified by the designated identifier. The data 400 is read from the inter-OS synchronization data storage unit 393, and the flag 402 is acquired.

  At T16, the inter-task message processing unit 341 determines from the flag 402 acquired at T15 whether the notified guest task 210 is sleeping to wait for a message from the host task 110. When waiting for a message from the host task 110, the process proceeds to T17. If it is not sleeping to wait for a message from the host task 110, the process returns to S21.

  At T17, the inter-task message processing unit 341 rewrites the flag 402 acquired at T15 with the content indicating the wake-up request, and stores it in the inter-OS synchronization data storage unit 393.

At T18, the interrupt signal input device 905 outputs an interrupt signal, and the process returns to S21.
Here, the interrupt signal output from the interrupt signal input device 905 is a signal indicating that a message has been exchanged between tasks of different OSs.
For example, an output signal of a GPIO (General Purpose Input / Output: general-purpose input / output device) (output device 904) is connected to an interrupt signal input device 905 and output to GPIO is output.
Alternatively, a DMA (Direct Memory Access) controller that is not used for other purposes is used to transfer the minimum unit of data between memories (storage device 902), thereby outputting an interrupt signal that notifies the completion. May be.
Alternatively, the interrupt signal may be output by executing, for example, a SWI (Software Interrupt) instruction without using hardware.

This interrupt signal is for generating an interrupt to be processed by the guest OS 200. Therefore, the priority of this interrupt process is higher than that of the guest OS 200 and lower than that of the host task 110 having a higher priority than the guest OS 200.
Therefore, during the execution of the host task 110 having a higher priority than the guest OS 200, processing for this interrupt is not performed due to the interrupt mask. Thereby, useless OS switching or the like does not occur.

FIG. 21 is a flowchart showing an example of the flow of the inter-OS communication interrupt process of the interrupt processing program for processing the interrupt by the interrupt signal input at T18 in this embodiment.
An interrupt processing program that performs inter-OS communication interrupt processing is an interrupt processing program under the management of the guest OS 200.
Therefore, after this interrupt signal is input, the task switching process, the interrupt vector rewriting process, etc. described in the first embodiment occur. Thereafter, the inter-OS communication interrupt process starts.

  At T31, the schedule section (inter-OS synchronization processing section) of the guest OS 200 reads the inter-OS synchronization data 400 stored in the inter-OS synchronization data storage section 393, and the flag 402 indicating the wake-up request is set. The guest task 210 that is the message notification destination is determined.

  At T32, the schedule unit (inter-OS synchronization processing unit) of the guest OS 200 clears the flag 402 read out at T31 and stores it in the inter-OS synchronization data storage unit 393.

  At T33, the schedule unit of the guest OS 200 wakes up the guest task that is the message notification destination.

  As a result, the guest task 210 that is the notification destination to which the host task 110 has notified the message can be woken up.

In addition, since the guest task 210 to be notified is woken up by the interrupt process, even when the guest OS 200 is interrupted while the other guest task 210 is executing, when the execution of the guest OS 200 is resumed, When the priority of the notification destination guest task 210 is higher than the priority of the guest task 210 whose execution has been interrupted, the notification of the guest task 210 whose execution has been interrupted is not resumed. The execution of 210 can begin immediately.
In the schedule processing of the schedule unit 330, when the guest OS 200 resumes execution without generating an interrupt at T18 and only rewriting the inter-OS synchronization data storage unit 393 at T17, the guest task 210 that has suspended execution Resume execution. Since no interrupt occurs, even if the notification destination guest task 210 has a higher priority, the notification destination guest task 210 wakes up until the processing of the guest task 210 that has been suspended is completed. Not.
By generating an interrupt signal at T18, such processing delay can be prevented.

  According to the parallel processing device in this embodiment, when the host task 110 generates a message to be notified to the guest task 210, the interrupt signal input device 905 outputs an interrupt signal. There is an effect that the processing of the waiting guest task 210 is not delayed.

  According to the parallel processing device in this embodiment, the existing OS can be used as the inter-OS synchronization data 400 by slightly modifying the data structure that the existing OS has for inter-task communication. There are few correction points required when using as a guest OS 200, and the development cost can be suppressed.

  According to the parallel processing device in this embodiment, in the interrupt processing program of the guest OS 200 activated by the interrupt signal, the guest task 210 that is the message notification destination is determined based on the inter-OS synchronization data 400. Since the process is performed, the guest task 210 waiting for the message notification can be woken up.

  When the guest task 210 notifies the host task 110 of a message, since the guest OS 200 is one of the host tasks 110 under the control of the host OS 100, the guest OS 200 notifies the host OS 100 of the notification destination. The wake-up of the host task 110 can be requested.

  As described above, an interrupt is entered from a task on the host OS 100, and the guest task 210 is woken up in the interrupt process on the guest OS 200. Therefore, the guest task 210 can be woken up from the host task 110.

  Thereby, since it is not necessary to poll the arrival of data on the guest OS 200 side, there is no overhead due to the polling process, and the process is not delayed until the next polling timing.

Embodiment 3 FIG.
A third embodiment will be described with reference to FIGS.
Since the hardware configuration of the parallel processing apparatus 900 in this embodiment is the same as that described in the first embodiment, description thereof is omitted here.

FIG. 22 is a conceptual diagram showing an example of the relationship of programs (tasks) executed in the parallel processing device 900 in this embodiment.
Note that programs or data that are the same as the programs or data described in Embodiment 1 are assigned the same reference numerals, and descriptions thereof are omitted here.

The host OS 100 has guest OS priority information 151.
The guest OS priority information 151 is information on how to change the priority of the guest OS 200.

One of the host tasks 110 managed by the host OS 100 is a priority control task 109.
The priority control task 109 is a program that performs processing for changing the priority of the guest OS.

FIG. 23 is a block configuration diagram showing an example of a functional block configuration of the parallel processing device 900 according to this embodiment.
Note that functional blocks that are common to the blocks described in the first embodiment are given the same reference numerals, and description thereof is omitted here.

  The parallel processing device 900 includes a guest OS priority information storage unit 394, a priority rewriting unit 351, and the like.

  The guest OS priority information storage unit 394 stores guest OS priority information 151 using a storage device.

The priority rewriting unit 351 rewrites the priority of the guest OS 200 stored in the priority storage unit 391 based on the guest OS priority information stored in the guest OS priority information storage unit 394. At this time, the priority of the guest OS 200 is changed according to the elapsed time measured by the clock device 906.
The priority rewriting unit 351 is realized by the execution device 901 executing the priority control task 109.

  FIG. 24 is a diagram showing an example of the data structure of the guest OS priority information 151 stored in the guest OS priority information storage unit 394 in this embodiment.

  The guest OS priority information 151 is data indicating, for example, the priority 501 of the priority execution period, the time 502 of the priority execution period, and the time 503 of the non-priority execution period.

The priority 501 of the priority execution period indicates a priority when the guest OS 200 is executed with a high priority.
A priority execution period time 502 indicates a period of time during which the guest OS 200 is executed with a high priority.
The non-priority execution period time 503 indicates the time period during which the guest OS 200 is executed with the lowest priority.

FIG. 25 is a conceptual diagram showing an example of task priorities in this embodiment.
As the priority rewriting unit 351 rewrites the priority of the guest OS 200, the priority between the host tasks 110 goes back and forth between the left state and the right state.

The period during which the guest OS 200 is executed with high priority (priority execution period) is in the state on the left side.
In this state, unless the guest OS 200 enters a sleep state, the task selection unit 332 does not select the normal processing tasks 123 to 125 having a lower priority than the guest OS 200, and the normal processing tasks 123 to 125 are executed. There is nothing.
Also, interrupts that cause the interrupt processing tasks 113 and 115 having a lower priority than the guest OS 200 to be executed are masked by the interrupt mask, so that the interrupt processing tasks 113 and 115 are executed unless the guest OS 200 enters a sleep state. Interrupts to be executed are not generated, and the interrupt processing tasks 113 and 115 are not executed.

When the guest OS 200 manages a large number of guest tasks 210, it is rare that all of the guest tasks 210 are in an inexecutable state, and therefore the guest OS 200 is rarely in a sleep state.
Even if the task has a low priority, if there is no opportunity to execute it regularly to some extent, it may interfere with the processing.

  Therefore, in this embodiment, the priority of the guest OS 200 is forcibly lowered to give an execution opportunity to a task with a low priority.

  The priority rewriting unit 351 uses the clock device 906 to measure the elapsed time since the priority execution period was started. The priority rewriting unit 351 rewrites the priority of the guest OS 200 stored in the priority storage unit 391 to the lowest priority when the time 502 of the priority execution period has elapsed.

The period during which the guest OS 200 is executed with a low priority (non-priority execution period) is in the state on the right side.
In this state, the guest OS 200 is not executed unless all the other host tasks 110 become inexecutable.
Instead, execution opportunities are also given to low priority tasks such as the normal processing tasks 123 to 125 and the interrupt processing tasks 113 and 115.

  Since the priority control task 109 needs to be executed even when the execution device 901 is executing the guest OS 200, it has a higher priority than the guest OS 200.

  FIG. 26 is a flowchart showing an example of the flow of the guest OS priority control process of the priority rewriting unit 351 in this embodiment.

  In T61, the priority rewriting unit 351 acquires the priority 501 of the priority execution period from the guest OS priority information 500 stored in the guest OS priority information storage unit 394.

  In T62, the priority storage unit 391 stores the priority 501 of the priority execution period acquired by the priority rewriting unit 351 in T61 as the priority of the guest OS (start of the priority execution period).

  In T63, the priority rewriting unit 351 acquires the priority execution period time 502 from the guest OS priority information 500 stored in the guest OS priority information storage unit 394.

At T64, the priority rewriting unit 351 sets the time 502 of the priority execution period acquired at T63 in the clock device 906.
Here, when the set time elapses, the clock device 906 notifies the interrupt signal input device 905 of the fact and generates an interrupt signal.

  In T65, the priority rewriting unit 351 causes the priority control task 109 to be in a sleep state until an interrupt from the clock device 906 occurs.

  Thereafter, when the time 502 of the priority execution period set in the clock device 906 elapses, the priority control task 109 is woken up by an interrupt from the clock device 906, and the processes after T66 are resumed.

  At T66, the priority storage unit 391 stores the lowest priority as the priority of the guest OS 200 (end of the priority execution period, start of the non-priority execution period).

  In T67, the priority rewriting unit 351 acquires the non-priority execution period time 503 from the guest OS priority information 500 stored in the guest OS priority information storage unit 394.

  At T68, the priority rewriting unit 351 sets the time 503 of the non-priority execution period acquired at T67 in the clock device 906.

  In T69, the priority rewriting unit 351 puts the priority control task 109 into a sleep state until an interrupt from the clock device 906 occurs.

  Thereafter, when the non-priority execution period time 503 set in the clock device 906 elapses, the priority control task 109 is woken up by an interrupt from the clock device 906, the processing is resumed, and the process returns to T61.

  As a result, the guest OS 200 alternately repeats the period of execution with a high priority and the period of execution with a low priority.

In this example, the priority order of the guest OS 200 in the non-priority execution period is the lowest priority order, but it does not necessarily have to be the lowest priority order.
However, if the priority of the guest OS 200 in the non-priority execution period is set to the lowest priority, even if the guest OS 200 is not in the sleep state, an execution opportunity can be given to all the other host tasks 110.

Since the existing OS is not assumed to operate as a task of another OS, the OS itself does not enter a sleep state even if all managed tasks are in a sleep state (there is no processing corresponding to S86).
Therefore, if the priority of the guest OS 200 in the non-priority execution period is set to the lowest priority, when the existing OS is used as the guest OS 200, the sleep processing (S86) need not be modified. Development costs can be reduced.

  In this example, there are two types of priority of the guest OS 200 and the period of two priorities is repeated. However, the number of priorities is not limited to two and may be larger.

  In this example, the priority is rewritten when a predetermined time has passed regardless of whether or not the guest OS 200 is executed. However, only the time when the guest OS 200 is executed is measured, The priority may be rewritten when it is executed for a period of time.

  Further, the host task 110 rewrites the guest OS priority information 500 stored in the guest OS priority information storage unit 394, so that, for example, the processing amount to be processed by the guest task 210 and the host tasks 110 other than the guest OS 200 can be processed. Depending on the amount of processing to be processed, the time and priority of the guest OS 200 can be changed. As a result, the OS can be switched according to the processing load.

  According to the parallel processing device in this embodiment, since the priority rewriting unit 351 periodically changes the priority of the guest OS 200, the host task 110 having a lower priority than the guest OS 200 in the priority execution period can also be used. There is an effect that regular execution opportunities are given.

  According to the parallel processing device of this embodiment, since the priority order of the guest OS 200 in the non-priority execution period is set to the lowest order, there are few modifications required when using an existing OS as the guest OS 200, and the development cost is suppressed. There is an effect that can be.

The task activation method used by the parallel processing device described above is:
In a multi-OS configuration in which the guest OS operates as one task of the host OS, the task priority and interrupt mask setting values are assigned at task startup based on the task priority and interrupt processing priority. It is characterized in that it is determined that the processing of the embedded process does not hinder the processing of the task with a higher priority.

The interrupt mask setting process in the multi-OS system by the parallel processing device described above is
When masking interrupts to be processed by the guest OS, the interrupt mask of the guest OS has a higher priority than the guest OS by masking the interrupt at the highest priority interrupt level handled by the guest OS. It is characterized by not inhibiting the treatment.

The multi-OS system using the parallel processing device described above is
When there is no processing to be executed in the guest OS, the sleep of the host OS is called to release the CPU.

The multi-OS system using the parallel processing device described above is
When the guest OS is in a sleep state and an interrupt to be processed by the guest OS occurs, the host OS wakes up the guest OS.

The multi-OS system using the parallel processing device described above is
When a task that is sleeping on the guest OS is woken up from the host OS, an interrupt to be processed on the guest OS side is generated from the host OS side, and the guest OS side wakes up the task on the guest OS in the interrupt processing. It is made to raise.

The multi-OS system using the parallel processing device described above is
In a multi-OS configuration in which a guest OS operates as one task of the host OS, the priority of the guest OS is raised or lowered with the passage of time.

FIG. 2 is a hardware configuration diagram illustrating an example of a hardware configuration of a parallel processing device 900 according to the first embodiment. FIG. 3 is a conceptual diagram illustrating an example of a relationship between programs (tasks) executed in the parallel processing device 900 according to the first embodiment. FIG. 3 is a block configuration diagram illustrating an example of a functional block configuration of the parallel processing device 900 according to the first embodiment. FIG. 3 is a conceptual diagram illustrating an example of task priorities in the first embodiment. FIG. 3 is a conceptual diagram illustrating an example of a relationship between a priority order of a host task 110 and an interrupt priority order in the first embodiment. 6 is a diagram illustrating an example of the contents of a mask table 108 generated by a mask table generation unit 333 and stored in a mask table storage unit 334 in Embodiment 1. FIG. FIG. 6 is a diagram showing an example of an interrupt vector stored in an interrupt vector storage unit 311 in the first embodiment. FIG. 6 is a flowchart showing an example of a task activation process flow of the schedule unit 330 when the host task 110 is activated in the first embodiment. FIG. 3 is a flowchart showing an example of a schedule process flow of a schedule unit 330 according to the first embodiment. FIG. 4 is a flowchart showing an example of a task switching process flow of a dispatch unit 320 according to the first embodiment. FIG. 3 is a flowchart showing an example of a flow of interrupt processing of an interrupt processing unit 310 when an interrupt signal is input in the first embodiment. The flowchart figure which shows an example of the flow of the interruption process of the interruption process programs 661-664 performed at the time of interrupt signal input in Embodiment 1. FIG. The flowchart figure which shows an example of the flow of OS switching processing of the switching program 669 performed at the time of interrupt signal input in Embodiment 1. FIG. The flowchart figure which shows an example of the flow of OS switching processing of the switching program 679 at the time of interrupt signal input in Embodiment 1. FIG. FIG. 5 is a flowchart showing an example of a flow of OS switching processing of an OS switching task 107 in the first embodiment. FIG. 6 is a flowchart showing an example of a flow of schedule processing of the guest OS 200 in the first embodiment. FIG. 6 is a block configuration diagram illustrating an example of a functional block configuration of a parallel processing device 900 according to a second embodiment. The figure which shows an example of the data structure of the data 400 for OS synchronization which the data storage part 393 for OS synchronization in Embodiment 2 memorize | stored. FIG. 10 is a flowchart showing an example of a flow of schedule processing of the guest OS 200 in the second embodiment. FIG. 9 is a flowchart showing an example of a schedule process flow of a schedule unit 330 according to the second embodiment. The flowchart figure which shows an example of the flow of the inter-OS communication interruption process of the interruption process program which processes the interruption by the interruption signal input by T18 in Embodiment 2. FIG. 10 is a conceptual diagram illustrating an example of a relationship between programs (tasks) executed in the parallel processing device 900 according to the third embodiment. FIG. 10 is a block configuration diagram illustrating an example of a functional block configuration of a parallel processing device 900 according to a third embodiment. FIG. 14 is a diagram illustrating an example of a data structure of guest OS priority information 151 stored in a guest OS priority information storage unit 394 according to the third embodiment. FIG. 10 is a conceptual diagram illustrating an example of task priorities in the third embodiment. FIG. 10 is a flowchart illustrating an example of a flow of guest OS priority control processing of a priority rewriting unit 351 according to the third embodiment.

Explanation of symbols

  100 Host OS, 101, 201 Scheduler, 102, 202 Interrupt vector, 103, 203 Interrupt processing, 104, 204 Mask setting processing, 105, 205 Inter-OS synchronization processing, 106 Task on host OS, 107 OS switching task , 108 Mask table, 109 Priority control task, 110 Host task, 111 to 115, 211 to 212 Interrupt processing task, 121 to 125, 221 to 223 Normal processing task, 151 Guest OS priority information, 200 Guest OS, 206 Task on guest OS, 210 Guest task, 310 Interrupt processing unit, 311 Interrupt vector storage unit, 312 Interrupt mask storage unit, 313 Interrupt processing execution unit, 320 Dispatch unit, 321 Context rewriting unit, 323 Interrupt vector Rewriting unit, 324 mask Fixed part, 330 Schedule part, 331 Executable judgment part, 332 Task selection part, 333 Mask table generation part, 334 Mask table storage part, 341 Inter-task message processing part, 351 Priority rewriting part, 391 Priority storage part, 392 Context storage unit, 393 OS synchronization data storage unit, 394 guest OS priority information storage unit, 400 OS synchronization data, 401 guest OS synchronization data, 402 flag, 501 priority of priority execution period, 502 Priority execution period time, 503 Non-priority execution period time, 611 Task priority, 612 Interrupt mask level, 621 to 632 interrupt, 641 to 659 interrupt vector, 661 to 664, 671 to 672 Interrupt processing program, 669, 679 switching program, 900 parallel processing device , 901 execution device, 902 storage device, 903 input device, 904 output device, 905 interrupt signal input device, 906 clock device.

Claims (15)

A guest parallel processing program that manages a plurality of programs as guest tasks, and switches and executes the guest tasks, thereby causing the computer to function as a guest parallel processing device that processes the plurality of programs in parallel, and other programs In a parallel processing device that processes the plurality of programs and the other programs in parallel by managing the host tasks and switching and executing the host tasks,
An execution device for executing the program;
A storage device for storing information;
Interrupts the execution of the program being executed by the execution device and outputs an interrupt signal to the execution device that requests the execution device to execute an interrupt processing program for processing an interrupt. An interrupt signal input device;
Based on a request by an interrupt signal input by the interrupt signal input device, an interrupt vector storage unit that stores information indicating a program executed by the execution device as an interrupt vector using the storage device;
A task selection unit for selecting a host task to be executed by the execution device from the host tasks;
Different interrupt vectors are stored in the interrupt vector when the host task selected by the task selection unit is the other program and when the host task selected by the task selection unit is the guest parallel processing program. Interrupt vector rewriting part to be stored in the part,
A parallel processing apparatus comprising: The above interrupt vector rewriting part
When the host task selected by the task selection unit is the other program, the interrupt vector storage unit stores
A switching program that makes the guest parallel processing program executable as an interrupt vector for an interrupt signal that requests the execution device to execute an interrupt processing program that is one of the guest tasks. Memorize the interrupt vector
As an interrupt vector for an interrupt signal that requests the execution device to execute an interrupt processing program that is one of the host tasks, the interrupt signal is executed to the execution device. 2. The parallel processing apparatus according to claim 1, wherein an interrupt vector indicating an interrupt processing program which is one of the requested host tasks is stored. The above interrupt vector rewriting part
When the program selected by the task selection unit is the guest parallel processing program, the interrupt vector storage unit stores
As an interrupt vector for an interrupt signal that requests the execution device to execute an interrupt processing program that is one of the guest tasks, the interrupt signal is executed to the execution device. Store the interrupt vector indicating the interrupt processing program that is one of the above guest tasks to request,
Another program having a higher priority than the guest parallel processing program is used as an interrupt vector for an interrupt signal that requests the execution device to execute an interrupt processing program that is one of the host tasks. The parallel processing apparatus according to claim 1, wherein an interrupt vector indicating a switching program to be executed is stored. The interrupt signal input device further includes:
4. The parallel processing device according to claim 2, wherein when the execution device executes the switching program, the interrupt signal is output to the execution device. The interrupt signal input device is
2. The interrupt signal is output to the execution device after the interrupt signal is output to the execution device until the execution device executes the interrupt processing program. The parallel processing device according to 1. After the interrupt signal input device inputs the interrupt signal to the execution device, the interrupt signal is input to the execution device until the execution device executes an interrupt stop command for stopping the output of the interrupt signal. Output to the execution unit,
The interrupt processing program includes the interrupt stop instruction,
The parallel processing apparatus according to claim 2, wherein the switching program does not include the interrupt stop instruction. The parallel processing device further includes:
Information indicating whether or not the execution device is permitted to execute an interrupt processing program in response to a request for an interrupt signal output from the interrupt signal input device to the execution device is used as an interrupt mask. An interrupt mask storage unit for storing using the storage device;
When the program selected by the task selection unit is a program having a higher priority than the guest parallel processing program, the execution of the interrupt processing program as the guest task is executed in the interrupt mask storage unit. As an interrupt mask for an interrupt signal requested to the device, store an interrupt mask indicating that the execution device is not permitted to execute the interrupt processing program that is the guest task,
When the program selected by the task selection unit is the guest parallel processing program, the interrupt processing program that is the host task having a lower priority than the guest parallel processing program is executed in the interrupt mask storage unit As an interrupt mask for an interrupt signal for requesting the execution device, the execution device that executes the interrupt processing program, which is the host task having a lower priority than the guest parallel processing program, is executed. A mask setting unit for storing an interrupt mask indicating that it is not permitted,
The parallel processing apparatus according to claim 1, comprising: The parallel processing device further includes:
A priority storage unit that stores information indicating the priority order in which the execution device should execute the host task as a priority, using the storage device;
An executable determination unit that determines whether the execution device is in a state in which the host task can be executed;
Have
The task selector above
Selecting a host task to be executed by the execution device based on the priority stored in the priority storage unit from among the host tasks determined to be executable by the executable determination unit. The parallel processing device according to claim 1. The executable determination unit is
The parallel processing apparatus according to claim 8, wherein when all of the guest tasks are not executable, the guest parallel processing program is determined not to be executable. The executable determination unit is
When the execution device executes the host task, the host device is not in an executable state when the execution device executes a process for notifying that the host task is not in an executable state. Judgment
The guest parallel processing program is
9. The parallel processing apparatus according to claim 8, further comprising a process of notifying that the guest task is not executable when all of the guest tasks are not executable. The parallel processing device
A clock device for measuring elapsed time;
A priority rewriting unit for rewriting the priority of the guest parallel processing program stored in the priority storage unit based on the elapsed time measured by the clock device;
The parallel processing device according to claim 8, comprising: The interrupt signal input device further includes:
The execution device generates a message to be notified to the notification waiting program that is the guest task that is not executable by waiting for a message notified from the other program, by the execution device executing the other program If
An interrupt signal for requesting the execution device to execute the interrupt processing program that is the guest task for making the notification waiting program executable is output to the execution device. The parallel processing device according to claim 1. The parallel processing device further includes:
A notification destination storage unit that stores information indicating the notification waiting program using the storage device when the execution device generates the message to be notified to the notification waiting program by executing the other program. Have
Request for an interrupt signal that the interrupt signal input device outputs to the execution device when the execution device generates the message to be notified to the notification waiting program by executing the other program 13. The interrupt processing program executed by the execution device based on the notification includes a process in which the execution device determines the notification waiting program based on information stored in the notification destination storage unit. The parallel processing device according to 1. An execution device for executing the program;
A storage device for storing information;
Interrupts the execution of the program being executed by the execution device and outputs an interrupt signal to the execution device that requests the execution device to execute an interrupt processing program for processing an interrupt. An interrupt signal input device;
Based on a request by an interrupt signal input by the interrupt signal input device, an interrupt vector storage unit that stores information indicating a program executed by the execution device as an interrupt vector using the storage device;
A parallel processing device having
A guest parallel processing program that manages a plurality of programs as guest tasks, and switches and executes the guest tasks, thereby causing the computer to function as a guest parallel processing device that processes the plurality of programs in parallel, and other programs In a parallel processing method for processing the plurality of programs and the other programs in parallel by managing the host tasks and switching and executing the host tasks.
A task selection step for selecting a host task to be executed by the execution device from among the host tasks;
Interrupt vector rewriting part
Different interrupt vectors are used when the host task selected by the task selection unit in the task selection step is the other program and when the host task selected by the task selection unit is the guest parallel processing program. An interrupt vector rewriting step to be stored in the interrupt vector storage unit;
A parallel processing method characterized by comprising:   A parallel processing program for causing a computer to function as the parallel processing device according to claim 1.

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