JP2004318538A - Method for monitoring performance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for monitoring the performance of a processor having a plurality of privilege modes whereby when a counter for counting the occurrence of events overflows, an interrupt handler matching the privilege level thereof in operation can be directly obtained. <P>SOLUTION: The method for monitoring performance is disclosed. A processor CPU having a plurality of privilege modes is provided with a counter means 1-0 for counting events within the processor and exchange events outside it, and an indicating means 1-2 for indicating destinations to the processor for each privilege level of the processor CPU when the counter means 1-0 overflows, to render the destinations controllable at each privilege level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
[0001] 1. Field of the Invention [0002] The present invention relates to a performance monitoring method for accurately and efficiently analyzing the operating state of software that operates using a plurality of privilege levels of a processor, and more particularly to a virtual machine implemented by software. In an environment, the present invention relates to a program which can cope with a behavior analysis of a program in each layer and a tuning for checking and improving a problem of the program.
[0002]
2. Description of the Related Art Many modern processors have a performance monitoring counter for counting events inside the processor and events for external communication.
[0003]
For example, an Intel Pentium processor has a plurality of counters, and is configured to be able to select and count from a number of events such as the number of clocks, the number of executed instructions, or the number of cache misses (for example, Non-Patent Document 1).
[0004]
As a result, it is possible to analyze an operation such as which part of the program has been used a lot.
[0005]
The PowerPC processor of International Business Machines Corporation has the same configuration, and can select and count from a large number of events.
[0006]
Some of these processors have a function of generating an interrupt at a specific or specified vector when the counter overflows.
[0007]
By using this function to sample the address where a specific event has occurred, it is possible to analyze where in the program the corresponding event occurs frequently.
[0008]
By using this technique, it is possible to perform tuning such as behavior analysis and bottleneck analysis of the operating system and application programs. Note that commercially available software that performs such an operation includes VTune manufactured by Intel Corporation.
[0009]
[Non-patent document 1]
"IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide" published by Intel Corporation
(IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide
CHAPTER15 Debugging and Performance
Monitoring
In particular, see the part after “15.8 PERFORMANE MONITORING OVERVIEW”. )
Intel's Web site (http://www.intel.com)
[0010]
According to the conventional performance monitoring method, as shown in FIG. 6, a hardware 1, a virtual machine monitor 2, an operating system (hereinafter referred to as OS) OS1, OS2,. In the virtual machine environment, the overflow collecting means 10 is provided in the virtual machine monitor 2 at a1, a2, a3, a4,... To detect overflow of a counter for counting the occurrence of the event.
[0011]
The privilege level indicates the restricted state of the function of the processor constituting the hardware, and the lower the numerical value is, the higher the privilege level is. The virtual machine monitor 2 having the privilege level 0 can use all the resources of the hardware. In the lower privilege level 2, the directly usable resource portion is considerably restricted compared to the higher privilege level portion.
[0012]
As described above, in the related art, when the counter that counts the occurrence of the event overflows, only one interrupt destination can be generated. Further, there is no function of changing the interrupt destination according to the operation state of the processor, that is, according to the privilege level.
[0013]
For this reason, when a plurality of pieces of software are operated in different privilege modes of the processor, it is not possible to directly generate an interrupt in the software operating in each layer, and the virtual part which controls the root part, that is, the whole once is controlled. The machine monitor 2 receives an interrupt, notifies each layer, and collects data that characterizes the operation of the program. In order to collect information for grasping the operation state of each layer required for profiling. The program is operated between the occurrence of the overhead and the information collection, causing a loss of accuracy, deviations in details, insufficient analysis, and overhead and distortion of measurement.
[0014]
In particular, in a virtual machine environment as shown in FIG. 6, interrupt processing is generally performed by the virtual machine monitor 2, so that the OS running thereon cannot receive an interrupt directly, and operates on the virtual machine monitor. It is difficult to accurately grasp the problem of the OS or application tuning, that is, the problem of the program, and to improve the problem.
[0015]
Accordingly, it is an object of the present invention to provide a performance monitoring method capable of profiling with low overhead when the counter overflows.
[0016]
SUMMARY OF THE INVENTION The present invention provides a function for dynamically changing an overflow interrupt destination of an event counter in accordance with the operation state of a processor, and a performance monitoring system using this function.
[0017]
An interrupt destination register is individually provided for each of a plurality of privilege levels in which the processor operates, and the interrupt destination is changed according to the privilege level in which the processor is currently operating. Also, by utilizing this function, a plurality of software operating at each privilege level are provided with an overflow interrupt processing means of an event counter, and necessary information is collected at each layer.
[0018]
As a result, in a case where a plurality of software programs are operated in different privileged modes of the processor, particularly in a virtual machine environment implemented by software, the virtual machine monitor and each operating system running thereon can be simultaneously operated with low overhead. Profiling can be performed.
[0019]
FIG. 1 shows a principle diagram of the present invention. In FIG. 1, 1 is hardware, 2 is a virtual machine monitor, 20 is an event counter overflow interrupt processing means provided in the virtual machine monitor, 21 is an event counter overflow interrupt processing means provided in the OS1, and 22 is provided in the OS2. The overflow interrupt processing means of the event counter provided in the application a1, the overflow interrupt processing means of the event counter provided in the application a1, the overflow interrupt processing means of the event counter provided in the application a2, and the overflow interrupt processing means 25 and 26 are provided in the applications a3 and a4, respectively. 5 shows overflow interrupt processing means of the event counter. One of the interrupt processing units 23 and 24 and one of the interrupt processing units 25 and 26 may be omitted. The privilege level of the virtual machine monitor is “0”, the privilege levels of OS1 and OS2 are “1”, and the privilege levels of the applications a1 to a4 are “2”.
[0020]
The OS1 and OS2 are selectively controlled by the virtual machine monitor 2, the applications a1 and a2 are selectively controlled by the OS1, and the applications a3 and a4 are selectively controlled by the OS2.
[0021]
The object in the present invention can be achieved by the following (1) to (4).
[0022]
(1) In a processor having a plurality of privilege modes, a counter means for counting an event inside the processor and an event of exchange with the outside, and an instruction means for designating an interrupt destination for each privilege level are provided. A performance monitoring method that allows the processor to control the interrupt destination for each processor privilege level.
[0023]
(2) The performance monitoring method according to (1), wherein an interrupt destination position, an interrupt level, and an interrupt mask can be designated for each processor privilege level when the counter means overflows.
[0024]
(3) In the above (1) or (2), a plurality of software can be operated in different privilege modes of the processor, and the software of each privilege level can directly obtain an overflow interrupt of the counting means for counting the event. Performance monitoring method.
[0025]
(4) In the above (3), profiling of a plurality of software is performed by operating a plurality of software for each privilege level of the processor and arranging an overflow interrupt handler of the event counter means within the same privilege level at the same logical address. A performance monitoring method that enables parallel execution.
[0026]
Thereby, the following effects can be obtained.
[0027]
(1) When the counter for event measurement overflows, interrupt control is performed for each privilege level of the processor. Therefore, interrupts can be individually interrupted according to the privilege level, and necessary data can be collected immediately. Therefore, accurate behavior analysis and bottleneck analysis can be performed without time lag.
[0028]
(2) Since an interrupt destination position, an interrupt level, and an interrupt mask can be specified for each privilege level, more detailed control such as masking a portion deemed unnecessary for performance analysis can be performed.
[0029]
(3) Since a plurality of software programs can be operated in different privilege modes of the processor and an appropriate interrupt handler for the counter overflow interrupt can be directly called, there is no overhead, accurate behavior analysis, bottleneck analysis, etc. Can be tuned.
[0030]
(4) Since a plurality of pieces of software are operated for each privilege level of the processor and the overflow interrupt handler of the event counter means within the same privilege level is arranged at the same logical address, the vector table is written even when the OS is switched, for example. Since there is no need to change, profiling of the OS and the application can be performed in parallel with less overhead.
[0031]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. In FIG. 2, 1-0 is an event counter, 1-1 is a privilege level checking means, and 1-2 is a vector table register, which is provided in the processor CPU in the hardware 1. The processor CPU executes a program composed of instructions 1, 2, 3,... Held in the memory M.
[0032]
The event counter 1-0 is incremented when a predetermined monitoring event, for example, a cache miss occurs during execution of the program, and the count value of the event counter 1-0 is set to a predetermined value. When the counter overflows, that is, when a counter overflow occurs, this is notified to the privilege level checking means 1-1 of the processor, and the privilege level of the instruction which caused the monitoring event at that time is checked, and the vector table register is checked. The interrupt processing set to the corresponding privilege level division from 1-2 is notified to the interrupt processing unit to execute the interrupt processing.
[0033]
In the vector table register 1-2, an interrupt handler address to be executed for this interrupt processing is written for each of the privilege levels 0, 1, and 2. By executing this, an event (for example, Basically, information indicating at which address the cache miss, the number of executed instructions, the number of clocks, and the like, and when the count overflow occurs is collected.
[0034]
The event counter 1-0 is provided for each event such as a cache miss, the number of clocks, the number of executed instructions, and the like. However, a common event counter may be provided among a plurality of events to count up the plurality of events collectively.
[0035]
When the event counter 1-0 overflows while the instructions 1, 2, 3,... Are sequentially executed, the privilege level of the instruction that caused the event is checked, and the vector table of the corresponding privilege level is checked. The interrupt processing set in the register 1-2 is performed. 2, the numbers 100, 110, 120,... On the left side of the instructions 1, 2, 3,... Indicate the memory addresses where the instructions are written. In this way, it is possible to directly call an appropriate interrupt handler for an overflow interrupt of an event counter which is a performance monitoring counter.
[0036]
A second embodiment of the present invention will be described with reference to FIG.
[0037]
In the second embodiment, an interrupt function of an event counter for measuring an event is controlled. Therefore, as shown in FIG. 3, a vector table corresponding to the number of privilege levels (three levels in this example) is used. A register 1-2-0 is prepared, and a mask bit, an interrupt level, and an interrupt number can be set in each vector table register 1-2-0.
[0038]
The mask bit indicates whether or not to enable the interrupt. For example, “0” indicates validity, and “1” indicates invalidity.
[0039]
The interrupt level indicates the priority when an interrupt occurs at the same time. For example, “0” indicates the highest priority, and “1” indicates the next priority. The example of FIG. 3 shows that when the event counters of the privilege levels 0 and 1 simultaneously overflow, the privilege level 0 is given priority.
[0040]
The interrupt number indicates the number of the interrupt vector table 1-3 to be referred to at the time of the interrupt. This interrupt number can be arbitrarily assigned according to the type of information to be collected when the event counter overflows. In the example of FIG. 3, when the event counter of the privilege level 0 overflows, an interrupt process is performed based on the interrupt handler of the interrupt 3 handler address indicated by the interrupt number 3 in the interrupt vector table 1-3, and the privilege level 1 of the privilege level 1 is processed. When the event counter overflows, an interrupt process is performed based on the interrupt handler of the interrupt 2 handler address indicated by the interrupt number 2. When the privilege level 2 event counter overflows, the interrupt handler of the interrupt 1 handler address indicated by the interrupt number 1 is executed. An interrupt process based on this is performed.
[0041]
As described above, when the event counter overflows and when the mask bit of the vector table register 1-2-0 according to the privilege level of the instruction which caused the event is set to be valid, the interrupt number An interrupt is generated with reference to the interrupt vector table corresponding to the above.
[0042]
In this way, fine control can be performed such that information collection of a specific privilege level can be focused.
[0043]
A third embodiment of the present invention will be described with reference to FIGS.
[0044]
FIG. 7 shows a conventional interrupt processing operation diagram in a virtual machine environment realized by software, and FIG. 4 shows a third embodiment of the present invention.
[0045]
Conventionally, an interrupt handler in a virtual machine monitor, which is a normal interrupt processing routine, is registered in all the interrupt handler addresses in the interrupt vector table IT of the memory M in FIG.
[0046]
Therefore, when an overflow interrupt of the event counter CNT occurs, regardless of whether the privilege level of the event is 0 or 1, the interrupt handler VIH in the virtual machine monitor is first called, and thereafter, the interrupt handler VIH is displayed on the virtual machine monitor at that time. OS running, are registered, for example, in the interrupt vector table T ₁ of the OS1, predetermined, for example, interrupt handler "interrupt 1" is called, the interrupt processing is performed.
[0047]
In this case, as described above, since the interrupt handler corresponding to the privilege level is called via the interrupt handler in the virtual machine monitor, overhead and distortion of measurement have occurred.
[0048]
In order to improve this, in this embodiment shown in FIG. 4, when an overflow interrupt occurs in the event counter IC, the privilege level at that time is checked, and the vector table register 1-0 is referred to according to the interrupt level. I do. In the vector table register 1-0, the address of the interrupt handler of the software operating at each privilege level is registered in the interrupt vector table in the memory M which is referred to when an interrupt due to overflow occurs. .
[0049]
Thus, for example, when the event counter overflows while the OS1 of the privilege level 1 is operating, the interrupt handler for the privilege 1 is immediately referred to by referring to the section of the privilege 1 in the vector table register 1-0. Interrupt 1 "can be called, and an interrupt handler corresponding to each privilege level can be called directly without passing through the interrupt handler of the virtual machine monitor.
[0050]
Accordingly, as shown in FIG. 4, even when a plurality of software, for example, virtual machine monitors, OS1, OS2, applications a1, a2, a3, and a4 are simultaneously operated in different privilege modes of the processor, an appropriate interrupt handler is set. Can be called directly.
[0051]
A fourth embodiment of the present invention will be described with reference to FIG.
[0052]
Even when an interrupt handler of software operating at each privilege level is registered in the interrupt vector table, if a plurality of software are operating within the same privilege level, for example, if OS1 and OS2 are operating, Each time the software is switched, it is necessary to change the handler address in the interrupt vector table.
[0053]
In order to improve this, in the fourth embodiment, the software having the same privilege level, for example, the overflow interrupt handlers of the event counters of OS1 and OS2 are arranged at the same logical address as shown in FIG.
[0054]
As shown in the physical memory and the logical memory in FIG. 5, the areas of OS1 and OS2 are completely different even if the logical addresses are the same, and their contents are also different. Different physical addresses happen to be mapped to the same logical address. Actually, the contents of the interrupt handlers of the event counters of OS1 and OS2 are different.
[0055]
By arranging the overflow interrupt handler address of the event counter at the same logical address in this way, it is possible to directly call the interrupt handler performing the corresponding processing not only between privilege levels but also when switching software within the same privilege level. Becomes possible.
[0056]
As described above, according to the present invention, when a plurality of software programs are operated in different privilege modes of the processor, or when a plurality of software programs are simultaneously operated in the same privilege mode, the performance monitoring counter is not used. It is possible to directly call an appropriate interrupt handler for an overflow interrupt.
[0057]
As a result, in a virtual machine environment realized by software, profiling of a virtual machine monitor and each operating system and applications running on it can be performed simultaneously and in parallel with low overhead, and tuning such as behavior analysis and bottleneck analysis can be performed efficiently. It is possible to perform it accurately and accurately.
[0058]
According to the present invention, the following effects can be obtained.
[0059]
(1) When the counter for event measurement overflows, interrupt control is performed for each privilege level of the processor. Therefore, interrupts can be individually interrupted according to the privilege level, and necessary data can be collected immediately. Therefore, accurate behavior analysis and bottleneck analysis can be performed without time lag.
[0060]
(2) Since an interrupt destination position, an interrupt level, and an interrupt mask can be specified for each privilege level, more detailed control such as masking a portion deemed unnecessary for performance analysis can be performed.
[0061]
(3) Since a plurality of software programs can be operated in different privilege modes of the processor and an appropriate interrupt handler for the counter overflow interrupt can be directly called, there is no overhead, accurate behavior analysis, bottleneck analysis, etc. Can be tuned.
[0062]
(4) Since a plurality of pieces of software are operated for each privilege level of the processor and the overflow interrupt handler of the event counter means within the same privilege level is arranged at the same logical address, the vector table is written even when the OS is switched, for example. Since there is no need to change, profiling of the OS and the application can be performed in parallel with less overhead.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 shows an embodiment of the present invention.
FIG. 3 shows a second embodiment of the present invention.
FIG. 4 shows a third embodiment of the present invention.
FIG. 5 shows a fourth embodiment of the present invention.
FIG. 6 shows a conventional example.
FIG. 7 shows an interrupt processing operation diagram in a virtual machine environment.
[Explanation of symbols]
1 Hardware 2 Virtual machine monitor

Claims (4)

On processors with multiple privilege modes,
Counter means for counting an event inside the processor and an event of exchange with the outside;
Instructing means for indicating an interrupt destination for each privilege level is provided,
A performance monitoring method in which an interrupt destination can be controlled for the processor for each privilege level of the processor when the counter means overflows. 2. The performance monitoring method according to claim 1, wherein an interrupt destination position, an interrupt level, and an interrupt mask can be designated for each privilege level of the processor when the counter means overflows. 3. A performance monitor according to claim 1, wherein a plurality of software are operated in different privilege modes of the processor, and the software for each privilege level can directly obtain an overflow interrupt of the counting means for counting the event. method. 3. The profiling of a plurality of software programs is performed in parallel by operating a plurality of software programs for each privilege level of the processor and arranging an overflow interrupt handler of the event counter means within the same privilege level at the same logical address. Performance monitoring method that enables

Images