JP3846543B2 - Memory access system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access system for accessing a DRAM, and more particularly to a memory access system suitable for use in randomly accessing a memory.
[0002]
[Prior art]
First, general DRAM access will be described. FIG. 6 is a schematic diagram of a configuration of a general SDRAM. Here, it is composed of two banks, bank address 0 and bank address 1, and in each bank, data is specified by a row address and a column address. Here, for the sake of simplicity, the row address and the column address are shown as taking values from 0 to 7. Data “ABCDE” is stored in bank address 0, row address 0, and column addresses 0 to 4.
[0003]
FIG. 7 is a timing chart when accessing a general SDRAM. As an example, as shown in FIG. 6, an operation of processing one access command for storing five data “ABCDE” in bank address 0, row address 0, and column addresses 0 to 4 is shown. First, in the cycle {circle around (1)}, a row signal to be accessed is asserted, and a bank address and a row address to be accessed are designated as an address signal. As a result, the designated bank is activated. In addition, in the notation of the address signal, the number on the left side indicates the bank address, and the number on the right side indicates the row address or the column address (the same applies in the following description). For example, in the cycle {circle around (1)}, “00” is indicated as an address signal, which indicates a bank address 0 and a row address 0.
[0004]
Next, in the cycle {circle around (2)}, a column signal and a write signal to be accessed are asserted, and a bank address and a column address to be accessed are designated as an address signal. The notation of the address signal is “00”, which indicates bank address 0 and column address 0. Further, in the cycle {circle around (2)}, the first data “A” to be written is set in the data signal. Data to be written “BCDE” is output for each cycle sequentially from the next cycle. In this manner, five data “ABCDE” can be written in the SDRAM.
[0005]
Next, a case where a plurality of continuous access commands are processed will be described. When the access commands are continuous, the first access command and the next access command have the same bank address and the same row address, the same bank address but a different row address, or the case of another bank address. Possible types of inter-command processing.
[0006]
First, an access when the first access command and the next access command have the same bank address and the same row address will be described. FIG. 8 is an explanatory diagram of an example in which data is written in the same bank address and the same row address, and FIG. 9 is a timing chart in the case where such writing is similarly performed. In FIG. 8, although the configuration of the SDRAM is the same as that of FIG. 6, five data “ABCDE” are stored in the bank address 0, row address 0, and column addresses 0 to 4 of the SDRAM as shown in FIG. 3 shows a state in which three data “FGH” are stored in the bank address 0, the row address 0, and the column addresses 5 to 7.
[0007]
When sequentially executing the first access command for writing the five data “ABCDE” and the next access command for writing the three data “FGH”, first, the row signal accessed in the cycle (1) shown in FIG. And the bank address and row address to be accessed are designated by the address signal. As a result, the designated bank is activated. In this example, bank address 0 and row address 0 are designated. Next, in the cycle {circle around (2)}, a column signal and a write signal to be accessed are asserted, and a bank address and a column address to be accessed are designated as an address signal. Here, bank address 0 and column address 0 are designated. Further, the first data “A” to be written is set in the data signal. Data to be written “BCDE” is output for each cycle sequentially from the next cycle. Thereby, the write operation based on the first access command can be performed.
[0008]
In the next access command, since the bank address and row address are the same as the first access command, the bank address and row address corresponding to the cycle (1) are not specified. In the next cycle {circle around (3)} in which the last data “E” in the first access command is written, the column signal and write signal accessed in the next access command are asserted, and the bank address and column address to be accessed are specified as the address signal. To do. In this case, bank address 0 and column address 5 are designated. Further, the first data “F” to be written is set in the data signal. By sequentially outputting the data “GH” to be written for each cycle from the next cycle, a write operation based on the second access command can be performed.
[0009]
Thus, it can be seen that when the consecutive access commands have the same bank address and the same row address, data can be written continuously in the two access commands.
[0010]
Next, a case where the first access command and the next access command access the same bank address and different row addresses will be described. FIG. 10 is an explanatory diagram of an example in which data is written to the same bank address and another row address, and FIG. 11 is a timing chart in the case of performing such writing. In FIG. 10, the configuration of the SDRAM is the same as that of FIG. 6, but five data “ABCDE” are stored in the bank address 0, row address 0, and column addresses 0 to 4 of the SDRAM as shown in FIG. 3 shows a state where three data “FGH” are stored in the bank address 0, the row address 1, and the column addresses 5-7.
[0011]
When the first access command for writing such five data “ABCDE” and the next access command for writing three data “FGH” are sequentially executed, first, a row signal accessed in the cycle {circle around (1)} shown in FIG. And the bank address and row address to be accessed are designated by the address signal. As a result, the designated bank is activated. In this example, bank address 0 and row address 0 are designated. Next, in the cycle {circle around (2)}, a column signal and a write signal to be accessed are asserted, and a bank address and a column address to be accessed are designated as an address signal. Here, bank address 0 and column address 0 are designated. Further, the first data “A” to be written is set in the data signal. Data to be written “BCDE” is output for each cycle sequentially from the next cycle. Thereby, the write operation based on the first access command can be performed.
[0012]
Here, since the row address of the next access command is different, the row signal and the write signal are asserted in the next cycle {circle around (3)} in which the last data “E” is written by the first access command, and the bank address is used as the address signal. Is set to 0, and the currently active bank 0 is precharged.
[0013]
In order to execute the next access command, a row signal to be accessed is asserted at timing (4), and a bank address and a row address to be accessed are designated as an address signal. As a result, the bank is activated. In this example, bank address 0 and row address 1 are designated. Next, in the cycle {circle around (5)}, a column signal and a write signal to be accessed are asserted, and a bank address and a column address to be accessed are designated as an address signal. Here, bank address 0 and column address 5 are designated. Further, the first data “F” to be written is set in the data signal. Data “GH” to be written is output for each cycle sequentially from the next cycle. As a result, the write operation by the second access command can be performed.
[0014]
In this way, when consecutive access commands access the same bank address and different row addresses, precharge and bank active operations must be inserted between the two access commands. Therefore, for example, in the example shown in FIG. 11, it can be seen that it takes 4 cycles between accesses for actual writing.
[0015]
Finally, a case where the first access command and the next access command access different bank addresses will be described. FIG. 12 is an explanatory diagram of an example in which data is written in another bank address, and FIG. 13 is a timing chart in the case where such writing is similarly performed. In FIG. 12, although the configuration of the SDRAM is the same as that of FIG. 6, five data “ABCDE” are stored in the bank address 0, the row address 0, and the column addresses 0 to 4 of the SDRAM as shown in FIG. , Three data “FGH” are stored in bank address 1, row address 1, and column addresses 5-7.
[0016]
When the first access command for writing such five data “ABCDE” and the next access command for writing three data “FGH” are sequentially executed, first, a row signal accessed in the cycle of (1) shown in FIG. And the bank address and row address to be accessed are designated by the address signal. As a result, the designated bank is activated. In this example, bank address 0 and row address 0 are designated. Next, in the cycle {circle around (2)}, a column signal and a write signal to be accessed are asserted, and a bank address and a column address to be accessed are designated as an address signal. Here, bank address 0 and column address 0 are designated. Further, the first data “A” to be written is set in the data signal. Data to be written “BCDE” is output for each cycle sequentially from the next cycle. Thereby, the write operation based on the first access command can be performed.
[0017]
In the next access command, since the bank to be accessed is different, the row signal to be accessed is asserted in advance in the cycle (3), for example, and the bank address and row address to be accessed are designated by the address signal. Can remain active. In this example, bank address 1 and row address 1 are designated, and bank 1 is activated while data is being written to bank 0.
[0018]
Since the bank address 1 and the row address 1 are activated in advance, immediately after the write operation by the first access command is completed, the column signal and the write signal to be accessed are asserted in the cycle (4), and the address signal The bank address and column address to be accessed can be designated. Here, bank address 1 and column address 5 are designated. Further, the first data “F” to be written is set in the data signal. Data “GH” to be written is output for each cycle sequentially from the next cycle. Thereby, the write operation based on the second access command can be performed.
[0019]
Further, precharging of bank address 0 can be performed during a write operation to bank address 1. For example, in the cycle (5), bank 0 can be precharged by asserting a low signal and a write signal and setting a bank address to 0 as an address signal.
[0020]
Thus, it can be seen that even when successive access commands access different bank addresses, it is possible for two access commands to perform a write operation in succession.
[0021]
As a conventional technique using the above-described operation, there are techniques described in, for example, Japanese Patent Laid-Open Nos. 10-162131 and 10-11356. In the technique described in Japanese Patent Application Laid-Open No. 10-162131, an area for storing image data is secured in advance so that DRAM access can be followed by an access command of the same bank address and the same row address or another bank address. . This increases the number of continuous accesses as described above, and speeds up DRAM access.
[0022]
However, when the intermediate language of the printer is developed into a raster image, for example, the coordinates of the image to be drawn do not know where the intermediate language moves within the page, and access to the DRAM is random access. In such a case, there is a problem that the efficiency is deteriorated if the memory allocation is determined in advance as described above.
[0023]
In the technique described in Japanese Patent Laid-Open No. 10-11356, when an access command having the same bank and the same row address as the currently processed access command exists, the command is preferentially processed next. The order is changed. As a result, access using the same bank address and the same row address can be realized, and access can be performed without leaving a space between commands.
[0024]
However, even in this technique, when the randomness of memory access is large as described above, there is little possibility that access commands having the same bank address and the same row address exist in the command buffer, and the access efficiency is poor.
[0025]
[Problems to be solved by the invention]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a memory access system in which access time is shortened and speeded up even during random access to a DRAM.
[0026]
[Means for Solving the Problems]
The present invention is a memory access system that receives an access command and accesses a DRAM so that, for a plurality of access commands, a command that is currently processed and a command that is processed next access different bank addresses. The access command order is changed, and access to the DRAM is performed in the changed order. Using a plurality of access commands obtained by dividing the data length of one access command, successive access commands access another bank. Thus, the access commands are replaced as described above.
As described above, since access to different bank addresses can be performed continuously, continuous access is possible by performing such replacement. In addition, in a situation where random access occurs, there may be many access commands with different bank addresses, and the access time can be effectively shortened. Further, there is no restriction such as securing a data storage area in advance, and the memory can be used efficiently.
[0027]
Furthermore, in the present invention, since the access commands are replaced so that a plurality of access commands obtained by dividing the data length of one access command access another bank, for example, even when there are few access commands accessing different bank addresses, It is possible to increase an access command for a bank address that has been accessed less. Therefore, the possibility that continuous access can be performed by performing replacement so as to access different bank addresses between adjacent access commands increases, and the access time can be further shortened.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a memory access system of the present invention. In the figure, 1 is a command generation unit, 2 is an access command holding unit, 3 is an access timing control unit, 4 is SDRAM, 5 is an access command control unit, 6 is a data output control unit, 11 to 14 are command buffers, 15 to 15 Reference numeral 17 denotes a selector. In this example, a write command is issued from the command generation unit 1 side, data is stored in the SDRAM 4, and the data is read and output by a read command from the data output control unit 6.
[0029]
In this example, the command generator 1 generates a write command for the SDRAM 4. FIG. 2 is an explanatory diagram of an example of the data structure of the write command. For example, as shown in FIG. 2, the write command includes a write access start address (bank address, row address, column address), write data, the number of write bursts (transfer data amount), and the like. Note that the command generation unit 1 may not be provided, and for example, a write command as shown in FIG. 2 may be input from the outside.
[0030]
The access command holding unit 2 holds a plurality of write commands generated by the command generating unit 1. In this example, the access command holding unit 2 has four command buffers 11 to 14, and whether or not the write command generated from the command generation unit 1 is empty in the order of the command buffers 11, 12, and 13. Is transferred to an empty command buffer. The write command stored in the command buffer 11 is then sent to the access timing control unit 3. The command buffer 14 is used when the write command is divided by the access command control unit and the write command increases. Selectors 15 to 17 are provided on the input sides of the command buffers 11 to 13, respectively. Write commands held in the preceding command buffers 12 to 14, write commands from the command generation unit 1, and access command control unit 5 Select one of the write commands. Of course, the access command holding unit 2 is not limited to such a configuration, as long as it can hold a plurality of write commands in order. Of course, the number of commands to be held is also arbitrary.
[0031]
While managing the state of the SDRAM 4, the access timing control unit 3 receives a write request from the access command holding unit 2 and a read request from the data output control unit 6 and executes access to the SDRAM 4.
[0032]
The access command control unit 5 accesses the bank command in which the write command currently processed in the access timing control unit 3 and the write command to be processed next are different from the write command held in the access command holding unit 2. The write command in the access command holding unit 2 is replaced. Also, when replacing, if necessary, the write command is divided, and the divided write command is used to access a bank address in which consecutive write commands are different.
[0033]
FIG. 3 is a flowchart illustrating an example of the division and sequential replacement control process in the access command control unit. In the description of FIG. 3 and the following description, the write command stored in the command buffer 11 is A, the write command stored in the command buffer 12 is B, and the write command stored in the command buffer 13 is C. As shown. In FIG. 3, the command currently being processed is referred to as “current”.
[0034]
First, in S21, the address of the command currently being processed by the access timing control unit 3 is compared with the address of the write command (A) stored in the command buffer 11. As a result of the comparison, access is not delayed unless the same bank address and another row address. That is, if the same bank address and the same row address are used, continuous access is possible as described with reference to FIGS. If different bank addresses are used, continuous access is possible in this case as described with reference to FIGS. Therefore, in S22, the access command control unit 5 does not divide and change the order.
[0035]
When the comparison result in S21 is the same bank address and another row address, the access is delayed as described with reference to FIGS. In this case, in S23, the access timing control unit 3 currently processes either the write command (B) stored in the command buffer 12 or the write command (C) stored in the command buffer 13. It is determined whether there is a bank address different from the address of the command inside. As a result of the determination, if there is no other bank address, the same bank address is used, so that another bank address cannot be selected as the next write command. In this case, in S24, for example, if there is a write command with the same bank address and the same row address, the order may be changed so that the write command is continuously executed. If there is no write command with the same bank address and the same row address, the commands are executed in the same order.
[0036]
As a result of the comparison in S23, if there is a write command of another bank address, in S25, both the write commands (B) and (C) stored in the command buffer 12 and the command buffer 13 are currently The access timing control unit 3 determines whether the address of the command being processed is different from the bank address. As a result of the determination, both of the write commands (B) and (C) stored in the command buffer 12 and the command buffer 13 have a bank address different from the address of the command currently being processed in the access timing control unit 3. If there is, the command order is changed by the access command control unit 5 in S26. In this case, the write command (A) stored in the command buffer 11 and the write command (B) stored in the command buffer 12 are exchanged. As a result, the bank address of the command currently being processed is different from the bank address of the write command (B) newly stored in the command buffer 11. Further, the bank address of the write command (B) newly stored in the command buffer 11 and the write command (A) newly stored in the command buffer 12 are also different. Furthermore, the bank addresses of the write command (A) newly stored in the command buffer 12 and the write command (C) stored in the command buffer 13 are also different. In this way, by replacing the write commands, the bank addresses of successive write commands can be made different, and access can be speeded up.
[0037]
As a result of the determination in S25, both the write command (B) and (C) stored in the command buffer 12 and the command buffer 13 are different from the address of the command currently being processed in the access timing control section 3 If it is not determined, the determination in S27 is performed. In this case, only one of the write command (B) stored in the command buffer 12 or the write command (C) stored in the command buffer 13 is currently being processed by the access timing control unit 3. This is a different bank address from the command address. In S27, it is determined whether or not the write command (B) stored in the command buffer 12 is a bank address different from the address of the command currently being processed by the access timing control unit 3.
[0038]
When it is determined in S27 that the write command (B) stored in the command buffer 12 is a bank address different from the address of the command currently being processed by the access timing control unit 3, the command is further processed in S28. It is determined whether the write command (A) stored in the buffer 11 and the write command (C) stored in the command buffer 13 have the same bank address and the same row address. When the write command (B) stored in the command buffer 12 is a bank address different from the address of the command currently being processed by the access timing control unit 3, the command buffer 11 and the command buffer 12 are simply stored. The write commands (A) and (B) may be exchanged. However, after the replacement, the same bank address as the write command (C) in the command buffer 13 may occur. In S28, such a case is determined.
[0039]
If it is determined in S28 that the write command (A) stored in the command buffer 11 and the write command (C) stored in the command buffer 13 have the same bank address and the same row address, in S29, The access command control unit 5 changes the command order. In this case, the write command (A) stored in the command buffer 11 and the write command (B) stored in the command buffer 12 are exchanged. As a result, the bank address of the command currently being processed is different from the bank address of the write command (B) newly stored in the command buffer 11. Further, the bank address of the write command (B) newly stored in the command buffer 11 and the write command (A) newly stored in the command buffer 12 are also different. Furthermore, the write command (A) newly stored in the command buffer 12 and the write command (C) stored in the command buffer 13 have the same bank address and the same row address. In this way, by changing the write command, the bank addresses of successive write commands can be made different, or the write commands having the same bank address and the same row address can be made continuous, thereby speeding up access. it can.
[0040]
If the write command (A) stored in the command buffer 11 in S28 and the write command (C) stored in the command buffer 13 are not the same bank address and the same row address, they are stored in the command buffer 11. When the write command (A) and the write command (B) stored in the command buffer 12 are exchanged, the write command (A) in the new command buffer 12 and the write command (C) stored in the command buffer 13 are replaced. ) Becomes the same bank address and another row address. Therefore, in S30, the write command (B) stored in the command buffer 12 is divided and the command order is changed. Here, the divided write commands are shown as B ′ and B ″.
[0041]
FIG. 4 is an explanatory diagram of an example of command division. As a specific example, the write command shown in FIG. 4A shows an example in which data having a burst number of 20 is written to the SDRAM 4 from the bank address 0, the row address 0, and the column address 5. Such a write command can be divided into, for example, two write commands each having 10 bursts. That is, as shown in FIG. 4B, a write command for writing 10 bursts of data from bank address 0, row address 0, and column address 5, and as shown in FIG. The row address 0 and the column address 15 can be divided into write commands for writing data with 10 bursts. Of course, the number of bursts to be divided is arbitrary in the division, but it is desirable to divide in consideration of the number of cycles for bank precharge and bank activation.
[0042]
In S30, the command order is changed by changing one of the divided write commands (in this case, B ') to the command buffer 11 and writing command (A) stored in the command buffer 11 to the command buffer 12 to the divided write command. The other (B ″ in this case) is stored in the command buffer 13 and the write command (C) stored in the command buffer 13 is stored in the command buffer 14. As a result, the command order is B ′, A, B ″ and C in this order. By dividing the command and changing the order, all the commands have different bank addresses, and access can be speeded up.
[0043]
If the write command (B) stored in the command buffer 12 in S27 is determined to be the same bank address as the address of the command currently being processed by the access timing control unit 3, it is stored in the command buffer 13. The write command (C) is a bank address different from the address of the command currently being processed by the access timing control unit 3. In this case, the command currently being processed, the write command (A) stored in the command buffer 11, and the write command (B) stored in the command buffer 12 have the same bank address. For this reason, even if the order is changed so that the write command (C) stored in the command buffer 13 that accesses another bank address is stored in the command buffer 11 or the command buffer 12, between any consecutive commands. It becomes the same bank address.
[0044]
Even if consecutive commands have the same bank address, they need only have the same row address. Therefore, in S31, the write command (A) stored in the command buffer 11 and the write command ( B) is the same bank address and the same row address. When the write command (A) stored in the command buffer 11 and the write command (B) stored in the command buffer 12 have the same bank address and the same row address, in S32, the two write commands The order of commands is changed while maintaining the order. That is, the write command (C) stored in the command buffer 13 is sent to the command buffer 11, the write command (A) stored in the command buffer 11 is sent to the command buffer 12, and the write command stored in the command buffer 12. (B) is stored in the command buffer 13 respectively. In this way, the bank address of the command currently being processed is different from the bank address of the write command (C) newly stored in the command buffer 11. The bank address of the write command (C) newly stored in the command buffer 11 and the write command (A) newly stored in the command buffer 12 are also different. Further, the write command (A) newly stored in the command buffer 12 and the write command (B) stored in the command buffer 13 have the same bank address and the same row address. In this way, by changing the write command, the bank addresses of successive write commands can be made different, or the write commands having the same bank address and the same row address can be made continuous, thereby speeding up access. it can.
[0045]
If the write command (A) stored in the command buffer 11 and the write command (B) stored in the command buffer 12 in S31 are not the same bank address and the same row address, the command currently being processed, The write command (A) stored in the command buffer 11 and the write command (B) stored in the command buffer 12 access the same bank address and different row addresses, and access efficiency is poor. . In such a case, in S33, the write command (C) in the command buffer 13 having a different bank address is divided, and the command order is changed. Here, the divided write commands are shown as C ′ and C ″. The division of the write commands may be performed in the same manner as the specific example shown in FIG. 4 described above. One of the write commands (here, C ′) is sent to the command buffer 11, the write command (A) stored in the command buffer 11 is sent to the command buffer 12, and the other divided write command (here, C ″) is sent to the command buffer. 13, the write command (B) stored in the command buffer 12 is stored in the command buffer 14. As a result, the command order is C ′, A, C ″, B. By dividing the command and changing the order, all the commands have different bank addresses, and access can be speeded up. .
[0046]
FIG. 5 is an explanatory diagram of a specific example of the operation in the embodiment of the memory access system of the present invention. FIG. 5B shows a specific example of the operation when one embodiment of the memory access system of the present invention is used. As a comparative example, FIG. 5A shows the operation at the time of conventional memory access. Yes. The horizontal axis in the figure is a time axis representing the time required for processing, and each cycle is shown by being divided by vertical lines. In addition, in the upper part and the lower part in the drawing, write commands executed at respective timings are shown. Furthermore, the cycle shown with hatching in the drawing is a cycle for bank activation, and the cycle shown with cross hatching shows a cycle for performing bank precharge.
[0047]
In this specific example, a case will be described in which write commands shown at the top and bottom in the drawing are processed. Here, the write command (N) indicates a write command currently being processed, and is a command for writing data N with a burst number of 10 from the bank address 0, the row address 0, and the column address 0. The write command (A) is a write command for writing data A with the burst number 10 from the bank address 0, the row address 1, and the column address 0. Similarly, the write command (B) is a command for writing data B from the bank address 0, row address 2, and column address 0 with a burst number of 10, and the write command (C) is a burst from bank address 1, row address 0, column address 0. This is a command for writing data C in equation (10). As will be described later, the write command (C ′) and the write command (C ″) are obtained by dividing the write command (C) according to the present invention.
[0048]
First, the operation during conventional memory access will be described. Since the write command (N) and the write command (A) are the same bank address and different row addresses, in order to execute them continuously, in addition to the actual write access, for the bank precharge and the bank activation between both accesses It takes a total of 4 cycles. This is as described with reference to FIGS. For the write command (A) and the write command (B), for the same reason, a total of four cycles are required for bank precharge and bank activation in addition to write access. Since the write command (B) and the write command (C) have different bank addresses, the bank precharge and bank active processes can be performed during the execution of the write command (B). Thus, data can be written.
[0049]
On the other hand, in the memory access system of the present invention, when the write commands (A) to (C) are processed according to the flowchart shown in FIG. 3, the process in S33 is performed. That is, the write command (C) is divided into a write command (C ′) and a write command (C ″), and the two divided write commands are divided between the write command (N) and the write command (A), and The order is changed so as to be inserted between the write command (A) and the write command (B), so that the write command is (N) → (C ′) → (A) as shown in the lower part of the figure. → (C ″) → rearranged as (B). As can be seen by referring to the bank addresses, the bank addresses are not consecutive in the write commands rearranged in this order. Therefore, as shown in FIG. 5B, bank precharge and bank active can be performed in parallel with the actual write operation, and therefore the data write operation can be performed continuously. As a result, memory access can be speeded up. In the example shown in FIG. 5, the conventional access method shown in FIG. 5A takes 50 cycles. However, in the memory access system of the present invention, the processing is completed in 42 cycles as shown in FIG. 5B. ing.
[0050]
The embodiment of the memory access system according to the present invention has been described above. The present invention is not limited to this embodiment, and various modifications are possible. For example, as described above, the number of commands held in the access command holding unit 2 is not limited to three (or four), and more commands may be held. If a large number of commands can be held, there is a high probability that a command for accessing another bank exists, and the access can be further speeded up by rearranging or performing division as necessary. In that case, one command may be divided into three or more as necessary, or a plurality of commands may be divided.
[0051]
In the example shown in FIG. 1, a write command is issued from the command generation unit 1 side, data is stored in the SDRAM 4, and the data is read and output by a read command from the data output control unit 6. However, the present invention is not limited to this. In addition to the write operation based on the write command, the read operation based on the read command can be rearranged and divided as necessary to increase the access speed.
[0052]
【The invention's effect】
As is clear from the above description, according to the present invention, the access commands are divided as necessary so that the access commands for accessing different bank addresses are continuous, the access commands are rearranged, Access to DRAM. This has the effect of speeding up access to the DRAM and reducing the access time. In particular, for example, when random access occurs, there is a high probability that an access command for accessing a different bank address will occur, and a high effect can be obtained for such applications.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a memory access system of the present invention.
FIG. 2 is an explanatory diagram of an example of a data structure of a write command.
FIG. 3 is a flowchart illustrating an example of division and sequential replacement control processing in an access command control unit.
FIG. 4 is an explanatory diagram of an example of command division.
FIG. 5 is an explanatory diagram of a specific example of operation in the embodiment of the memory access system of the present invention.
FIG. 6 is a schematic diagram of a configuration of a general SDRAM.
FIG. 7 is a timing chart at the time of accessing a general SDRAM.
FIG. 8 is an explanatory diagram of an example when data is written in the same bank address and the same row address;
FIG. 9 is a timing chart when data is written to the same bank address and the same row address.
FIG. 10 is an explanatory diagram of an example when data is written to the same bank address and another row address;
FIG. 11 is a timing chart when data is written to the same bank address and another row address;
FIG. 12 is an explanatory diagram of an example when data is written to another bank address;
FIG. 13 is a timing chart when data is written to another bank address.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Command generation part, 2 ... Access command holding part, 3 ... Access timing control part, 4 ... SDRAM, 5 ... Access command control part, 6 ... Data output control part, 11-14 ... Command buffer, 15-17 ... Selector .

Claims (1)

  An access command holding means for holding a plurality of access commands for accessing the DRAM, and a bank address in which a command that is currently processing the plurality of access commands held in the access command holding means is different from a command to be processed next Access command control means for replacing the access command in the access command holding means so as to access the access command, and the access command control means divides the data length of one access command held in the access command holding means A memory access system using the plurality of access commands, wherein the access commands are exchanged so that consecutive access commands access different banks.

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