JP2016076867A - Information processor, control method for information processor, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the same circuit configuration as already configured circuit configuration information from being reconfigured in the case of dynamically performing the partial reconfiguration of the circuit configuration information.SOLUTION: In an information processor having: first storage means in which a plurality of storage areas are all rewritable; and second storage means in which circuit configuration information associated with specific function processing is stored, the function and use state of the circuit configuration information stored in each storage area is managed in association. Then, when the circuit configuration stored in any storage area is rewritten to the other circuit configuration information on the basis of a function to be executed, whether or not the same circuit configuration information is already configured is determined on the basis of the use state. In this case, when it is determined that the same circuit configuration is already configured, the circuit configuration information corresponding to the function to be executed is restrained from being reconfigured.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an information processing apparatus, a control method for the information processing apparatus, and a program.

It is well known that information processing apparatuses use reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) that can change the internal logic circuit configuration.
Generally, PLDs and FPGAs switch internal logic blocks by writing logic circuit configuration information stored in a nonvolatile memory such as a ROM to a configuration memory, which is an internal volatile memory, at startup. In addition, since the information in the configuration memory is cleared when the power is turned off, it is necessary to perform reconfiguration by writing the logic circuit configuration information into the configuration memory again when the power is turned on.
This method of configuring hardware resources only once is called static reconfiguration. On the other hand, those capable of changing the logic circuit configuration while the circuit is operating have been developed, and a method of changing the logic circuit during the operation is called dynamic reconfiguration.

  Some FPGAs can rewrite only a specific area, not the entire chip, and such rewriting is called partial reconfiguration. In particular, performing partial reconfiguration without stopping other operating circuits is called dynamic partial reconfiguration.

  In dynamic partial reconfiguration, the entire configuration memory is not rewritten at the time of dynamic reconfiguration, but only a part of the configuration memory area is rewritten to realize partial reconfiguration of the logic block inside the FPGA. Is possible.

  By using such a dynamic partial reconfiguration technology, it is possible to switch and implement multiple circuits in one area, so the function to implement hardware resource time division multiplexing and logical blocks Can be changed. As a result, it is possible to flexibly realize various functions according to applications with a small amount of hardware resources while maintaining high calculation performance by hardware.

  As a technique using this dynamic partial reconfiguration, for example, in a pipeline configuration process, a method of reconfiguring on a reconfigurable circuit in order from the first partial circuit in the pipeline and processing data while switching functions is disclosed. (For example, refer to Patent Document 1).

In recent information processing devices including image processing devices such as MFP (Multi Function Printer), it is possible to select multiple processing (copy job, print job, SEND job, etc.) according to user requests. The corresponding image processing is realized by hardware or software.
When a reconfigurable circuit such as an FPGA is applied as image processing hardware of the image processing apparatus, the circuit configuration can be dynamically and partially switched for each function as described above. As a result, various image processing functions can be realized with few hardware resources.

JP 2011-186981 A

  As described above, the reconfigurable circuit is reconfigured at least partially before each execution of various processes. While various image processing functions can be realized with a small amount of hardware resources, there is a problem in that performance is degraded due to overhead because reconfiguration takes a certain amount of time.

  The present invention has been made to solve the above-described problems. The object of the present invention is to provide circuit configuration information that has already been configured when the circuit configuration information is dynamically partially reconfigured by the function to be executed. It is to provide a mechanism that can suppress reconfiguration of the same circuit configuration.

The information processing apparatus of the present invention that achieves the above object has the following configuration.
A first storage means in which a plurality of storage areas can be rewritten, a second storage means for storing circuit configuration information associated with a specific functional process, and circuit configuration information stored in each storage area. Management means for managing functions and usage states in association with each other, and when rewriting circuit configuration information stored in one of the storage areas to other circuit configuration information based on the function to be executed, already the same circuit configuration information If it is determined that the same circuit configuration information has already been configured, the circuit configuration information corresponding to the function to be executed is not reconfigured. And a restricting means for restricting to.

  According to the present invention, when the circuit configuration information is dynamically partially reconfigured, it is possible to suppress reconfiguration of the same circuit configuration as the already configured circuit configuration information.

It is a block diagram explaining the structure of an image processing apparatus. It is a block diagram which shows the partial reconstruction of an image processing apparatus. It is a figure explaining the function and circuit function of an image processing apparatus. It is a figure which shows the circuit structure information comprised in a partial reconfiguration | reconstruction part. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. It is a figure which shows the detailed structure of a PR management table. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. It is a block diagram explaining the structure of an image processing apparatus. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. It is a figure which shows the detailed structure of a PR management table. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. It is a block diagram explaining the structure of an image processing apparatus. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. It is a figure which shows the detailed structure of a PR management table. 4 is a flowchart illustrating job execution processing control of the image processing apparatus. 4 is a flowchart illustrating job execution processing control of the image processing apparatus.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
<Description of system configuration>
[First Embodiment]
[Configuration of image processing device]

FIG. 1 is a block diagram illustrating the configuration of an image processing apparatus to which the information processing apparatus according to the present embodiment is applied.
In FIG. 1, the image processing apparatus 100 includes an operation unit 103 for a user using the image processing apparatus 100 to perform various operations. Further, the image processing apparatus 100 includes a scanner unit 109 that reads image information in accordance with an instruction from the operation unit 103, and a printer unit 107 that prints image data on paper. The operation unit 103 is connected to the system bus 120 via the operation unit I / F 113. Note that the image processing apparatus 100 shown in the present embodiment is configured to execute a copy job function, a print job function, a facsimile job function, and a send job function.
The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp (not shown), a scanning mirror, and the like for reading a document. The printer unit 107 includes a CPU (not shown) that controls the printer unit 107 and a photoconductive drum and a fixing device (not shown) that perform image formation and fixing.

  In addition, the image processing apparatus 100 includes a CPU 101 that comprehensively controls the operation of the image processing apparatus 100, and executes control software for controlling each unit of the image processing apparatus. The image processing apparatus 100 also includes a ROM 104 that stores a program executed by the CPU 101. The image processing apparatus 100 includes a RAM 111 that is a system work memory for the operation of the CPU 101 and also an image memory for temporarily storing image data. A RAM 111 and a memory controller 110 that controls writing and reading operations to the RAM 111 are provided. The memory controller 110 is connected to the system bus 120 and the image bus 121 and controls access to the RAM 111.

  The image processing apparatus 100 includes an FPGA 140 that constitutes an image processing circuit or the like as a reconfigurable device. In this embodiment, an FPGA is described as an example of a reconfigurable device. However, a configuration in which a reconfigurable device other than an FPGA is connected may be used. The image processing apparatus 100 includes a configuration controller 130 that controls the circuit configuration (configuration) of the FPGA under the control of the CPU 101.

  The image processing apparatus 100 includes a configuration ROM 150 in which logic circuit configuration information (configuration data) for configuring the FPGA 140 is stored. The FPGA 140 is dynamically rewritable and partially rewritable. That is, while a circuit configured as a part of the reconfiguration unit of the FPGA 140 is operating, another circuit can be reconfigured in another part that does not overlap with the part occupied by the circuit.

  The image processing apparatus 100 also includes a scanner I / F 108 to which image data is input from the scanner unit 109 and a printer I / F 106 that outputs image data to a printer. The FPGA 140, the scanner I / F 108, and the printer I / F 106 are connected to an image bus 121 for transferring image data to be processed.

The image processing apparatus 100 communicates (transmits / receives) with a general-purpose computer (not shown) on the network via the network I / F 102. The image processing apparatus 100 communicates (transmits / receives) with a general-purpose computer (not shown) connected to the image processing apparatus 100 via the USB I / F 114. Further, the image processing apparatus 100 is connected to a public network via a FAX I / F 115, and communicates (transmits / receives) with other image processing apparatuses and facsimile apparatuses (not shown).
The image processing apparatus 100 includes a ROM I / F 112 that controls programs executed by the CPU 101, writing to the ROM 104, and reading operations. The image processing apparatus 100 also includes a system bus 120 that connects the CPU 101, the network I / F 102, the operation unit 103, the ROM I / F 112, the configuration controller 130, and the FPGA 140 to each other. An HDD 117 is connected to the system bus 120 via the HDD I / F 116.
The CPU 101 performs parameter settings for the FPGA 140, the scanner I / F 108, and the printer I / F 106 via the system bus 120.

[Configuration related to partial reconfiguration]
Next, a configuration relating to partial reconstruction in the image processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 2 is a block diagram showing a configuration particularly related to the partial reconstruction of the image processing apparatus 100 shown in FIG.
2, the CPU 101, the configuration controller 130, the configuration ROM 150, the FPGA 140, the memory controller 110, and the ROM I / F 112 are as described above with reference to FIG. Note that FPGA is an abbreviation for programmable field array.

  The FPGA 140 further includes a partial reconstruction unit (PR1) 201, a partial reconstruction unit (PR2) 202, a partial reconstruction unit (PR3) 203, and a partial reconstruction unit (PR4) 204 therein. Each of the partial reconstruction units 201 to 204 can dynamically rewrite an image processing circuit or the like. Note that the types of functions A to F related to the circuit functions configured in the partial reconfiguration units 201 to 204 are shown in FIG. The partial reconstruction unit (PR1) 201, the partial reconstruction unit (PR2) 202, the partial reconstruction unit (PR3) 203, and the partial reconstruction unit (PR4) 204 are used as storage areas, respectively, and have specific function processing. Is stored in a rewritable manner. The specific function process is a process associated with a job type to be described later.

  In this embodiment, an example in which a circuit having an image processing or compression / decompression function is configured in the partial reconstruction unit has been described, but it goes without saying that other circuits can be configured in the partial reconstruction unit. Yes.

  The RAM 111 has an area for a PR management table 220 described later. The PR management table 220 includes function IDs indicating what functional circuits each of the four partial reconfiguration units (PR1 to PR4) 201 to 204 configures, and a flag indicating whether or not they are currently used. The

  The ROM 104 holds a priority order table described later. The ROM 104 stores the relationship between the circuit functions that can be configured in the partial reconfiguration units 201 to 204 and the priority order indicating the frequency of use of each circuit function. The priority order is prepared in the ROM 104 by assuming in advance the frequency used when the image processing apparatus 100 executes a general job.

  Here, a relationship between each circuit function configured on the FPGA 140 and a job executed by the image processing apparatus 100 is shown in FIG. Hereinafter, a circuit configured as the job operation illustrated in FIG. 3B will be described. The following operations are controlled by a program executed by the CPU 101.

The image processing apparatus 100 has a function of copying image data of a document read by the scanner unit 109 (copy job) and a function of printing print data sent from an external printer driver (PDL print job).
Also, a function for saving FAX data received from the FAX I / F 115 as image data (FAX reception job), and image data of a document read by the scanner unit 109 to an external general-purpose computer (not shown) via the network I / F 102 It has a function to send (SEND job).
In the case of an image processing system to which the dynamic reconfiguration technique is applied, a necessary image processing function is configured in the FPGA 140 according to the function selected by the user and the changed setting item, and actual processing is performed.

(Copy job)
In the copy job, the image data obtained by reading the document by the scanner unit 109 is subjected to the read image processing 302 configured in any of the partial reconstruction units 201 to 204 to be applied to a predetermined area of the RAM 111. Buffer. The image data buffered in the RAM 111 is then subjected to image processing on a circuit having a print image processing function 303 configured in any of the partial reconstruction units 201 to 204, and is sent to the printer unit 107 via the printer I / F 106. Forwarded.

  The reading image processing function 302 includes an image area separation processing unit, a color space conversion processing unit, a filter processing unit, a background removal processing unit, and the like. Here, the image area separation processing unit determines the image area by detecting a character part from the input image, and generates an image area signal used for subsequent image processing. In the table conversion process, table conversion is performed in order to convert image data, which is read luminance data, into density data. In the filter processing unit, arithmetic processing is performed with a digital spatial filter in accordance with a purpose such as edge enhancement. The background removal processing unit performs a process of removing the background color when image data obtained by reading a document having a light background color is sent.

  The print image processing function 303 includes a color space conversion processing unit, a correction processing unit, and an error diffusion processing unit. The color space conversion processing unit performs CMYK conversion on the RGB data according to the output characteristics of the image processing apparatus. The correction processing unit converts the density of the image data. The error diffusion processing unit performs N-value conversion by comparing the input image data with a predetermined threshold value, and diffuses the difference between the input image data and the threshold value at that time to surrounding pixels to be N-valued thereafter. By doing so, halftone processing is performed.

(Printer job)
In the printer job, PDL data transmitted from the host computer or the like via the network is received via the network I / F 102 and temporarily buffered in a predetermined area of the RAM 111. The CPU 101 analyzes the buffered PDL data, generates a drawing command group, and buffers it in a predetermined area of the RAM 111. The buffered drawing command group is generated by RIP processing by a circuit having a RIP (Raster Image Processor) processing function 318 configured in any of the partial reconstruction units 201 to 204, and is generated in a predetermined area of the RAM 111. Data is drawn.
The rendered image data is subjected to image processing by a circuit having a print image processing function 303 configured in any of the partial reconstruction units 201 to 204, and is transferred to the printer unit 107 via the printer I / F 106. The RIP processing function 318 is a function for drawing the read image data of the bitmap on the RAM 111 based on the drawing command group.

(FAX job)
In the FAX job, FAX data transmitted from the external public network via the FAX I / F 115 is received and buffered in a predetermined area of the RAM 111. From the received FAX data, JBIG compressed data is extracted based on the header information, and subjected to JBIG decompression processing by a circuit having the JBIG decompression circuit function 322 configured in any of the partial reconstruction units 201 to 204. The restored FAX image data is buffered in a predetermined area of the RAM 111.
The buffered FAX image data is subjected to FAX image processing on a circuit having a FAX image processing function 306 configured in any of the partial reconstruction units 201 to 204, and stored in a predetermined area of the HDD 117. The image processing for FAX includes a smoothing process, an image processing apparatus that performs resolution conversion from the resolution of the facsimile standard to the printing resolution of the image processing apparatus 100, and the like.

(SEND job)
In the SEND job, the image data read from the document by the scanner unit 109 is subjected to the image processing for reading 302 configured in any of the partial reconstruction units 201 to 204 as in the case of the copy job, and a predetermined area of the RAM 111 is obtained. Buffer. Next, in order to efficiently transmit image data to an external general-purpose computer (not shown) via the network I / F 102, the network I is subjected to JPEG compression processing by a circuit having a JPEG compression function configured in any of the partial configuration circuits. / F102 to an external general-purpose computer (not shown).

  The relationship between jobs and circuit functions has been described above. In this embodiment, an example is shown in which two circuit functions are used for each job, but the present invention is not limited to this. Similarly, the contents of functions necessary for job execution are not limited to the example shown in FIG.

Next, a configuration data storage method configured in the partial reconfiguration units 201 to 204 of the FPGA 140 in the image processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 4 is an example of configuration data configured in each of the partial reconfiguration units 201 to 204 of the FPGA 140 stored in the configuration ROM 150.

The configuration ROM 150 stores a plurality of configuration data necessary for partial reconfiguration. The configuration data 400 for PR1 represents configuration data that can be configured in the partial reconfiguration unit (PR1) 201.
FIG. 4 shows an example in which there are six functions A, B, C, D, E, and F that can be configured in the partial reconfiguration unit (PR1) 201. Reference numeral 401 denotes configuration data for configuring a function A circuit in PR1. Similarly, 402 is a PR1 function B circuit configuration, 403 is PR1 function C circuit configuration, 404 is PR1 function D circuit configuration, 405 is PR1 function E circuit configuration, and 406 is PR1 function F circuit configuration. 3 shows configuration data for configuring a circuit configuration.

  The configuration data 410 for PR2 represents configuration data that can be configured in the partial reconfiguration unit (PR2) 202. The configuration data 410 for PR2 also stores configuration data for six functions A, B, C, D, E, and F. The partial reconfiguration unit (PR2) 202 has six functions. It is possible to configure by switching.

  The configuration data 420 for PR3 represents configuration data that can be configured in the partial reconfiguration unit (PR3) 203. The configuration data 420 for PR3 also stores configuration data for six functions A, B, C, D, E, and F. The partial reconfiguration unit (PR3) 203 has six functions. It is possible to configure by switching.

  The configuration data 430 for PR4 represents configuration data that can be configured in the partial reconfiguration unit (PR4) 204. The configuration data 430 for PR4 also stores configuration data of six functions A, B, C, D, E, and F. The partial reconfiguration unit (PR4) 204 has six functions. It is possible to configure by switching.

  As described above, it is necessary to prepare configuration data for each partial reconfiguration unit. For example, in order to configure the circuit configuration of the function A to the partial reconfiguration unit (PR1) 201 and the partial reconfiguration unit (PR2) 202, the same function is realized as the PR1 function A401 and the PR2 function B402. However, it is necessary to prepare different configuration data depending on the configuration location.

  In the present embodiment, the FPGA 140 has four partial reconfiguration units, and the functions configured in the partial reconfiguration unit will be described by taking six cases of A, B, C, D, E, and F as an example. Here, although the number of partial reconfiguration units is “4” and the number of functions is “6”, this is only for the sake of easy understanding, and is not limited to those numbers.

  FIG. 5 is a flowchart showing job execution processing control of the image processing apparatus according to the present embodiment. Each procedure (step) in the flowchart of FIG. 5 is realized by the CPU 101 executing a stored control program.

First, in step S501, the image processing apparatus 100 waits for job reception. If the image processing apparatus 100 receives a copy job, print job, FAX job, SEND job, or the like in S501, the process proceeds to S502.
In step S <b> 502, the CPU 101 specifies functions that need to be configured in the FPGA 140 when executing the received job, for example, according to the table of FIG. 3B. In S503 and S504, it is determined whether there is a circuit that needs to sequentially read the PR management table 220 stored in the RAM 111 and is stopped.

Here, the detailed configuration of the PR management table 220 will be described with reference to FIG.
In FIG. 6, the PR management table 220 has a function ID indicating what function circuit is configured for each of the partial reconfiguration units 201 to 204 and each partial reconfiguration unit is in use as a use state. Has a status indicating whether or not. These function IDs and statuses are sequentially rewritten in the steps described later depending on the program that executes the job.

  In S503, the function ID in the PR management table 220 is read, and it is determined whether a desired circuit function is already configured in any of the partial reconfiguration units 201-204. For example, if the PR management table 220 is in the state shown in FIG. 6 when the function E is required, the function E does not exist in any partial reconfiguration unit, so the process proceeds to NO and branches to the partial reconstruction process from S505 to S508. To do. On the other hand, for example, when the function C is necessary, the PR management table 220 shifts to S504 because the function C circuit is already configured in PR3 as shown in FIG.

  In step S504, the CPU 101 determines whether the circuit function determined to be already configured in step S503 is used by another job. It should be noted that the image processing apparatus 100 can execute a plurality of jobs in parallel. In S504, for example, when the function B is required, the PR management table 220 determines that the function B configured in PR2 is in use as shown in FIG. 6, so that the determination is YES and the process proceeds from S505 to S508 for partial reconfiguration. .

  On the other hand, for example, when function C is required, the PR management table 220 is open as shown in FIG. 6 because the function C circuit configured in PR3 is open, so that NO is determined in S504, which will be described later. Proceed to S520. In this case, it is limited to reconfigure existing circuit functions. That is, since the circuit reconfiguration operation can be skipped, the overall time for job execution is reduced and the performance is improved.

In S503, when performing partial reconstruction, the process proceeds to S505 to perform reconstruction area selection processing. Hereinafter, the selection processing of the reconstruction unit in S505 will be described with reference to a detailed flowchart in FIG.
FIG. 7 is a flowchart showing job execution processing control of the image processing apparatus according to the present embodiment. Each procedure (step) in the flowchart of FIG. 7 is realized by the CPU 101 executing a stored control program.
First, in step S <b> 701, the CPU 101 refers to the PR management table 220. For example, when the CPU 101 determines that the PR management table 220 and the priority order table 221 are in the state illustrated in FIG. 6, the CPU 101 first refers to the PR management table 220 and extracts a reconfigurable partial reconfiguration unit. Here, it can be seen that PR1, PR3, and PR4 can be reconfigured.
In step S <b> 702, the CPU 101 obtains a function configured in the reconfigurable partial reconfiguration unit. Here, function A, function C, and function D are shown. In step S <b> 703, the CPU 101 obtains priority orders corresponding to these functions from the priority order table 221. Finally, in S704, the CPU 101 selects the partial reconfiguration unit having the lowest priority. Here, the priorities corresponding to the function A, the function C, and the function D are “4, 5, 3”, respectively. For this reason, the partial reconfiguration unit in which the function C (rank “5”) having the lowest priority is configured, that is, PR3 is selected. Here, the partial reconfiguration unit that is not configured with a circuit function has the priority “0” as shown in the priority table 221 and is the strongest selection candidate for reconfiguration.

The circuit function that is least likely to be used in the future is reconfigured from the partial reconfiguration units 201 to 204 that can be reconfigured by the above selection method. In other words, it is possible to preserve the circuit function that is highly likely to be reused and increase the probability of proceeding to YES in the future reconfiguration necessity determination process (S504), thereby improving the performance when viewed over a long period.
If there is only one partial reconstruction unit extracted in S701, it is possible to immediately select the partial reconstruction unit as a reconstruction target and omit steps S702 to S704.

Here, the description returns to the processing illustrated in FIG. When the partial reconfiguration unit to be reconfigured is selected in S505, the CPU 101 specifies configuration data to be loaded into the partial reconfiguration unit from the configuration data stored in the configuration ROM 150 in S506.
For example, when the circuit of the function E is reconfigured in the partial reconfiguration unit 204 (PR4), the configuration data 435 that is the configuration data of the function E for PR4 in FIG. 4 is determined as the configuration data.

  In S507, the CPU 101 changes the function ID and status of the PR management table 220. That is, when the function E is reconfigured to PR4, the function ID corresponding to PR4 in the PR management table 220 is changed from function D to function E and the status corresponding to PR4 is changed from “open” to “in use”. To do. These processes prevent other jobs being executed in parallel from using PR4 by mistake.

  When branching from S504 to NO and skipping partial reconfiguration of circuit functions, the CPU 101 updates the contents of the PR management table 220 in S520. In this case, since the circuit function is not reconfigured, the function ID is not updated, and only the status is changed from “released” to “in use”. This prevents other parallel executing jobs from using PR4 by mistake.

  In S508, the partial reconfiguration unit is reconfigured by the configuration controller 130. According to the above example, circuit function E is reconfigured by loading configuration data 435 into PR4. In step S509, a circuit function (image processing or compression / decompression processing) necessary for job execution is executed.

  When branching to NO in S504 and partial reconfiguration of the circuit function is skipped, the circuit of the partial reconfiguration unit that has already been configured is activated and the circuit function (image processing or compression / decompression processing) necessary for job execution is executed. To do.

On the other hand, if the circuit is reconfigured by branching from S504 to YES, the circuit of the partial reconfiguration unit partially reconfigured in S508 is activated and the circuit function (image processing or compression / decompression processing necessary for job execution) is started. ).
In step S509, the CPU 101 performs register setting for circuit activation, end interrupt wait operation, and end interrupt handling processing operation.

Here, when the operation of the circuit function is completed, in S510, the CPU 101 changes the status of the PR management table 220 to “opening”. For example, when the operation of PR4 is completed, the status corresponding to PR4 is changed from “in use” to “opening”. This makes it possible for other parallel jobs to use PR4.
This completes the processing of one circuit function. If it is not the last process, the process proceeds from S511 to NO to execute the next circuit function. If it is the last process, the process proceeds from S511 to YES to end the job.

[Second Embodiment]
In the first embodiment, when a circuit function desired to be used is not usable in the partial reconfiguration unit of the FPGA 140 and any of the partial reconfiguration units 201 to 204 needs to be reconfigured, it is most likely used in the future. The case where a low circuit is selected has been described. At that time, the CPU 101 checks the frequency of the priority table 221 that uses the function in advance as a selection criterion and stores it in the ROM 104 as the priority.
Although this method is simple to implement, it cannot cope with a difference in usage by a user who uses the image processing apparatus 100 or a case where the usage changes over time.
Therefore, an example in which a criterion for determining a function to be reconfigured according to how the image processing apparatus 100 is actually used will be described as a second embodiment and a third embodiment.

  In the second embodiment, the last used date and time of each circuit function configured in the partial reconfiguration unit of the FPGA 140 is recorded, and the oldest used circuit function can be used in the future based on the update state of each circuit function. Therefore, it is assumed that the circuit function is low, and is a candidate for reconfiguration.

FIG. 8 shows a configuration relating to partial reconfiguration of the present embodiment.
FIG. 8 is a block diagram illustrating the configuration of the image processing apparatus according to the present embodiment. The same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.
The difference from the first embodiment is that a last update date / time table 821 is prepared in the HDD 117 instead of the priority order table 221 stored in the ROM 104. Details of the last update date and time table 821 and the PR management table 220 are shown in FIG. The configuration of the PR management table 220 is not different from that in the first embodiment.

The operation flow of this embodiment will be described with reference to FIG.
FIG. 9 is a flowchart showing job execution processing control of the image processing apparatus according to the present embodiment. Each procedure (step) in the flowchart of FIG. 9 is realized by the CPU 101 executing a stored control program.
The processing in this embodiment is almost the same as that in the first embodiment. When a job is received and a necessary circuit function is specified and is not in the partial reconfiguration unit, or when it is in use depending on another job In step S905, the reconstruction unit selection process is the same.
However, there is a difference in the content of the process of selecting the partial reconfiguration unit that performs reconfiguration. As another difference, after performing processing such as image processing and compression / decompression using the circuit configured in the partial reconfiguration unit, in S910, the last update of the corresponding circuit function in the last update date / time table 821 is performed. Update the date and time.

Next, the processing of S905 as a difference will be described with reference to FIGS. 7, 10, and 11. FIG.
FIG. 11 is a flowchart showing job execution processing control of the image processing apparatus according to the present embodiment, which is a detailed procedure of S905 shown in FIG. Each procedure (step) in the flowchart of FIG. 9 is realized by the CPU 101 executing a stored control program. Also, description of the same processing as in FIG. 7 is omitted.
In FIG. 10, first, the CPU 101 refers to the PR management table 220 in S <b> 701 shown in FIG. 7. For example, when the PR management table 220 and the priority order table 221 are in the state shown in FIG. 10, the CPU 101 first refers to the PR management table 220 and extracts a reconfigurable partial reconfiguration unit. Here, it can be seen that PR1, PR3, and PR4 can be reconfigured. Next, in S702, the functions configured in the reconfigurable partial reconstruction unit are obtained. Here, function A, function C, and function D are shown. The process up to this point is the same as in the first embodiment.

  In step S1103, the last use date / time corresponding to these functions is obtained from the last update date / time table 821. Finally, a partial reconfiguration unit having the oldest last use date and time is selected as S1104. Here, the last use date and time corresponding to the function A, the function C, and the function D are “2014/4/1 08:30:30, 2014/4/1 08:30:30, 2014/3/31 08:30, respectively. 0:00 ”, the partial reconfiguration unit, that is, PR4 in which the function D having the oldest use date and time is configured is selected. Here, as shown in the last update date / time table 821, the partial reconfiguration unit having no circuit function is treated as the strongest selection candidate for reconfiguration although the date / time is not specified.

  With the above selection method, the least used circuit function is reconfigured from the reconfigurable partial reconfiguration units. In other words, a circuit function that is highly likely to be reused is preserved, and the probability of proceeding to YES in the future reconfiguration necessity determination process (S504) can be increased, thereby improving the performance when viewed over a long period.

[Third Embodiment]
In the third embodiment, the number of times each circuit function configured in the partial reconfiguration unit of the FPGA 140 is used is recorded, and the least frequently used circuit function is predicted as a circuit function that is unlikely to be used in the future. It is a candidate.

FIG. 12 shows a configuration related to partial reconstruction in the third embodiment.
FIG. 12 is a block diagram illustrating the configuration of the image processing apparatus according to the present embodiment. The same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.
The difference between the present embodiment and the first embodiment is that the use count table 1221 is prepared in the HDD 117 instead of the priority order table 221 stored in the ROM 104. The numbers in the usage count table are added each time processing is performed for each circuit function. Further, by periodically resetting the value to be added, it is possible to update to a value according to the frequency at that time. An example of the details of the usage count table 1221 and the PR management table 220 is shown in FIG. The PR management table 220 is the same as in the first embodiment.

The operation flow of the fourth embodiment will be described with reference to FIG.
FIG. 13 is a flowchart showing job execution processing control of the image processing apparatus according to the present embodiment. Each procedure (step) in the flowchart of FIG. 13 is realized by the CPU 101 executing a stored control program.
This is almost the same as in the first embodiment. When a job is received, a necessary circuit function is specified and it is not in the partial reconfiguration unit, or even if it is used by another job, the reconfiguration is performed in S1305 However, the selection process is the difference. In addition, after performing processing such as image processing and compression / decompression using a circuit configured in the partial reconfiguration unit, the number of times of use of the corresponding circuit function in the number-of-uses table 1221 is incremented by 1 and updated in S1310.

Next, the process of S1305 as a difference will be described with reference to FIG.
FIG. 15 is a flowchart illustrating job execution process control of the image processing apparatus according to the present exemplary embodiment. This example corresponds to the detailed procedure of S1305 shown in FIG. Each procedure (step) in the flowchart of FIG. 15 is realized by the CPU 101 executing a stored control program.
First, in step S <b> 701, the CPU 101 refers to the PR management table 220. For example, when the PR management table 220 and the usage count table 1221 are in the state shown in FIG. 14, the CPU 101 first refers to the PR management table 220 and extracts a reconfigurable partial reconfiguration unit. Here, it can be seen that PR1, PR3, and PR4 can be reconfigured. Next, in S702, the functions configured in the reconfigurable partial reconstruction unit are obtained. Here, function A, function C, and function D are shown. The process up to this point is the same as in the first embodiment.

  In step S <b> 1503, the CPU 101 obtains the usage count corresponding to these functions from the usage count table 1221. Finally, in S1504, the partial reconstruction unit having the smallest number of uses is selected. Here, since the number of uses corresponding to the function A, the function C, and the function D is “50, 32, 29”, respectively, the partial reconfiguration unit in which the function D having the smallest number of use (29) is configured, that is, PR4 Is selected. Here, the partial reconfiguration unit in which the circuit function is not configured is defined as 0 times as shown in the use count table 1221 and is treated as the strongest selection candidate for reconfiguration.

  With the above selection method, the least frequently used circuit function is reconfigured from the reconfigurable partial reconfiguration units. In other words, a circuit function that is highly likely to be reused is preserved, and the probability of proceeding to YES in the future reconfiguration necessity determination process (S504) can be increased, thereby improving the performance when viewed over a long period.

[Fourth Embodiment]
In the above embodiment, when the necessary circuit function has already been configured on the partial reconfiguration circuit, the reconfiguration has not been performed. However, depending on the job contents and the circuit function, it may be assumed that the performance is improved by adapting to changes in the usage state in which a plurality of partial reconfiguration units having the same circuit function perform parallel processing.

For example, taking a SEND job as an example, in the SEND job, image data read by the scanner unit 109 and subjected to image processing for reading is JPEG-compressed and transmitted to an external general-purpose computer (not shown) via the network I / F 102. .
When JPEG compression is performed on this image data, compression processing is required for each color component (R, G, B). Here, it is possible to reduce the overall compression processing time by executing the compression processing for each color component in parallel.
In other words, in order to increase the speed of a single job (here, a SEND job), even if the necessary circuit is already configured in the partial reconfiguration unit, it is still unused (the status of the PR management table 220 is in the “released” state). If there is a partial reconstruction unit, it is preferable to reconfigure the JPEG function.
On the other hand, even in such a case, if importance is attached to the multi-functionality of the image processing apparatus, it is preferable to leave the unused partial reconstruction unit unused for other jobs.

Switching between parallel execution and single execution is preferably determined based on job priority, importance, and frequency of use of functions already in the unused partial reconfiguration unit. Also, the user may be able to set from the operation unit 103.
FIG. 16 shows a flowchart of such an implementation example.

FIG. 16 is a flowchart illustrating job execution process control of the image processing apparatus according to the present exemplary embodiment. This example corresponds to the detailed procedure of S1305 shown in FIG. Each procedure (step) in the flowchart of FIG. 16 is realized by the CPU 101 executing a stored control program.
The difference from the first embodiment is that, even when it is determined in S504 that the circuit necessary for the job is already in the partial reconfiguration unit, it is further determined in S1604 whether the CPU 101 performs the parallel operation. .
Therefore, if a parallel operation is necessary depending on the above-mentioned determination materials, the process proceeds to S505 to reconfigure the second circuit function. Only in this case, the execution of the circuit function in S1609 performs a parallel operation by the partial configuration circuit determined to be usable in S1604 and the partial configuration circuit reconfigured in S507 after shifting from S1604 to S505. .

  According to the present embodiment, for example, for a high priority job, many assets (partial reconfiguration units 201 to 204) of the FPGA 140 are allocated and processed at high speed. Also, for low-priority jobs, resources are saved for other jobs. That is, even when a desired circuit function is already configured in any of the partial reconfigurations 201 to 204, whether or not partial reconfiguration of the same circuit function is further performed is switched depending on the system state.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus 101 ... CPU
104 ROM
111 ... RAM
120: System bus 121: Image bus 130: Configuration controller 140: FPGA

Claims (14)

A first storage means in which a plurality of storage areas can be rewritten,
Second storage means for storing circuit configuration information associated with specific function processing;
Management means for managing the function and usage state of the circuit configuration information stored in each storage area in association with each other,
When rewriting circuit configuration information stored in one of the storage areas to other circuit configuration information based on the function to be executed, it is determined based on the use state whether the same circuit configuration information has already been configured. A determination means;
When it is determined that the same circuit configuration information has already been configured, a limiting unit that limits the circuit configuration information corresponding to the function to be executed so as not to be reconfigured,
An information processing apparatus comprising: A first storage means in which a plurality of storage areas can be rewritten,
Second storage means for storing circuit configuration information associated with specific function processing;
Management means for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
Corresponding to the function of the circuit configuration information stored in each storage area managed by the management means when rewriting circuit configuration information stored in any storage area to other circuit configuration information based on the function to be executed Control means for reconfiguring the storage area specified based on the assigned priority order with the other circuit configuration information;
An information processing apparatus comprising: A first storage means in which a plurality of storage areas can be rewritten,
Second storage means for storing circuit configuration information associated with specific function processing;
Management means for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
When the circuit configuration information stored in one of the storage areas is rewritten to other circuit configuration information based on the function to be executed, the function of the circuit configuration information stored in each storage area managed by the management unit is updated. Control means for reconfiguring the storage area specified based on the state with the other circuit configuration information;
An information processing apparatus comprising: A first storage means in which a plurality of storage areas can be rewritten,
Second storage means for storing circuit configuration information associated with specific function processing;
Management means for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
Use of the function of the circuit configuration information stored in each storage area managed by the management means when rewriting circuit configuration information stored in one of the storage areas to other circuit configuration information based on the function to be executed Control means for reconfiguring the storage area specified based on the number of times with the other circuit configuration information;
An information processing apparatus comprising: A first storage means in which a plurality of storage areas can be rewritten,
Second storage means for storing circuit configuration information associated with specific function processing;
Management means for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
Based on the function to be executed or the usage status of each storage area, whether or not the same circuit configuration information as the circuit configuration information stored in any one of the storage areas is to be written to another storage area based on the function to be executed Judgment means to judge,
If it is determined that the same circuit configuration information is further written to another storage area, the control means for reconfiguring the same circuit configuration information as the already configured circuit configuration information in another storage area;
An information processing apparatus comprising:   The information processing apparatus according to claim 1, wherein the first storage unit is a programmable field array.   The information processing apparatus according to claim 1, wherein the information processing apparatus is an image processing apparatus.   6. The information processing apparatus according to claim 1, wherein the functions to be executed include a copy job function, a print job function, a facsimile job function, and a send job function. A method for controlling an information processing apparatus, comprising: a first storage unit that can rewrite any of a plurality of storage areas; and a second storage unit that stores circuit configuration information associated with a specific function process. ,
A management process for managing the function of the circuit configuration information stored in each storage area in association with the usage state;
When rewriting circuit configuration information stored in one of the storage areas to other circuit configuration information based on the function to be executed, it is determined based on the use state whether the same circuit configuration information has already been configured. A determination process;
When it is determined that the same circuit configuration information has already been configured, a limiting step for limiting the circuit configuration information corresponding to the function to be executed so as not to be reconfigured, and
An information processing apparatus control method comprising: A method for controlling an information processing apparatus, comprising: a first storage unit that can rewrite any of a plurality of storage areas; and a second storage unit that stores circuit configuration information associated with a specific function process. ,
A management process for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
Corresponds to the function of the circuit configuration information stored in each storage area managed in the management step when rewriting circuit configuration information stored in any storage area to other circuit configuration information based on the function to be executed A control step of reconfiguring the storage area specified based on the assigned priority order with the other circuit configuration information;
An information processing apparatus control method comprising: A method for controlling an information processing apparatus, comprising: a first storage unit that can rewrite any of a plurality of storage areas; and a second storage unit that stores circuit configuration information associated with a specific function process. ,
A management process for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
When the circuit configuration information stored in one of the storage areas is rewritten to other circuit configuration information based on the function to be executed, the function of the circuit configuration information stored in each storage area managed in the management process is updated. A control step of reconfiguring the storage area specified based on the state with the other circuit configuration information;
An information processing apparatus control method comprising: A method for controlling an information processing apparatus, comprising: a first storage unit that can rewrite any of a plurality of storage areas; and a second storage unit that stores circuit configuration information associated with a specific function process. ,
A management process for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
When rewriting circuit configuration information stored in one of the storage areas to other circuit configuration information based on the function to be executed, use of the function of the circuit configuration information stored in each storage area managed in the management step A control step of reconfiguring the storage area specified based on the number of times with the other circuit configuration information;
An information processing apparatus control method comprising: A method for controlling an information processing apparatus, comprising: a first storage unit that can rewrite any of a plurality of storage areas; and a second storage unit that stores circuit configuration information associated with a specific function process. ,
A management process for managing the function and state of the circuit configuration information stored in each storage area in association with each other;
Based on the function to be executed or the usage status of each storage area, whether or not the same circuit configuration information as the circuit configuration information stored in any one of the storage areas is to be written to another storage area based on the function to be executed A determination process for determining
When it is determined that the same circuit configuration information is further written to another storage area, a control step of reconfiguring the same circuit configuration information as the already configured circuit configuration information in another storage area;
An information processing apparatus control method comprising:   A program for causing a computer to execute the control method of the information processing apparatus according to any one of claims 9 to 13.

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