JP2016057828A - Image processing device, control method of the same, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when a dynamic part reconfiguration request is generated, it is necessary to wait until the processing in any partial reconfiguration part is completed in order to decide the partial reconfiguration part to be reconfigured in the case that any processing is under execution in all the partial reconfiguration parts, and the time is required for the reconfiguration.SOLUTION: An image processing device having a circuit including a plurality of regions capable of reconfiguring a circuit configuration determines whether or not all of the plurality of regions are under operation when a reconfiguration request is generated, and when determined that all of the plurality of regions are under operation, acquires all pieces of circuit configuration information corresponding to each of the plurality of regions so as to be stored in the storage part, the circuit configuration information being for mounting the designated function by the reconfiguration request, and when the processing is completed in any region among the plurality of regions, the circuit configuration information corresponding to the region completed with the processing is read from the storage part, and the reconfiguration is performed in the region completed with the processing.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a program.

  Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) capable of changing the internal logic circuit configuration are known. Generally, PLDs and FPGAs switch internal logic blocks by writing logic circuit configuration information stored in a nonvolatile memory such as a ROM to a configuration memory, which is an internal volatile memory, at startup. Information in the configuration memory is cleared when the power is turned off, and reconfiguration is performed by writing logic circuit configuration information to the configuration memory again when the power is turned on. This method of configuring hardware resources only once at startup is called static reconfiguration. On the other hand, a circuit that can change the logic circuit configuration while the circuit is operating has been developed, and such a method is called dynamic reconfiguration.

  Some FPGAs can rewrite only a specific area, not the whole, and such rewriting is called partial reconfiguration. In particular, partial reconfiguration is performed without stopping other circuits in operation. This is called dynamic partial reconfiguration. In the dynamic partial reconfiguration, the entire configuration memory is not rewritten at the time of dynamic reconfiguration, but only a part of the configuration memory area is rewritten to realize partial reconfiguration of the logic block inside the FPGA.

  In order to perform partial reconstruction, it is necessary to specify in advance an area where partial reconstruction can be performed at the time of design. An area where partial reconstruction can be performed is called a PR (Partial Reconfigurable) area or the like. In order to perform partial reconfiguration, it is necessary to prepare logic circuit configuration information dedicated to each area. For this reason, when a circuit is configured in any of a plurality of areas even with the same function, it is necessary to prepare a plurality of pieces of logic circuit configuration information suitable for each of the plurality of areas.

  A recent image processing apparatus such as an MFP (Multi Function Printer) can select a plurality of processes according to a request from a user, and the image processes corresponding to each process are realized by hardware or software. When a reconfigurable circuit such as an FPGA is applied as image processing hardware of the image processing apparatus, the circuit configuration can be dynamically and partially switched for each function. As a result, various image processing functions can be realized with few hardware resources.

  On the other hand, the time required to change (rewrite) the circuit configuration during operation is long, and the time is proportional to the size of the logic circuit configuration information written in the configuration memory. Therefore, conventionally, techniques for reducing the rewriting time of the circuit configuration have been proposed. As a conventional technique for reducing the rewriting time, a process that is likely to be processed next is predicted during image processing, and logic circuit configuration information for realizing the predicted process is preceded by a high-speed configuration memory. The technique of loading is disclosed. By loading in advance, the time until the start of processing can be shortened, and the overall speed of image processing can be increased (see, for example, Patent Document 1).

JP 2012-234337 A

  In order to specify the logic circuit configuration information used in the partial reconfiguration, it is necessary to determine a desired processing content and to specify an area to be reconfigured. However, since the method described in Patent Document 1 does not consider the area to be reconfigured, it cannot be applied to a partially reconfigurable device having a plurality of rewritable areas. In particular, when a reconfiguration request occurs, if some process is being executed in all areas, it is necessary to wait until the process in any area is completed in order to determine the area to be reconfigured. The reconstruction time cannot be shortened.

  In order to solve the above problems, the present invention has the following configuration. That is, an image processing apparatus including a circuit including a plurality of regions in which a circuit configuration can be reconfigured, the control unit controlling the reconfiguration of the circuit configuration in each of the plurality of regions, and corresponding to each of the plurality of regions. And storage means for temporarily storing at least one circuit configuration information used when reconfiguring the plurality of areas from among a plurality of circuit configuration information defined for each function; and Determination means for determining whether or not each of the plurality of areas is operated by a function of a configured circuit configuration, and when the reconfiguration request is generated, all of the plurality of areas are included in the determination means. If it is determined whether or not all of the plurality of areas are in operation by the determination unit, the storage unit implements the function specified in the reconfiguration request of All of the circuit configuration information corresponding to each of the plurality of areas is acquired and stored in the storage unit, and the control means performs processing in any one of the plurality of areas. Is completed, the circuit configuration information corresponding to the area where the process is completed is read from the storage unit, and reconfiguration is performed in the area where the process is completed.

  According to the present invention, even if it is uncertain which region can be reconfigured because a reconfiguration request is generated during operation of all the regions having a plurality of regions that can be partially reconfigured. Therefore, the reconstruction time can be shortened and the processing speed can be increased.

The figure which shows the hardware structural example of the image processing apparatus which concerns on this invention. The figure which shows the example of the structure in connection with the dynamic partial reconstruction which concerns on this invention. The figure which shows the structural example of the configuration data which concerns on this invention. The flowchart of the control process of the dynamic partial reconstruction which concerns on 1st embodiment. The figure which shows the structural example of the PR area | region management table which concerns on 1st embodiment. The figure for demonstrating the operation state and effect which concern on this invention. The figure which shows the structural example of the management information which concerns on 2nd embodiment. The flowchart of the control process of the dynamic partial reconstruction which concerns on 2nd embodiment. The figure which shows the structural example of the management information which concerns on 3rd embodiment. The flowchart of the control process of the dynamic partial reconstruction which concerns on 3rd embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<First embodiment>
[Configuration of image processing apparatus]
FIG. 1 is a diagram illustrating an apparatus configuration example of an image processing apparatus according to the present embodiment. The image processing apparatus 100 according to the present embodiment includes an operation unit 103, a scanner unit 109, and a printer unit 107. The operation unit 103 is used when a user using the image processing apparatus 100 performs various operations. The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp for reading a document, a scanning mirror (not shown), and the like, and reads image information in accordance with an instruction from the operation unit 103. The printer unit 107 includes a CPU (not shown) that controls the printer unit 107, a photosensitive drum for performing image formation and fixing, a fixing device (not shown), and the like, and prints image data on paper.

  The image processing apparatus 100 includes a CPU 101, a ROM 104, and a RAM 111. The CPU 101 comprehensively controls the operation of the image processing apparatus 100 and executes control software for controlling each unit of the image processing apparatus 100. The ROM 104 stores a program executed by the CPU 101. The RAM 111 is a volatile storage unit and is used for various purposes. For example, the RAM 111 is a system work memory for the operation of the CPU 101, an image memory for temporarily storing image data, and a memory for temporarily storing logic circuit configuration information described later. The RAM 111 is connected to a memory controller 110 that controls writing and reading operations to the RAM 111. The memory controller 110 is connected to the system bus 120 and the image bus 121 and controls access to the RAM 111. A RAM 111 that can read and write at a higher speed than the HDD 150 is used.

  The image processing apparatus 100 includes an FPGA 140 that constitutes an image processing circuit or the like as a reconfigurable device. In the present embodiment, an FPGA is described as an example of a reconfigurable device. However, a configuration in which a reconfigurable device other than an FPGA is connected may be used. The image processing apparatus 100 includes a configuration controller 130 that controls the circuit configuration (configuration) of the FPGA under the control of the CPU 101. In the present embodiment, the configuration controller 130 is shown in the form of a hardware module, but a different mounting method may be used. For example, it may be realized as software that operates on the CPU 101.

  The image processing apparatus 100 also includes an HDD 150 in which logic circuit configuration information (hereinafter referred to as configuration data) for configuring a circuit in the FPGA 140 is stored. The HDD 150 is a storage area for storing not only configuration data but also image data, and also a storage area for storing a program operating on the CPU 101. The HDD 150 is connected to the system bus 120 and the image bus 121 via the HDD I / F 116. The HDD I / F 116 is often inferior in reading performance (access speed) to the RAM 111 already described. The FPGA 140 is dynamically rewritable and partially rewritable. That is, while a circuit configured as a part of the reconfiguration unit of the FPGA 140 is operating, another circuit can be reconfigured in another part that does not overlap with the part occupied by the circuit.

  The image processing apparatus 100 also includes a scanner I / F 108 to which image data is input from the scanner unit 109 and a printer I / F 106 that outputs image data to the printer unit 107. The FPGA 140, the scanner I / F 108, and the printer I / F 106 are connected to an image bus 121 for transferring image data to be processed.

  The image processing apparatus 100 communicates (transmits / receives) with a general-purpose computer (not shown) on the network via the network I / F 102. The image processing apparatus 100 communicates (transmits / receives) with a USB device (not shown) connected to the image processing apparatus 100 via the USB I / F 114. Further, the image processing apparatus 100 is connected to a public network via a FAX I / F 115, and communicates (transmits / receives) with other image processing apparatuses and facsimile apparatuses (not shown). The image processing apparatus 100 includes a ROM I / F 112 that controls writing and reading operations to the ROM 104. In the image processing apparatus 100, the CPU 101, the network I / F 102, the operation unit I / F 113, the ROM I / F 112, the HDD I / F 116, the memory controller 110, the configuration controller 130, and the FPGA 140 are mutually connected via the system bus 120. Connected to. The CPU 101 transmits and receives various types of information via the FPGA 140 and the system bus 120. In the present embodiment, the image processing apparatus is described as an example. However, the present invention is not limited to this, and may be another information processing apparatus including a circuit that can be partially reconfigured.

[Configuration related to partial reconfiguration]
With reference to FIG. 2, a configuration related to partial reconstruction of the configuration of the image processing apparatus 100 according to the present embodiment illustrated in FIG. 1 will be described. The CPU 101, memory controller 110, RAM 111, configuration controller 130, HDD I / F 116, HDD 150, and FPGA 140 are as described above with reference to FIG.

  The FPGA 140 includes a plurality of partial reconstruction units inside as a unit for partial reconstruction. In the present embodiment, the FPGA 140 includes a PR region 201 (PR1), a PR region 202 (PR2), a PR region 203 (PR3), and a PR region 204 (PR4). In each PR region, the image processing circuit or the like can be dynamically rewritten. In this embodiment, an example in which a circuit having an image processing function is configured in the PR region has been described. However, a circuit other than the image processing function may be configured in the PR region.

  The configuration controller 130 includes a reconfiguration management unit 205. The reconfiguration management unit 205 has a function of managing partial reconfiguration of each PR area. For example, the availability of each PR area is managed, such as whether each PR area is used for the current process or whether a function is written. After that, the reconfiguration management unit 205 determines whether or not each PR area can be rewritten. The reconfiguration management unit 205 loads the configuration data usable in each PR area into the RAM 111 and configures the configuration in each PR area based on the instruction from the CPU 101 and the determination as to whether or not each PR area can be rewritten. Rewrite data. Processing when the reconfiguration management unit 205 determines that some processing is being executed in all PR regions will be described later with reference to FIG.

  Next, a method for storing configuration data configured in the PR areas 201 to 204 of the FPGA 140 according to this embodiment will be described with reference to FIG. FIG. 3 is an example of configuration data corresponding to the PR areas 201 to 204 of the FPGA 140 stored in the HDD 150.

  The HDD 150 defines and stores a plurality of configuration data necessary for partial reconfiguration. In FIG. 3, configuration data 300 for PR1 represents configuration data that can be configured in the PR region 201 (PR1). FIG. 3 shows an example in which there are six functions A, B, C, D, E, and F that can be configured in the PR region 201 (PR1). The configuration data 301 is configuration data for configuring a function A circuit in PR1. Similarly, the configuration data 302 to 306 represent configuration data for configuring the circuit configurations of the functions B to F in PR1, respectively.

  The configuration data 310 for PR2 represents configuration data that can be configured in the PR region 202 (PR2). The configuration data 310 for PR2 also stores configuration data for six functions A, B, C, D, E, and F, and is configured by switching the six functions in the PR area 202 (PR2). It is possible. The configuration data 320 for PR3 represents configuration data that can be configured in the PR region 203 (PR3). The configuration data 320 for PR3 also stores configuration data for six functions A, B, C, D, E, and F, and is configured by switching the six functions in the PR area 203 (PR3). It is possible. The configuration data 330 for PR4 represents configuration data that can be configured in the PR region 204 (PR4). The configuration data 330 for PR4 also stores configuration data for six functions A, B, C, D, E, and F, and is configured by switching the six functions in the PR area 204 (PR4). It is possible.

  As described above, it is necessary to prepare configuration data for each PR region as a premise of the present invention. For example, in order to configure the circuit configuration of the function A in the PR region 201 and the PR region 202, different configuration data corresponding to the configuration location (here, the configuration data 301 of the function A for PR1 and the function for PR2) It is necessary to prepare configuration data 311) for A. Therefore, when multi-functional processing is performed on the FPGA 140, a large-capacity storage such as the HDD 150 is prepared, and by holding configuration data for each partial reconfiguration area, each partial reconfiguration area is flexible. Can be used. Note that the large-capacity storage does not need to be incorporated in the image processing apparatus 100, and may be realized so as to be provided outside the image processing apparatus 100 and to communicate with the image processing apparatus 100 through the network I / F 102 or the like.

  In the present embodiment, as shown in FIG. 2, the FPGA 140 includes four partial reconstruction areas, and the functions configured in the partial reconstruction areas are six cases of functions A, B, C, D, E, and F. Will be described as an example. Of course, the number of partial reconfiguration regions and the number of functions that can be configured are not limited to the above, and the present invention can be applied to other numbers.

[Control flow during reconfiguration]
FIG. 4 is a flowchart showing control at the time of reconfiguration of the image processing apparatus 100 according to the present embodiment. Note that each procedure in the flowchart of FIG. 4 is described as being executed by the CPU 101 included in the image processing apparatus 100, but a part of the processing may be performed by the reconfiguration management unit 205.

  In step S401, the CPU 101 receives a job set by a user or the like. That is, a processing start request in the image processing apparatus 100 is accepted. Here, a job other than the user may be set.

  In step S402, the CPU 101 specifies functions necessary for executing the job received in step S401. Furthermore, the CPU 101 specifies functions that need to be configured in the FPGA 140. For example, it is specified that a circuit for realizing the function E needs to be configured in the PR area for the received job processing. Of course, other functions may be reconfigured, and functions not shown in FIG. 3 may be reconfigured. Further, it may be specified that a plurality of functions are necessary.

  In step S <b> 403, the CPU 101 acquires a status indicating the operation state of each PR area from the reconfiguration management unit 205. The status indicating the operation state of each PR area managed by the reconfiguration management unit 205 will be described later with reference to FIG. Here, when the functions necessary for executing the job are already configured, the reconfiguration may not be performed. In the present embodiment, it is assumed that a necessary function is not configured at this time, and a function to be reconfigured is designated by a reconfiguration request.

  In S404, the CPU 101 determines whether there is an empty PR area in which the circuit has not been written, based on the information acquired in S403. If there is an empty PR area (YES in S404), the process proceeds to S413. If there is no empty PR area (NO in S404), the process proceeds to S405.

  In step S405, the CPU 101 determines whether there is one or more PR regions for which processing has been completed based on the information acquired in step S403. If at least one PR region has been processed (YES in S405), the process proceeds to S413. If any process is being executed in all PR regions (NO in S405), the process proceeds to S406.

  In S406, the CPU 101 instructs the configuration controller 130 to read the configuration data for realizing the function specified in S402 for all the PR areas. Upon receiving the instruction, the configuration controller 130 loads configuration data from the HDD 150 to the RAM 111. As described with reference to FIG. 3, the configuration data is prepared for each PR region, and there are a plurality of configuration data for realizing the same function. Note that the order of loading the plurality of configuration data may be determined in advance or may be determined randomly.

  In S407, the CPU 101 acquires the status of the operation state of each PR area from the reconfiguration management unit 205.

  In S408, the CPU 101 determines whether or not the processing in any one of the PR regions has been completed based on the information acquired in S407. If processing in any PR region has been completed (YES in S408), the process proceeds to S409. If processing is continuing in all PR regions (NO in S408), the process returns to S407.

  In step S409, the CPU 101 identifies the PR region for which processing has ended based on the information acquired in step S407.

  In S410, the CPU 101 instructs the configuration controller 130 to select configuration data that conforms to the PR area specified in S409 or S413 from the configuration data loaded in the RAM 111. The configuration data selected here is configuration data for realizing the function specified in S402.

  In S411, the CPU 101 performs partial reconfiguration by reading the configuration data selected in S410 by the configuration controller 130 from the RAM 111 and writing it in the specified PR area of the FPGA 140.

  In S412, the CPU 101 starts execution of the process specified in S402 by the function partially reconfigured in S411.

  In step S413, the CPU 101 identifies an unused PR region based on the information acquired in step S403. In the present embodiment, when a reconfiguration request is made, an area that can be written immediately is referred to as an “unused PR area”, and is distinguished from the PR area that is specified as being writable because the processing is completed in S409.

  In S414, the CPU 101 specifies configuration data that can be written to the unused PR area specified in S413. Specifically, the configuration data corresponding to the unused PR area specified in S413, the configuration data corresponding to the function specified in S402 is stored in the storage area where the configuration data exists, such as the RAM 111 and the HDD 150. It is searched from.

  In S415, the CPU 101 determines whether or not the target configuration data is in the RAM 111 as a result of the search in S414. If the target configuration data is in RAM 111 (YES in S415), the process proceeds to S410. If the target configuration data is not in RAM 111 (NO in S415), the process proceeds to S416.

  In S416, the CPU 101 instructs the configuration controller 130 to load the configuration data specified in S414 from the HDD 150 to the RAM 111. Thereafter, the process proceeds to S410.

  An example of a method for determining the operation state of each PR region described in FIG. 4 will be described with reference to FIG. In the present embodiment, description will be made assuming that the reconfiguration management unit 205 has a PR area management table 500 indicating the operation state of the PR area. The PR area management table 500 includes a function corresponding to the configuration data written in each PR area, and the operation status of the function. These pieces of information are updated under the control of the reconfiguration management unit 205 or the CPU 101. For example, when the CPU 101 controls the configuration controller 130 to perform partial reconfiguration and instructs the start of processing, the operation state for the relevant PR region in the PR region management table 500 is set to “in operation”. Further, when the processing in the PR region is completed, the operation state is set to “operation completed” or the like. Note that the status type indicating the operation state may be set according to the function. When the configuration data written in the PR area is changed, a function corresponding to the changed configuration data is indicated. Thus, it is possible to determine which function is configured in which PR region and what the operation state of the function is. The operation state determination method is not limited to the above, and may be managed by other methods.

[effect]
Next, referring to FIG. 6, the specific operation of the present embodiment will be described, and the effects according to the present invention will be described. FIG. 6 is a time chart in which the operation contents of each PR region and the operation contents of the configuration controller 130 are arranged in time series when the flowchart shown in FIG. 4 is executed. In FIG. 6, the horizontal axis indicates the passage of time, and PR1, PR2, PR3, and PR4 that are PR regions according to the present embodiment, and the operation contents in the configuration controller 130 are arranged in time series. Function PR is configured in PR1, function B is configured in PR2, and function C is configured in PR3 and 4, indicating that processing is being performed in each PR region. Here, a function newly requested for partial reconfiguration will be described as function E.

  At the reconfiguration start request timing 601, the operation status is determined (S 404 and S 405 in FIG. 4), and it is determined that the process is being executed in all the PR regions (NO in S 405). Then, under the control of the CPU 101, the configuration controller 130 loads configuration data corresponding to each PR area of the function E from the HDD 150 to the RAM 111 (S406). After the configuration data load end timing 602, the process waits for the processing end timing in one of the PR areas while confirming the operation status of each PR area (S407, S408). Then, at the timing when the processing is completed in any PR region (here, the timing 603 when the processing by the function C of PR4 is completed) (YES in S408), the terminated PR region is specified (S409). Thereafter, reconfiguration is performed on the PR region using configuration data corresponding to the PR region (PR4 in this case) loaded in the RAM 111.

  As described above, according to the present embodiment, by reading the configuration data for all the PR areas into the RAM before the process is completed, partial reconfiguration can be performed immediately after the process in one of the PR areas is completed. It becomes. On the other hand, when the configuration of the present invention is not applied, the configuration data is loaded and reconfigured corresponding to the PR region for which the processing is completed after the processing end timing is reached. In other words, when the present invention is implemented, when a reconfiguration request occurs, some processing is being executed in all PR regions, and it is undecided in which PR region the next function should be reconfigured However, it is possible to shorten the reconstruction time.

<Second Embodiment>
In the first embodiment, even when processing is being executed in all PR areas when a reconfiguration request is generated, the reconfiguration time is obtained by reading the configuration data for all PR areas into the RAM in advance. Explained that can be shortened.

  In the second embodiment, considering the timing at which the processing in the PR region ends, the configuration data for the PR region that is predicted to be the earliest timing to end is loaded in order. As a result, even when processing in any one of the PR regions is completed before the loading of all the configurations is completed, it is possible to efficiently perform the reconfiguration and shorten the reconfiguration time.

[Configuration according to the second embodiment]
In the present embodiment, the processing end timing in the PR region is predicted and calculated in advance. FIG. 7A shows an example of a PR region management table 700 configured to further include information on the calculated processing end timing. In consideration of the processing end timing in each PR area held in the PR area management table 700, the order of the configuration data to be read is controlled. The apparatus configuration of the image processing apparatus according to the present embodiment is assumed to be the same as that of the first embodiment, and description thereof is omitted here.

  The PR area management table 700 shown in FIG. 7A includes the function corresponding to the configuration data written in each PR area, the operation status of the function, and the end time of the process being executed in each PR area. Consists of. For example, in FIG. 7A, the function A (reading image processing) written in PR1 is “operating”, and the processing end time is managed as “15:00”. Such information is held for each PR region. Under the control of the CPU 101, after the configuration controller 130 partially reconfigures the FPGA 140, the PR region management table 700 is updated at the timing when processing is started in the PR region, and the processing end time is acquired. Note that the update timing of the PR region management table 700 is not limited to the above timing. The operation of the PR area management table 700 may be realized as software operating on the CPU 101 or may be realized as being performed by the reconfiguration management unit 205.

  Next, an example of an end time acquisition method will be described. The time until a series of processes occupying the hardware may be predictable. For example, when image processing is performed on one piece of image data, the time required for image processing can be calculated from the amount of data included in the image data and the throughput performance of the image processing apparatus. Considering this result and the process start time, the process end time can be calculated. By holding this result in the PR area management table 700, it is possible to obtain the processing end order in each PR area when a reconfiguration request occurs. The method for obtaining the processing end time is not limited to the above method, and predetermined values may be stored as a table, or various other processing time calculation methods may be used.

  On the other hand, it may be difficult to accurately predict the end time. For example, the image processing apparatus 100 can copy a document. There are widely known methods for copying originals by manually scanning one by one and methods for automatically copying a plurality of originals using an auto document feeder (ADF). Whether you want to manually scan one by one or make a copy, or use ADF to automatically scan and copy multiple originals, you can accurately determine how many originals you want to scan before starting the process. Difficult to get into. However, when copying by manually scanning, generally, there is an interval between scans of the original, and therefore the end time can be estimated as the end time by scanning one original and copying. For example, the average required time when a plurality of copies are made may be obtained in advance as the time required for this copy. On the other hand, in the case of copying using ADF, it is generally difficult for the user to accurately obtain how many originals to scan before starting the process, and a plurality of originals are continuously collected with a short time interval. Scanned. Therefore, it is not easy to estimate the processing time and the end time. When it is difficult to estimate the end timing of processing by the apparatus, the end time is set so as to end the latest among the simultaneously executed functions as shown in FIG. It is conceivable to set the required maximum processing time as the end time. In addition, for a process of a specific type or a specific setting, an end time may be determined according to a relationship with a process that is operating in another PR region, or the end time may be determined using a predetermined processing time. You may decide.

  FIG. 7B shows a load order list 710 of configuration data determined in consideration of the processing end time in each PR area held in the PR area management table 700. Here, as a method for determining the load order of the configuration data, it is determined that the configurable config data is loaded in the order of the PR region with the earlier processing end time. As described above, for a process for which it is difficult to estimate the process end time, an operation such as making the load order last may be performed as shown in FIG. The load order list 710 may be managed by the reconfiguration management unit 205 or may be managed by software operating on the CPU 101. The reconfiguration management unit 205 executes loading according to the order stored in the load order list 710 when loading the configuration data corresponding to each PR area into the RAM 111 under the instruction of the CPU 101.

[Partial reconstruction control flow considering end time]
FIG. 8 shows a job execution process of the image processing apparatus according to the present embodiment using a method of loading from the configuration data for the PR area with the earliest end timing in consideration of the timing when the process in the PR area ends. It is a flowchart showing control. Note that the processing other than S801 to S807 is the same as the processing of the flowchart of FIG. 4 that has already been described in the first embodiment, and thus description of the overlapping portions is omitted.

  If there is no PR area for which processing has been completed (NO in S405), in S801, the CPU 101 acquires the processing end time in each PR area from the PR area management table 700. The method for calculating the processing end time is, for example, as already described in the description of FIG.

  In step S802, the CPU 101 determines the order of configuration data to be loaded into the RAM 111 based on the processing end time acquired in step S801, and generates a load order list 710. As already described, even when the same function is realized by partial reconfiguration, it is necessary to prepare different configuration data depending on the configuration location. In this embodiment, the RAM 111 is preferentially loaded from the configuration data corresponding to the PR region where the processing is predicted to be completed earliest. As a result, the probability that reconfigurable configuration data exists in the RAM 111 is further increased even when the circuit configuration information is being downloaded when the processing in any PR region is completed. it can.

  In S803, the CPU 101 instructs the configuration controller 130 to load the Xth configuration data into the RAM 111 based on the order determined in S805. Note that the initial value of the variable X is “1”, and the load order list 710 is the first, second,. . . And

  In step S <b> 407, the CPU 101 acquires the status of the operation state of all PR areas from the reconfiguration management unit 205.

  In S408, the CPU 101 determines whether or not the processing in any one of the PR regions has been completed based on the information acquired in S407. If processing in any PR region has been completed (YES in S408), the process proceeds to S409. If processing is continuing in all PR regions (NO in S408), the process proceeds to S804.

  In step S <b> 804, the CPU 101 determines whether all configuration data has been loaded into the RAM 111. If it has been loaded (YES in S804), the process returns to S407 and waits until the processing in any PR region is completed. If all the configuration data has not been loaded (NO in S804), the process proceeds to S805.

  In S805, the CPU 101 sets the configuration data to be loaded in the next order (X + 1) of the current configuration data to be loaded in accordance with the order managed in the load order list 710 of the configuration data. To be loaded.

  In step S409, the CPU 101 identifies the PR region that is determined to have been processed in step S408.

  In step S806, the CPU 101 acquires a list of configuration data (not shown) that has been loaded into the RAM 111. The list of loaded configuration data may be acquired by searching the configuration data in the RAM 111, or may be stored in advance by other methods.

  In step S807, the CPU 101 compares the loaded configuration data list acquired in step S806 with the PR area specified in step S409, and determines whether or not reconfigurable configuration data has been loaded in the RAM 111. If already loaded (YES in S807), the process proceeds to S410. If not loaded (NO in S807), the process proceeds to S416. An example of the case where the load has not been completed is a case where the time until the end of processing in one of the PR areas is shorter than the time required to load the configuration data when a reconfiguration request occurs.

  In the present embodiment, the determination process of S807 is added as a condition for performing the process of S416. That is, even in the case where the processing in one of the PR regions is completed before the loading is completed, this step is performed and necessary configuration data is loaded into the RAM 111.

  According to the present embodiment, even when the processing in the PR area is completed before the loading of all the configuration data is completed, it is possible to efficiently perform the reconfiguration and shorten the configuration time. That is, configuration data that is likely to be used for partial reconstruction is preferentially loaded by determining the load order of configuration data in consideration of the processing end time in all partial reconstruction areas. As a result, in addition to the effects of the first embodiment, the time from completion to completion of reconfiguration can be shortened even if processing in any PR region is completed without loading all configuration data. It becomes.

<Third embodiment>
In the first and second embodiments, when a reconfiguration request is generated, configuration data corresponding to a desired function is prepared for all the PR areas, so that after processing in one of the PR areas is completed. Explained that the time to complete reconfiguration can be shortened. In the third embodiment, in a system in which the RAM space that can be used to store configuration data is limited, the number of configuration data corresponding to one function that can exist simultaneously on the RAM is limited, thereby efficiently re-storing. A configuration that can be configured will be described.

[Partial reconstruction considering RAM capacity]
In general, in a device such as an image processing apparatus, RAM resources are often limited mainly from the viewpoint of cost. As already described in the first embodiment, the RAM is a temporary storage device in which various processes are allocated to the storage area, and the resources allocated to each function are smaller than all the resources included in the RAM. Become. On the other hand, partial reconfiguration has the property that it is necessary to prepare different configuration data depending on the configuration location (PR region), and therefore it tends to occupy the storage region. In such a system, by limiting the number of configuration data that can exist in the RAM, partial reconfiguration can be performed without occupying resources. In addition, by performing such control, it is possible to prepare configuration data corresponding to a plurality of functions even if resources are limited. Therefore, even when a plurality of reconfiguration requests are generated, desired configuration data can be prepared in the RAM before the processing in the PR area is completed. The device configuration according to this embodiment is the same as that of the first and second embodiments, and a description thereof is omitted here.

  A method of calculating the number of config data that can be loaded when the capacity of the RAM 111 that can be used to hold the config data is 20 MB will be described with reference to FIG. Note that the capacity of RAM that can be used to hold configuration data is not limited to 20 MB.

  FIG. 9A shows a configuration example of a configuration capacity table 800 that holds the capacity of each configuration data. In the configuration capacity table 800, for example, the capacity of the configuration data for function A is 3 MB. Similarly, configuration data for each function and its size are stored in association with each other.

  FIG. 9B shows a configuration example of a load availability information table 810 that holds a determination result as to whether or not a function for which a reconfiguration request is currently generated can be loaded. In FIG. 9B, the functions for which reconfiguration requests are generated are arranged in the order in which the requests are generated. In the load availability information table 810, the size of the configuration data corresponding to each function, the maximum load number information for each configuration data, the number of loaded data, the remaining capacity information of the RAM 111 after loading, and information indicating whether or not the current load is possible Are stored in association with each other. The load availability information table 810 may be updated with some action that changes the table element as a trigger when a reconfiguration request occurs or when the number of loaded configuration data changes. It may be updated as an opportunity.

  Next, an example of a method for determining whether or not loading is possible will be described. Here, for simplification of description, an image processing apparatus in which the maximum number of each configuration data is set in advance will be described as an example. In order to determine whether or not to load, the remaining capacity of the RAM 111 after loading the configuration data is calculated from the current remaining capacity information of the currently available RAM 111 and the size of the configuration data to be loaded. If the remaining capacity of the RAM 111 after loading the configuration data is 0 or more, it is determined that loading is possible, and otherwise, it is determined that loading is impossible. This is performed in the order of functions in which a reconfiguration request has occurred. In FIG. 9B, the remaining capacity of the RAM 111 when the configuration data corresponding to the second reconfiguration request is loaded is 8 MB, and the configuration data up to this point can be loaded. On the other hand, when loading configuration data corresponding to the third reconfiguration request, the data size exceeds the remaining capacity, so it is determined that the load is impossible.

  In the above example, the image processing apparatus has been described with the maximum number of configuration data as a fixed value. However, the maximum number may be dynamically changed. For example, when there is only one reconfiguration request, the maximum capacity of the RAM set for holding configuration data can be held as an upper limit. When a new reconfiguration request is generated, the maximum number is updated so that two types of configuration data can be loaded. If the update is repeated, the maximum number may be less than the number of configuration data already loaded. In that case, the configuration data loaded last (configuration data with the lowest priority) may be deleted. In the above description, the method for limiting the maximum number of configuration data that can be loaded into the RAM has been described with two examples. However, other methods may be used.

[Partial reconfiguration control flow with a limited number of loadable configurations]
FIG. 10 is a flowchart showing the control processing of the image processing apparatus according to the present embodiment, which imposes a limit on the number of configuration data that can exist in the preset RAM 111. Since steps other than S1001 to S1005 have already been described in the above-described embodiment, description of overlapping portions will be omitted.

  If there is no PR area for which processing has been completed (NO in S405), in S1001, CPU 101 determines which PR area is to be loaded with configuration data. Any determination method may be applied. For example, using the method described in the second embodiment, it is conceivable to load a PR region whose processing end is early from reconfigurable configuration data.

  In step S1002, the CPU 101 acquires information held in the load availability information table 810 illustrated in FIG. Information acquired here includes whether or not configuration data for which a reconfiguration request has been issued can be loaded, the maximum number of loadable configurations, and the number of configuration data that have been loaded. The load availability information table 810 is continuously updated at a predetermined timing.

  In step S1003, the CPU 101 determines whether or not configuration data loading can be started based on the information acquired in step S1002. If it is determined that loading is possible (YES in S1003), the process proceeds to S803. If it is determined that loading is not possible (NO in S1003), the process proceeds to S407.

  In step S <b> 803, the CPU 101 instructs the configuration controller 130 to load the Xth configuration data that is currently loaded in accordance with the loading order determined in step S <b> 1001.

  In S805, the CPU 101 changes the load target to the next configuration data (X + 1), and proceeds to S407.

  If it is determined that the processing has not been completed in all the PR regions (NO in S408), in S1004, the CPU 101 refers to the information acquired in S1002 and the number of configuration data already loaded and the maximum load is possible. Compare the numbers and determine whether or not the maximum loadable number of configuration data has been loaded. If the number of loaded configuration data is equal to or greater than the maximum loadable number (YES in S1004), the process proceeds to S407. If smaller than the maximum loadable number (NO in S1004), the process proceeds to S1002.

  According to the present embodiment, dynamic partial reconfiguration can be efficiently performed even in an image processing apparatus in which the RAM space that can be used for holding configuration data is limited. That is, in the partial reconfiguration that easily occupies the storage area, the partial reconfiguration can be performed without occupying the storage resource by limiting the number of configuration data that can exist in the RAM. By performing such control, it becomes possible to prepare configuration data for a plurality of functions even if resources are limited. Therefore, even when a plurality of reconfiguration requests are generated, desired configuration data can be prepared in the RAM before the processing in the PR area is completed.

<Other embodiments>
The present invention is also realized by executing the following processing. That is, software (program) for realizing the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus, 101 ... CPU, 104 ... ROM, 111 ... RAM, 120 ... System bus, 121 ... Image bus, 130 ... Configuration controller, 140 ...・ FPGA, 150 ... HDD

Claims (11)

An image processing apparatus including a circuit including a plurality of regions in which a circuit configuration can be reconfigured,
Control means for controlling reconfiguration of the circuit configuration in each of the plurality of regions;
Temporarily store at least one circuit configuration information used when reconfiguring the plurality of regions from a plurality of circuit configuration information corresponding to each of the plurality of regions and defined for each function. Storage means for storing
Determination means for determining whether or not each of the plurality of regions is operated by a function of a configured circuit configuration;
The determination unit determines whether or not all of the plurality of areas are operating when a reconfiguration request occurs.
When it is determined by the determination means that all of the plurality of areas are operating, the storage means is circuit configuration information for implementing the function specified in the reconfiguration request, and Acquire all circuit configuration information corresponding to each of a plurality of areas and store in the storage unit,
When the process is completed in any one of the plurality of areas, the control unit reads out circuit configuration information corresponding to the area where the process is completed from the storage unit, and sets the area where the process is completed. An image processing apparatus characterized in that reconstruction is performed. A determination means for determining an order of acquiring circuit configuration information stored in the storage unit when the reconfiguration request occurs;
The image processing apparatus according to claim 1, wherein the storage unit acquires circuit configuration information according to the order determined by the determination unit and stores the circuit configuration information in the storage unit. And further comprising an estimation means for estimating an end time at which a process in operation in each of the plurality of regions ends.
The image processing apparatus according to claim 2, wherein the determining unit determines the order so as to sequentially acquire the circuit configuration information corresponding to the region having the early end time estimated by the estimating unit.   The image processing apparatus according to claim 3, wherein the estimation unit estimates an end time according to a predefined value when a predetermined process whose end time cannot be estimated is operating in the area.   In the case where a predetermined process whose end time cannot be estimated by the estimation unit is operating in the area, the storage means sets the order in which the circuit configuration information corresponding to the area is acquired as a predefined order. The image processing apparatus according to claim 3. A limiting unit that limits the number of circuit configuration information for each function that can be stored in the storage unit when the reconfiguration request occurs;
6. The storage device according to claim 1, wherein the storage unit acquires circuit configuration information for each function based on the number limited by the limiting unit and stores the circuit configuration information in the storage unit. The image processing apparatus described.   The restricting unit dynamically determines the number of circuit configuration information for each function that can be stored according to the size of the circuit configuration information and the size of the resource of the storage unit. The image processing apparatus according to claim 6.   When the determination unit determines that the process is completed in any one of the plurality of regions while the storage unit acquires the circuit configuration information and stores the circuit configuration information in the storage unit, the process is performed. When the circuit configuration information corresponding to the area where the process is completed is already stored in the storage unit, the control unit causes the reconfiguration to be performed using the circuit configuration information already stored. Item 8. The image processing apparatus according to any one of Items 1 to 7. The storage unit is a volatile memory,
The storage means acquires circuit configuration information from a storage device whose access speed to data is slower than the storage unit when the reconfiguration request occurs, and temporarily stores the circuit configuration information. The image processing apparatus according to any one of 1 to 8. A method for controlling an image processing apparatus including a circuit including a plurality of regions in which a circuit configuration can be reconfigured,
A control step of controlling reconfiguration of the circuit configuration in each of the plurality of regions;
Temporarily store at least one circuit configuration information used when reconfiguring the plurality of regions from a plurality of circuit configuration information corresponding to each of the plurality of regions and defined for each function. A storage process to be stored in
A determination step of determining whether or not each of the plurality of regions is operated by a function of a configured circuit configuration,
In the determination step, when a reconfiguration request is generated, it is determined whether or not all of the plurality of areas are operating,
When it is determined in the determination step that all of the plurality of areas are operating, circuit configuration information for implementing the function specified in the reconfiguration request in the storage step, Acquire all circuit configuration information corresponding to each of the plurality of regions and store in the storage unit,
In the control step, when the process is completed in any one of the plurality of areas, the circuit configuration information corresponding to the area where the process is completed is read from the storage unit, and the process is completed in the area where the process is completed. And a method for controlling the image processing apparatus. A computer including a circuit including a plurality of areas in which a circuit configuration can be reconfigured.
Control means for controlling reconfiguration of the circuit configuration in each of the plurality of regions;
Temporarily store at least one circuit configuration information used when reconfiguring the plurality of regions from a plurality of circuit configuration information corresponding to each of the plurality of regions and defined for each function. Storage means for storing in
Each of the plurality of regions is made to function as a determination unit that determines whether or not it is operating by a function of a configured circuit configuration,
The determination unit determines whether or not all of the plurality of areas are operating when a reconfiguration request occurs.
When it is determined by the determination means that all of the plurality of areas are operating, the storage means is circuit configuration information for implementing the function specified in the reconfiguration request, and Acquire all circuit configuration information corresponding to each of a plurality of areas and store in the storage unit,
When the process is completed in any one of the plurality of areas, the control unit reads out circuit configuration information corresponding to the area where the process is completed from the storage unit, and sets the area where the process is completed. A computer that is configured to perform reconfiguration.

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