JP5273017B2 - Method for manufacturing flip mounted body - Google Patents

Method for manufacturing flip mounted body Download PDF

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JP5273017B2
JP5273017B2 JP2009263536A JP2009263536A JP5273017B2 JP 5273017 B2 JP5273017 B2 JP 5273017B2 JP 2009263536 A JP2009263536 A JP 2009263536A JP 2009263536 A JP2009263536 A JP 2009263536A JP 5273017 B2 JP5273017 B2 JP 5273017B2
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flip
wiring board
bare chip
underfill material
manufacturing
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JP2011108903A (en
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黒川  真一
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve productivity in the method of manufacturing of a flip mounting structure as a circuit board to which bare chips are flip-mounted. <P>SOLUTION: The method of manufacturing flip mounting structure includes a step of coating respective mounting regions of a wiring board to which a plurality of mounting regions for flip-chip mounting the bare chips are prepared with an under-fill material paste, a step of respectively conducting the pressure-bonding of the bare chips on the wiring board via the under-fill material after the alignment process and the tentative fixing of the bare chips for half-curing of the under-fill material with heat treatment to the mounting region, and a step of pressing the wiring board with a pressing means from the upper and lower directions in order to press simultaneously the plurality of bare chips on the wiring board to the wiring board side and shifting the under-fill material to the curing state from the semi-curing state through heat treatment. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、ベアチップがフリップ実装された回路基板であるフリップ実装体の製造方法に係り、特に、生産性向上に鑑みた、フリップ実装体の製造方法に関する。   The present invention relates to a method for manufacturing a flip package, which is a circuit board on which a bare chip is flip mounted, and more particularly, to a method for manufacturing a flip package in view of improving productivity.

配線板にベアチップをフリップ実装する場合、電気的、機械的な接続の信頼性を向上するため、ICチップと配線板との間に樹脂(いわゆるアンダーフィル樹脂)を充填するように設けるのが一般的である。この樹脂は、製造途上でペースト状、液状、あるいは半硬化の状態であったものが硬化されたものである。したがって、加熱などにより硬化させる工程が必須であり、単なるはんだ実装の場合より工程所要時間(タクトタイム)を要する。   When flip-mounting a bare chip on a wiring board, it is common to provide a resin (so-called underfill resin) between the IC chip and the wiring board in order to improve the reliability of electrical and mechanical connections. Is. This resin is obtained by curing a paste-like, liquid, or semi-cured state during production. Therefore, the process of hardening by heating etc. is essential, and the time required for the process (tact time) is required as compared with the case of simple solder mounting.

配線板の分野では、生産効率向上のため、近年、ひとつの基板に、同じ製品を多面付けして製造する方法が採られている。このような多面付け基板の場合、個片化する前に、それぞれの製品に対応してICチップを上記のようにフリップ実装しようにすると、その実装数に応じて、実装工程は非常に時間のかかるものとなる。実装数によっては、実用的とは言えない時間を要してしまう。   In the field of wiring boards, in recent years, in order to improve production efficiency, a method has been adopted in which a single substrate is manufactured by attaching the same product to multiple faces. In the case of such a multi-sided substrate, if the IC chip is to be flip-mounted as described above corresponding to each product before being singulated, the mounting process takes a very long time depending on the number of mounted IC chips. It becomes such a thing. Depending on the number of implementations, it may take time that is not practical.

下記、特許文献1には、マイクロウェーブにより、複数のICチップについて一度にアンダーフィル樹脂を硬化し得る方法が開示されている。これを応用すれば、多面付け基板の場合であっても、実用的な時間で多数のフリップ実装の工程を行い得ると考えられる。しかしながら、マイクロウェーブ加熱を行う装置を多数のICチップ対応とすれば専用の装置として構成する必要が生じ、ICチップの基板上へのアライメントについては従来のボンダにより対応することになる。よって、マイクロウェーブ加熱までの間にアンダーフィル材が変形することも考えられ、ICチップの実装位置ずれによる信頼性低下の心配がある。   The following Patent Document 1 discloses a method in which an underfill resin can be cured at once for a plurality of IC chips by microwaves. If this is applied, it is considered that many flip mounting processes can be performed in a practical time even in the case of a multi-sided substrate. However, if the device for performing microwave heating is compatible with a large number of IC chips, it is necessary to configure the device as a dedicated device, and the alignment of the IC chip on the substrate is handled by a conventional bonder. Therefore, it is conceivable that the underfill material is deformed before the microwave heating, and there is a concern that the reliability is lowered due to the mounting position shift of the IC chip.

また、下記、特許文献2には、フィルム状のアンダーフィル材を用いた、複数のICチップについて一度に適用し得る、アンダーフィル樹脂の硬化方法が開示されている。しかしながら、フィルム状のアンダーフィル材は、ペースト状のアンダーフィル材に比較して、高価、取り扱いが難で貼付工程に時間を要する、などの難点がある。   Patent Document 2 below discloses a method for curing an underfill resin that can be applied to a plurality of IC chips at once using a film-like underfill material. However, the film-like underfill material has disadvantages that it is expensive, difficult to handle and requires a long time for the pasting process, as compared with the paste-like underfill material.

特開2004−31902号公報(図4)Japanese Patent Laying-Open No. 2004-31902 (FIG. 4) 特開2005−32952号公報(図2)Japanese Patent Laying-Open No. 2005-32952 (FIG. 2)

本発明は、上記した事情を考慮してなされたもので、ベアチップがフリップ実装された回路基板であるフリップ実装体の製造方法において、その生産性を向上することを目的とする。   The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to improve productivity in a manufacturing method of a flip mounted body which is a circuit board on which a bare chip is flip mounted.

上記の課題を解決するため、本発明の一態様であるフリップ実装体の製造方法は、ベアチップがフリップ実装されるべき実装領域が複数用意された配線基板の前記実装領域のそれぞれにペースト状のアンダーフィル材を塗布する工程と、前記アンダーフィル材を介して前記配線基板上にベアチップを位置合わせして圧接するとともに加熱して前記アンダーフィル材を半硬化させるベアチップ仮固定を前記実装領域のそれぞれについて行う工程と、前記配線基板上の複数のベアチップを一括して該配線基板の側に押し付けるように、前記配線基板を上下からプレス手段で押圧するとともに、加熱して前記アンダーフィル材を半硬化の状態から硬化の状態に移行させる工程とを具備することを特徴とする。   In order to solve the above-described problems, a method for manufacturing a flip package according to one aspect of the present invention includes a paste-like underlayer on each of the mounting regions of a wiring board in which a plurality of mounting regions on which a bare chip is to be flip-mounted are prepared. For each of the mounting regions, a step of applying a fill material, and a bare chip temporary fixing that aligns and presses the bare chip on the wiring board through the underfill material and heats and semi-hardens the underfill material. And a step of pressing the wiring board from above and below with a pressing means so as to collectively press a plurality of bare chips on the wiring board against the side of the wiring board, and heating the semi-cured underfill material. And a step of shifting from a state to a cured state.

すなわち、この製造方法では、ペースト状のアンダーフィル材を用い、これを半硬化させるベアチップ仮固定を、配線基板上のベアチップ実装領域のそれぞれについて行う。このように半硬化の段階に留めることで、ベアチップごとにシリーズに行われる工程時間の大幅な短縮を得る。その後、配線基板上の複数のベアチップを一括してプレス手段で加圧、加熱する。これにより、アンダーフィル材を一括して半硬化の状態から硬化の状態に移行させ、フリップ実装を完了させる。実装すべきベアチップが多数あるほど、実装時間短縮の効果が高い。   That is, in this manufacturing method, a paste-like underfill material is used, and bare chip temporary fixing for semi-curing the paste is performed for each bare chip mounting region on the wiring board. By staying in the semi-curing stage in this way, a significant reduction in the process time performed in series for each bare chip is obtained. Thereafter, the plurality of bare chips on the wiring board are collectively pressed and heated by a pressing means. Thereby, the underfill material is collectively shifted from the semi-cured state to the cured state, and the flip mounting is completed. The more bare chips to be mounted, the higher the effect of shortening the mounting time.

本発明によれば、ベアチップがフリップ実装された回路基板であるフリップ実装体の製造方法において、その生産性を向上することができる。   According to the present invention, the productivity can be improved in the method of manufacturing a flip mounted body which is a circuit board on which a bare chip is flip mounted.

本発明の一実施形態に係るフリップ実装体の製造方法を適用し得る配線基板の構成の例を示す斜視図。The perspective view which shows the example of a structure of the wiring board which can apply the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention. 本発明の一実施形態に係るフリップ実装体の製造方法の適用下における、アンダーフィル材塗布後の状態を部分断面で示す構成図。The block diagram which shows the state after application | coating of an underfill material in the application of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention in a partial cross section. 本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるアンダーフィル材塗布の態様を斜視で示す工程図。The process figure which shows the aspect of the underfill material application | coating which is one process of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention with a perspective view. 本発明の一実施形態に係るフリップ実装体の製造方法の適用下における、ベアチップ仮固定後の状態を部分断面で示す構成図。The block diagram which shows the state after bare chip | tip temporary fixation under application of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention in a partial cross section. 本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるベアチップ仮固定の態様を斜視で示す工程図。The process figure which shows the aspect of the bare chip temporary fixing which is one process of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention with a perspective view. 図5に示したベアチップ仮固定の工程における、フリップチップボンダのヘッドとベアチップとの関係図。FIG. 6 is a diagram showing the relationship between the flip chip bonder head and the bare chip in the bare chip temporary fixing step shown in FIG. 5. 図2、図3中に示したアンダーフィル材における、その粘度の温度特性の例を示すグラフ。The graph which shows the example of the temperature characteristic of the viscosity in the underfill material shown in FIG. 2, FIG. 本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるアンダーフィル材硬化移行の態様を斜視で示す工程図。The process figure which shows the aspect of the underfill material hardening transfer which is one process of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention with a perspective view. 図8に示したアンダーフィル材硬化移行の工程を部分断面で示す説明図。Explanatory drawing which shows the process of underfill material hardening transfer process shown in FIG. 8 in a partial cross section. 本発明の一実施形態に係るフリップ実装体の製造方法を適用した場合のフリップ実装時間を比較例の場合のそれと対照して示す表。The table | surface which shows the flip mounting time at the time of applying the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention in contrast with the case of a comparative example. 本発明の一実施形態に係るフリップ実装体の製造方法の適用によって得られたフリップ実装体を部材に用いた部品内蔵配線板の構成を示す断面図。Sectional drawing which shows the structure of the component built-in wiring board which used the flip mounting body obtained by application of the manufacturing method of the flip mounting body which concerns on one Embodiment of this invention for a member. 図11に示した部品内蔵配線板を製造するための最終積層工程を示す工程図。FIG. 12 is a process diagram illustrating a final lamination process for manufacturing the component built-in wiring board illustrated in FIG. 11.

本発明の実施態様として、前記プレス手段が、前記ベアチップの存在する側を押圧する押圧部に第1の加熱手段を有し、前記ベアチップの存在しない側を押圧する押圧部に第2の加熱手段を有し、前記第1の加熱手段の方が前記第2の加熱手段より発熱容量が大である、とすることができる。プレス手段の押圧部に設ける加熱手段については、このように、ベアチップの存在する側を押圧する押圧部の方に大きな発熱容量を持たせるほうが、アンダーフィル樹脂への加熱がより効果的になる。ベアチップの方が配線基板より熱伝導率が高いためである。また、配線基板はベアチップより耐熱性が劣るので、この点からもこの構成が好ましい。   As an embodiment of the present invention, the pressing means has a first heating means at a pressing portion that presses the side where the bare chip exists, and a second heating means at the pressing portion that presses the side where the bare chip does not exist And the first heating means has a larger heat generation capacity than the second heating means. As for the heating means provided in the pressing part of the pressing means, the heating to the underfill resin is more effective when the pressing part that presses the side where the bare chip is present has a larger heat generation capacity. This is because the bare chip has higher thermal conductivity than the wiring board. Moreover, since the wiring board is inferior in heat resistance to the bare chip, this configuration is also preferable in this respect.

また、実施態様として、前記プレス手段が、前記ベアチップの存在する側を押圧する押圧部に加熱手段を有し、前記ベアチップの存在しない側を押圧する押圧部に加熱手段を有していない、とすることができる。これは、上記の考えを進めて、プレス手段の押圧部に設ける加熱手段をベアチップの存在する側を押圧する押圧部にのみ設けた態様である。   Further, as an embodiment, the pressing means has a heating means in a pressing portion that presses the side on which the bare chip exists, and does not have a heating means in a pressing portion that presses the side on which the bare chip does not exist. can do. This is a mode in which the above idea is advanced and the heating means provided in the pressing portion of the pressing means is provided only in the pressing portion that presses the side where the bare chip exists.

また、実施態様として、ベアチップ仮固定を前記実装領域のそれぞれについて行う前記工程が、前記アンダーフィル材が1.0×10Pa・sないし1.0×10Pa・sの粘度になるように加熱して行われる、とすることができる。この粘度は、完全に硬化する前の粘度であって、しかも、ベアチップの(仮固定の)位置合わせ状態が確実に保たれる粘度として設定したものである。 Further, as an embodiment, in the step of performing bare chip temporary fixing for each of the mounting regions, the underfill material has a viscosity of 1.0 × 10 3 Pa · s to 1.0 × 10 5 Pa · s. It can be carried out by heating. This viscosity is a viscosity before being completely cured, and is set as a viscosity that reliably maintains the (temporarily fixed) alignment state of the bare chip.

また、アンダーフィル材を塗布する前記工程が、ディスペンサを用いてなされる、とすることができる。ディスペンサを用いるのは一般的である。より効率向上を目指してディスペンサに代えスクリーン印刷のような印刷技術を用いることも可能である。   Further, the step of applying the underfill material can be performed using a dispenser. It is common to use a dispenser. It is also possible to use a printing technique such as screen printing instead of the dispenser with the aim of improving efficiency.

ここで、アンダーフィル材を塗布する前記工程が、前記ディスペンサにより前記アンダーフィル材を加温してなされる、とすることができる。これは、加温によりアンダーフィル材の初期粘度を常温の場合より下げ、より塗布しやすくして塗布効率の向上を得るものである。   Here, the step of applying the underfill material may be performed by heating the underfill material with the dispenser. This lowers the initial viscosity of the underfill material by heating to make it easier to apply and improve the application efficiency.

また、実施態様として、前記プレス手段が、前記配線基板を押圧するための耐熱樹脂製の板材を有する、とすることができる。配線基板を押圧するための板材としては、熱による変形が小さいものが好ましい。例えば、金属製、セラミック製なども考えられる。耐熱樹脂製の場合はわずかな可撓性があり硬質であるものの押圧する対象物の形状に倣いやすく、より好ましいと考えられる。   As an embodiment, the pressing means may include a heat-resistant resin plate material for pressing the wiring board. As a plate material for pressing the wiring board, one that is small in deformation due to heat is preferable. For example, a metal or a ceramic can be considered. In the case of a heat-resistant resin, although it is slightly flexible and hard, it is easy to follow the shape of the object to be pressed, which is considered preferable.

以上を踏まえ、以下では本発明の実施形態を図面を参照しながら説明する。図1は、本発明の一実施形態に係るフリップ実装体の製造方法を適用し得る配線基板の構成の例を示す斜視図である。この配線基板10は、同じ製品を多面付けして製造されたものであって、個片化する前の状態のものである。したがい、個片化ごとの領域10aが縦横に並んでとられている。   Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing an example of the configuration of a wiring board to which a method for manufacturing a flip package according to an embodiment of the present invention can be applied. This wiring board 10 is manufactured by applying the same product in multiple faces, and is in a state before being separated into individual pieces. Therefore, the area | region 10a for every singulation is taken along the length and breadth.

個片化ごとの領域10a内には、少なくともベアチップがフリップ実装されるべき実装領域がひとつ用意されている。その実装領域には、フリップ実装するための、配線パターンによるランドが形成されている。なお、図示していないが、領域10a内には、他の部品を実装するためのランドや、配線基板として通常用意される層間接続導体などを備えていてももちろんよい。このような個片化前の配線基板10を対象としてベアチップをフリップ実装することで、以下説明するように、フリップ実装体を製造する効率の向上を図る。   In the region 10a for each separation, at least one mounting region where a bare chip is to be flip-mounted is prepared. In the mounting area, a land by a wiring pattern for flip mounting is formed. Although not shown, the area 10a may be provided with lands for mounting other components, interlayer connection conductors normally prepared as a wiring board, and the like. By flip-mounting the bare chip for the wiring board 10 before being singulated as described above, the efficiency of manufacturing the flip-mounted body is improved as described below.

次に、図2は、本発明の一実施形態に係るフリップ実装体の製造方法の適用下における、アンダーフィル材塗布後の状態を部分断面で示す構成図である。図2において、図1中に示した構成要素と同一のものには同一符号を付してある。図2に示すように、まず、各領域10a中において、ベアチップがフリップ実装されるべき実装領域(配線パターン11による実装用のランドが設けられた領域)にアンダーフィル材21を塗布する。アンダーフィル材21は、ペースト状のものであり、例えば、エポキシ樹脂、フェノール樹脂、アミン樹脂などの樹脂である。樹脂中に導電微粒子を分散させて異方導電性を発揮するようにしたものを使用することもできる。   Next, FIG. 2 is a configuration diagram showing a partial cross-sectional view after applying the underfill material under the application of the flip package manufacturing method according to the embodiment of the present invention. In FIG. 2, the same components as those shown in FIG. As shown in FIG. 2, first, underfill material 21 is applied to a mounting region (a region where a land for mounting by wiring pattern 11 is provided) in which each bare chip is to be flip-mounted in each region 10a. The underfill material 21 is a paste-like material, for example, a resin such as an epoxy resin, a phenol resin, or an amine resin. A material in which conductive fine particles are dispersed in a resin to exhibit anisotropic conductivity can also be used.

図3は、本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるアンダーフィル材塗布の態様を斜視で示す工程図である。図3において、すでに説明した図中に示した構成要素と同一のものには同一符号を付してある。図3に示すように、アンダーフィル材21の配線基板10上への塗布には、ディスペンサを使用することができる。すなわち、個片化ごとの領域10aが縦横に並んでいる配線基板10を対象として、ディスペンサノズル31を移動させつつ、所定位置に所定量のアンダーフィル材21を塗布していく。   FIG. 3 is a process diagram showing perspectively an aspect of underfill material application, which is a step in the method of manufacturing a flip package according to an embodiment of the present invention. In FIG. 3, the same reference numerals are given to the same components as those already described in the drawings. As shown in FIG. 3, a dispenser can be used for applying the underfill material 21 onto the wiring substrate 10. That is, a predetermined amount of the underfill material 21 is applied to a predetermined position while moving the dispenser nozzle 31 for the wiring substrate 10 in which the regions 10a for each singulation are arranged vertically and horizontally.

アンダーフィル材21は、その粘度が通常、常温で10〜100Pa・sである。ディスペンサノズル31からの塗布の効率を向上するため、ディスペンサノズル31が数十℃に加温されるようにしてアンダーフィル材21の初期粘度を例えば10Pa・s未満にし、塗布しやすくすることも有用である(後述の図7も参照できる)。また、ディスペンサによる塗布に代えて、スクリーン印刷を用いてアンダーフィル材21を配線基板10上に塗布することもできる。効率性を考慮して選択できる。   The viscosity of the underfill material 21 is normally 10 to 100 Pa · s at room temperature. In order to improve the efficiency of application from the dispenser nozzle 31, it is also useful to make the dispenser nozzle 31 heated to several tens of degrees Celsius so that the initial viscosity of the underfill material 21 is, for example, less than 10 Pa · s, thereby facilitating application. (Also refer to FIG. 7 described later). Moreover, it can replace with application | coating by dispenser and can also apply the underfill material 21 on the wiring board 10 using screen printing. It can be selected in consideration of efficiency.

次に、図4は、本発明の一実施形態に係るフリップ実装体の製造方法の適用下における、ベアチップ仮固定後の状態を部分断面で示す構成図である。図4において、すでに説明した図中に示した構成要素と同一のものには同一符号を付してある。図3に示したアンダーフィル材21の塗布工程により図2に示した構成が得られたあと、図4に示した構成を得るべく工程を進める。   Next, FIG. 4 is a configuration diagram showing, in a partial cross section, a state after temporary fixing of the bare chip under the application of the method for manufacturing a flip package according to one embodiment of the present invention. In FIG. 4, the same components as those shown in the already described drawings are denoted by the same reference numerals. After the configuration shown in FIG. 2 is obtained by the application process of the underfill material 21 shown in FIG. 3, the process proceeds to obtain the configuration shown in FIG.

図4に示すように、この状態は、ベアチップ41がスタッド状バンプ42を介して配線パターン11によるランド上に仮固定された状態である。この時点のアンダーフィル材21Aは、アンダーフィル材21が半硬化されたもの(例えば1.0×10Pa・s〜1.0×10Pa・sの粘度)であり、完全には硬化されていない。 As shown in FIG. 4, this state is a state in which the bare chip 41 is temporarily fixed on the land by the wiring pattern 11 via the stud-like bumps 42. The underfill material 21A at this time is a semi-cured material of the underfill material 21 (for example, a viscosity of 1.0 × 10 3 Pa · s to 1.0 × 10 5 Pa · s), and is completely cured. It has not been.

図5は、本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるベアチップ仮固定の態様を斜視で示す工程図である。図6は、図5に示したベアチップ仮固定の工程における、フリップチップボンダのヘッドとベアチップとの関係図である。図5、図6において、すでに説明した図中に示した構成要素と同一のものには同一符号を付してある。   FIG. 5 is a process diagram showing in perspective a mode of bare chip temporary fixing, which is one step of the method for manufacturing a flip package according to one embodiment of the present invention. FIG. 6 is a view showing the relationship between the head of the flip chip bonder and the bare chip in the bare chip temporary fixing step shown in FIG. In FIG. 5 and FIG. 6, the same reference numerals are given to the same components as those already described in the drawings.

図5に示すように、ベアチップ41の配線基板10上へのベアチップ仮固定には、フリップチップボンダを使用することができる。すなわち、アンダーフィル材21が各実装領域に塗布された配線基板10を対象として、スタッド状バンプ42を伴うベアチップ41を吸着したフリップチップボンダヘッド51によりベアチップ仮固定する。ベアチップ仮固定が終了するたびに、新たなベアチップ41をフリップチップボンダヘッド51に吸着し、これを新たな実装領域に位置合わせし、さらにベアチップ41の配線基板10側への押し付け、加熱を行う。   As shown in FIG. 5, a flip chip bonder can be used for bare chip temporary fixing of the bare chip 41 onto the wiring substrate 10. That is, the bare chip is temporarily fixed by the flip chip bonder head 51 that sucks the bare chip 41 with the stud-like bumps 42 for the wiring substrate 10 on which the underfill material 21 is applied to each mounting region. Each time the bare chip temporary fixing is completed, a new bare chip 41 is attracted to the flip chip bonder head 51, aligned with a new mounting area, further pressed against the wiring substrate 10 side of the bare chip 41, and heated.

フリップチップボンダヘッド51による配線基板10側へのベアチップ41の押し付けは、スタッド状バンプ42ひとつ当たりに換算して例えば0.1〜1Nの押圧力とすることができる。押し付けと同時に行う加熱は、図6に示すようなフリップチップボンダヘッド51内に設けられたヒータ51a(例えばセラミックヒータ)を用いて行うことができる。このヒータ51aは、ベアチップ41を仮固定すべくアンダーフィル材21を半硬化するだけの能力を有すればよい。   The pressing of the bare chip 41 to the wiring board 10 side by the flip chip bonder head 51 can be set to a pressing force of, for example, 0.1 to 1 N in terms of one stud-like bump 42. The heating performed simultaneously with the pressing can be performed using a heater 51a (for example, a ceramic heater) provided in the flip chip bonder head 51 as shown in FIG. The heater 51a only needs to have a capability of semi-curing the underfill material 21 to temporarily fix the bare chip 41.

図7は、図2、図3中に示したアンダーフィル材における、その粘度の温度特性の例を示すグラフであり(ただし昇温速度:5℃/分)、熱硬化性樹脂一般が有する、常温での低粘度状態、高温度での硬化状態、および低粘度状態から硬化状態へ至る温度で呈する半硬化状態が、それぞれどの程度の粘度であるかを示すためのグラフである。図7に示すように、本願での半硬化状態とは、粘度が例えば1.0×10Pa・s〜1.0×10Pa・s程度の場合をいう。この粘度は、完全に硬化する前の粘度であって、しかも、ベアチップ41の仮固定の位置合わせ状態が次工程までの間、確実に保たれる粘度として設定されたものである。 FIG. 7 is a graph showing an example of the temperature characteristics of the viscosity of the underfill material shown in FIGS. 2 and 3 (however, the temperature rising rate: 5 ° C./min), which is generally possessed by thermosetting resins. It is a graph for showing how much the viscosity is in a low viscosity state at normal temperature, a cured state at high temperature, and a semi-cured state exhibited at a temperature from a low viscosity state to a cured state. As shown in FIG. 7, the semi-cured state in the present application refers to a case where the viscosity is, for example, about 1.0 × 10 3 Pa · s to 1.0 × 10 5 Pa · s. This viscosity is a viscosity before being completely cured, and is set as a viscosity that can reliably maintain the temporarily fixed alignment state of the bare chip 41 until the next step.

図7に示す特性グラフ形状は、一般に、昇温速度を上げるとグラフの立ち上がりが右側に移動するように変化する。これは、熱硬化性樹脂一般は、温度と時間との積を積算した熱量により、硬化が進むためである。図7は昇温速度が5℃/分の場合の特性であるが、実際には、時間的に、ヒータ51aの発熱温度を高めに設定し昇温速度を上げた場合、例えば数十秒程度のうちにアンダーフィル材21を半硬化のアンダーフィル材21Aに変性させることができる。   The characteristic graph shape shown in FIG. 7 generally changes so that the rising edge of the graph moves to the right as the temperature increase rate is increased. This is because, in general, thermosetting resins are cured by the amount of heat obtained by integrating the product of temperature and time. FIG. 7 shows the characteristics when the rate of temperature increase is 5 ° C./min. Actually, however, when the temperature rise rate is increased by increasing the heat generation temperature of the heater 51a, for example, about several tens of seconds. Among them, the underfill material 21 can be modified to a semi-cured underfill material 21A.

アンダーフィル材21Aのように半硬化の状態で留めるようにしてベアチップ41を仮固定することで、それぞれを完全に硬化してフリップ実装する場合より、要する時間は大幅に軽減できる。しかも、仮固定された状態は次工程まで確実に維持され、アンダーフィル材21Aが変形してベアチップ41の実装位置ずれを起こし信頼性を低下させる心配もない。   By temporarily fixing the bare chip 41 so as to be kept in a semi-cured state like the underfill material 21A, the time required can be greatly reduced as compared with the case where each is completely cured and flip-mounted. In addition, the temporarily fixed state is reliably maintained until the next process, and there is no fear that the underfill material 21A is deformed and the mounting position of the bare chip 41 is shifted to reduce the reliability.

次に、図8は、本発明の一実施形態に係るフリップ実装体の製造方法の一過程であるアンダーフィル材硬化移行の態様を斜視で示す工程図である。図9は、図8に示したアンダーフィル材硬化移行の工程を部分断面で示す説明図である。図8、図9において、すでに説明した図中に示した構成要素と同一のものには同一符号を付してある。   Next, FIG. 8 is a process diagram showing in perspective a mode of underfill material curing transition, which is one step in the method of manufacturing a flip package according to one embodiment of the present invention. FIG. 9 is an explanatory diagram showing, in partial cross section, the process of underfill material curing transition shown in FIG. 8 and 9, the same reference numerals are given to the same components as those shown in the already described drawings.

図8に示すように、ベアチップ仮固定がすべての実装領域について終了した配線基板10は、プレス手段たる、板状の押圧部61、62により上下方向から一括的に押圧され、同時に加熱される。この加熱は、図9に示すように、押圧部61、62の内部に設けられたヒータ61a、62a(例えばセラミックヒータ)を用いて行うことができる。板状の押圧部61、62は、フリップチップボンダヘッド51に比べて面積、体積ともに大であり、必要な熱を十分に発生することができる。   As shown in FIG. 8, the wiring board 10 for which the bare chip temporary fixing has been completed for all the mounting regions is collectively pressed from above and below by plate-like pressing portions 61 and 62 serving as pressing means, and is simultaneously heated. As shown in FIG. 9, this heating can be performed using heaters 61 a and 62 a (for example, ceramic heaters) provided inside the pressing portions 61 and 62. The plate-like pressing portions 61 and 62 are large in both area and volume as compared with the flip chip bonder head 51, and can sufficiently generate necessary heat.

この加熱により半硬化のアンダーフィル材21Aは、硬化状態のアンダーフィル材21Bに変化する。押圧時には、例えば押圧部61a、62aの温度をあらかじめ昇温させておき(例えば180〜250℃)、スタッド状バンプ42ひとつ当たりに換算して例えば0.1〜1Nの押圧力でこれを行う。例えば、60バンプ/チップで、配線基板10に16のベアチップを実装の場合、1バンプ当たり1Nであれば、960Nの押圧力である。   By this heating, the semi-cured underfill material 21A is changed to a cured underfill material 21B. At the time of pressing, for example, the temperature of the pressing portions 61a and 62a is raised in advance (for example, 180 to 250 ° C.), and this is performed with a pressing force of, for example, 0.1 to 1 N in terms of one stud-like bump 42. For example, in the case of mounting 16 bare chips on the wiring substrate 10 with 60 bumps / chip, if the pressure is 1N per bump, the pressing force is 960N.

押圧時間は、用いるアンダーフィル材21の性質により異なるが、一般的には5〜90秒程度とすることができる。押圧部61、62による加熱は、ベアチップ41の側の押圧部62での発熱容量の方を、配線基板10側の押圧部61での発熱容量より大きくするのが伝熱効率上はより好ましい。押圧された状態でのアンダーフィル材21Aへの伝熱は、配線基板10(樹脂)を介するよりベアチップ41(シリコン)を介する方が、熱伝導率の違いから、大きくなるためである。配線基板10側の押圧部61からの加熱においては、配線基板10(樹脂)の温度がガラス転移点に達しないようにする。これらの点から、下側の押圧部61についてはヒータ61aを設けない構成とすることも考えられる。   The pressing time varies depending on the properties of the underfill material 21 to be used, but can generally be about 5 to 90 seconds. It is more preferable in terms of heat transfer efficiency that the heating by the pressing parts 61 and 62 is larger in the heat generation capacity in the pressing part 62 on the bare chip 41 side than in the pressing part 61 on the wiring board 10 side. This is because heat transfer to the underfill material 21 </ b> A in the pressed state is greater due to the difference in thermal conductivity through the bare chip 41 (silicon) than through the wiring substrate 10 (resin). In heating from the pressing portion 61 on the wiring board 10 side, the temperature of the wiring board 10 (resin) is prevented from reaching the glass transition point. From these points, it can be considered that the lower pressing portion 61 is not provided with the heater 61a.

板状の押圧部61、62には、例えば、耐熱樹脂製の板材を用いることができる。基本的に、配線基板10を押圧するための板材は、熱による変形が小さいものが好ましい。この点で、例えば、金属製、セラミック製なども考えられる。耐熱樹脂製の場合はわずかな可撓性があり硬質であるものの押圧する対象物(ベアチップ41が仮固定された配線基板10)の形状に倣いやすく、より好ましいと考えられる。   For the plate-like pressing portions 61 and 62, for example, a heat-resistant resin plate material can be used. Basically, it is preferable that the plate material for pressing the wiring board 10 is small in deformation due to heat. In this respect, for example, metal or ceramic may be considered. In the case of a heat-resistant resin, although it is slightly flexible and hard, it is easy to follow the shape of the object to be pressed (the wiring board 10 on which the bare chip 41 is temporarily fixed), which is considered to be more preferable.

図10は、本発明の一実施形態に係るフリップ実装体の製造方法を適用した場合のフリップ実装時間を比較例の場合のそれと対照して示す表である。図10に示すように、フリップチップボンダによりベアチップをひとつひとつフリップ実装する場合(表左欄)には、ベアチップの数に比例して合計実装時間が増加し、ベアチップ数が例えば8個であれば、合計616秒を要する(77秒/1個として)。これに対して、上記で説明してきた方法による場合(表右欄)では、ベアチップ仮固定に20秒/1個を要し、最後の一括硬化に60秒を要するとして、合計220秒で済む。したがって、大幅な生産効率向上が達せられる。この効果は、ベアチップ数が多くなるほどさらに大きくなる。   FIG. 10 is a table showing the flip mounting time when the method for manufacturing a flip mounted body according to one embodiment of the present invention is applied in contrast to that in the comparative example. As shown in FIG. 10, when flip-chip bonders are used to flip-mount bare chips one by one (the left column in the table), the total mounting time increases in proportion to the number of bare chips. It takes a total of 616 seconds (77 seconds / 1 piece). On the other hand, in the case of the method described above (the right column in the table), 20 seconds / 1 piece is required for temporary fixing of the bare chip and 60 seconds are required for the final batch curing, so that the total time is 220 seconds. Therefore, a significant improvement in production efficiency can be achieved. This effect is further increased as the number of bare chips increases.

次に、上記説明のようにして得られたフリップ実装体の応用について例(部品内蔵配線板の例)を図11、図12を参照して説明する。図11は、上記説明したフリップ実装体の製造方法の適用によって得られたフリップ実装体を部材に用いた部品内蔵配線板の構成を示す断面図である。図12は、図11に示した部品内蔵配線板を製造するための最終積層工程を示す工程図である。図11、図12において、すでに説明した図中に示した構成要素と同一相当のものには同一符号を付してある。   Next, an example (an example of a component built-in wiring board) of the application of the flip mounted body obtained as described above will be described with reference to FIGS. FIG. 11 is a cross-sectional view showing a configuration of a component built-in wiring board using as a member a flip mount obtained by applying the flip mount manufacturing method described above. FIG. 12 is a process diagram showing a final lamination process for manufacturing the component built-in wiring board shown in FIG. In FIG. 11 and FIG. 12, the same reference numerals are given to the same components as those shown in the already described drawings.

図11に示す部品内蔵配線板は、絶縁層101、102、103、104、105、配線層(配線パターン)201、11、203、204、205、206、層間接続体(導電性組成物印刷による導電性バンプ)301、302、304、305、スルーホール導電体303、ベアチップ41、スタッド状バンプ42、アンダーフィル材21B、はんだレジスト601、602を有する。   The component built-in wiring board shown in FIG. 11 includes insulating layers 101, 102, 103, 104, and 105, wiring layers (wiring patterns) 201, 11, 203, 204, 205, and 206, and an interlayer connector (by conductive composition printing). Conductive bumps) 301, 302, 304, 305, through-hole conductor 303, bare chip 41, stud-like bump 42, underfill material 21B, and solder resists 601 and 602.

図11に示す部品内蔵配線板を得るための最終積層工程である図12において、金属箔201A、206Aは、それぞれ、配線層201、206に加工されるべき金属箔(銅箔)である。また、プリプレグ102A、104Aは、それぞれ、絶縁層102、104に硬化させるべき前駆体(半硬化部材)である。図12に示すような配置で各配線板素材1、2、3を積層配置してプレス機で加圧、加熱する。これにより、プリプレグ102A、104Aが完全に硬化し全体が積層、一体化する。このとき、加熱により生じるプリプレグ102A、104Aの流動性により、ベアチップ41の周りの空間およびスルーホール導電体303内部の空間にはプリプレグ102A、104Aが変形進入する。   In FIG. 12, which is the final lamination step for obtaining the component built-in wiring board shown in FIG. 11, metal foils 201A and 206A are metal foils (copper foils) to be processed into the wiring layers 201 and 206, respectively. The prepregs 102A and 104A are precursors (semi-cured members) to be cured on the insulating layers 102 and 104, respectively. The respective wiring board materials 1, 2, and 3 are stacked and arranged in the arrangement as shown in FIG. Thereby, the prepregs 102A and 104A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 102A and 104A generated by heating, the prepregs 102A and 104A are deformed and entered into the space around the bare chip 41 and the space inside the through-hole conductor 303.

すなわち、図11に示す部品内蔵配線板は、図12に示すように、製造途上の部材としてフリップ実装体(配線板素材1)を用いる。そして、このフリップ実装体は、ベアチップ41に対応して部品用開口部701が設けられた中間の配線板素材2を介して上側の配線板素材3と積層、一体化される。この積層、一体化では、ベアチップ41の高さが一定に揃っていないとその高さ方向につかえたり、空隙ができやすくなったりして歩留まり低下をきたす恐れがある。この点で、上記説明した製造方法によるフリップ実装体を用いれば、図8に示したような一括的な押圧がされているので、ベアチップ41の高さがより一定に揃えられている。よって、歩留まり向上の効果が得られる。   That is, as shown in FIG. 12, the component built-in wiring board shown in FIG. 11 uses a flip mounting body (wiring board material 1) as a member in production. The flip mounted body is laminated and integrated with the upper wiring board material 3 via the intermediate wiring board material 2 provided with the component opening 701 corresponding to the bare chip 41. In this lamination and integration, if the height of the bare chip 41 is not uniform, it may be used in the height direction or a gap may be easily formed, resulting in a decrease in yield. In this respect, if the flip mounting body according to the manufacturing method described above is used, since the collective pressing as shown in FIG. 8 is performed, the height of the bare chip 41 is made more uniform. Therefore, the effect of improving the yield can be obtained.

1,2,3…配線板素材、10…配線基板、10a…個片化ごとの領域、11…配線パターン、21…アンダーフィル材(ペースト状)、21A…アンダーフィル材(半硬化)、21B…アンダーフィル材(硬化後)、31…ディスペンサノズル、41…ベアチップ、42…スタッド状バンプ、51…フリップチップボンダヘッド、51a…ヒータ、61,62…押圧部(プレス手段)、61a,62a…ヒータ(加熱手段)、101,102,103,104,105…絶縁層、102A,104A…プリプレグ、201,203,204,205,206…配線層(配線パターン)、201A,206A…金属箔(銅箔)、301,302,304,305…層間接続体(導電性組成物印刷による導電性バンプ)、303…スルーホール導電体、601,602…はんだレジスト、701…部品用開口部。   1, 2, 3 ... wiring board material, 10 ... wiring board, 10a ... area for each piece, 11 ... wiring pattern, 21 ... underfill material (paste), 21A ... underfill material (semi-cured), 21B ... Underfill material (after curing), 31 ... Dispenser nozzle, 41 ... Bare chip, 42 ... Stud bump, 51 ... Flip chip bonder head, 51a ... Heater, 61, 62 ... Pressing part (pressing means), 61a, 62a ... Heater (heating means), 101, 102, 103, 104, 105 ... insulating layer, 102A, 104A ... prepreg, 201, 203, 204, 205, 206 ... wiring layer (wiring pattern), 201A, 206A ... metal foil (copper) Foil), 301, 302, 304, 305 ... interlayer connection (conductive bumps printed by conductive composition), 303 ... through hole Conductor, 601, 602 ... solder resist, 701 ... component opening.

Claims (8)

ベアチップがフリップ実装されるべき実装領域が複数用意された配線基板の前記実装領域のそれぞれにペースト状のアンダーフィル材を塗布する工程と、
前記アンダーフィル材を介して前記配線基板上にベアチップを位置合わせして圧接するとともに加熱して前記アンダーフィル材を半硬化させるベアチップ仮固定を前記実装領域のそれぞれについて行う工程と、
前記配線基板上の複数のベアチップを一括して該配線基板の側に押し付けるように、前記配線基板を上下からプレス手段で押圧するとともに、加熱して前記アンダーフィル材を半硬化の状態から硬化の状態に移行させる工程と
を具備することを特徴とするフリップ実装体の製造方法。
Applying a paste-like underfill material to each of the mounting regions of the wiring board in which a plurality of mounting regions in which the bare chip is to be flip-mounted are prepared;
A step of performing bare chip temporary fixing for each of the mounting regions in which the bare chip is aligned and pressed on the wiring substrate via the underfill material and heated to semi-harden the underfill material;
The wiring board is pressed from above and below by pressing means so that a plurality of bare chips on the wiring board are collectively pressed against the wiring board, and the underfill material is cured from a semi-cured state by heating. And a step of shifting to a state. A method for manufacturing a flip package.
前記プレス手段が、前記ベアチップの存在する側を押圧する押圧部に第1の加熱手段を有し、前記ベアチップの存在しない側を押圧する押圧部に第2の加熱手段を有し、前記第1の加熱手段の方が前記第2の加熱手段より発熱容量が大であることを特徴とする請求項1記載のフリップ実装体の製造方法。   The pressing means has a first heating means at a pressing portion that presses the side where the bare chip exists, and has a second heating means at a pressing portion that presses the side where the bare chip does not exist, 2. The method of manufacturing a flip package according to claim 1, wherein the heating means has a larger heat generation capacity than the second heating means. 前記プレス手段が、前記ベアチップの存在する側を押圧する押圧部に加熱手段を有し、前記ベアチップの存在しない側を押圧する押圧部に加熱手段を有していないことを特徴とする請求項1記載のフリップ実装体の製造方法。   The press means has a heating means in a pressing portion that presses the side on which the bare chip exists, and does not have a heating means in a pressing portion that presses the side on which the bare chip does not exist. The manufacturing method of the flip mounting body as described. ベアチップ仮固定を前記実装領域のそれぞれについて行う前記工程が、前記アンダーフィル材が1.0×10Pa・sないし1.0×10Pa・sの粘度になるように加熱して行われることを特徴とする請求項1または2記載のフリップ実装体の製造方法。 The step of performing bare chip temporary fixing for each of the mounting regions is performed by heating so that the underfill material has a viscosity of 1.0 × 10 3 Pa · s to 1.0 × 10 5 Pa · s. The method for manufacturing a flip package according to claim 1 or 2, wherein アンダーフィル材を塗布する前記工程が、ディスペンサを用いてなされることを特徴とする請求項1記載のフリップ実装体の製造方法。   2. The method of manufacturing a flip package according to claim 1, wherein the step of applying the underfill material is performed using a dispenser. アンダーフィル材を塗布する前記工程が、前記ディスペンサにより前記アンダーフィル材を加温してなされることを特徴とする請求項5記載のフリップ実装体の製造方法。   6. The method of manufacturing a flip package according to claim 5, wherein the step of applying the underfill material is performed by heating the underfill material with the dispenser. 前記プレス手段が、前記配線基板を押圧するための耐熱樹脂製の板材を有することを特徴とする請求項1記載のフリップ実装体の製造方法。   2. The method of manufacturing a flip mount assembly according to claim 1, wherein the pressing means includes a heat-resistant resin plate material for pressing the wiring board. ペースト状の前記アンダーフィル材が、エポキシ樹脂を有することを特徴とする請求項1記載のフリップ実装体の製造方法。   The method for manufacturing a flip package according to claim 1, wherein the paste-like underfill material includes an epoxy resin.
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