JP5234761B2 - Electronic component bonding method, circuit board, and electronic apparatus - Google Patents

Electronic component bonding method, circuit board, and electronic apparatus Download PDF

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JP5234761B2
JP5234761B2 JP2008213683A JP2008213683A JP5234761B2 JP 5234761 B2 JP5234761 B2 JP 5234761B2 JP 2008213683 A JP2008213683 A JP 2008213683A JP 2008213683 A JP2008213683 A JP 2008213683A JP 5234761 B2 JP5234761 B2 JP 5234761B2
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electronic component
adjacent
fillet
shape
substrate
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JP2010050308A (en
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高司 石川
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NEC Casio Mobile Communications Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、基板上に隣接させて接着する電子部品の接着方法と、その方法によって製造される回路基板と、その回路基板を備える電子機器に関する。   The present invention relates to a method for bonding electronic components that are bonded adjacent to each other on a substrate, a circuit board manufactured by the method, and an electronic apparatus including the circuit substrate.

近年、製品の小型化のために、基板においてもますます高密度実装化が要求されており、電子部品間の間隔は非常に小さくなってきている。
そして、基板と電子部品との接続信頼性を向上させるためにアンダーフィル材を塗布し硬化する工程が行われるが、特に、隣接する電子部品間に発生しやすいブリッジ部が剥離等の問題を起こすことがわかってきた。 In recent years, in order to reduce the size of products, higher density mounting is demanded on the board, and the interval between electronic components is becoming extremely small.
In order to improve the connection reliability between the substrate and the electronic component, a process of applying and curing an underfill material is performed. In particular, a bridge portion that is likely to occur between adjacent electronic components causes a problem such as peeling. I understand that.

ところで、特許文献１には、ヤング率等の特性値として最適な封止樹脂を用いて実装するとチップの剥離等が発生しにくくなる技術、また、封止樹脂のフィレット部形状を良好に形成すると好ましいことが開示されている。
また、特許文献２には、超音波振動を用いて、アンダーフィル樹脂のフィレット部形状を良好にして、信頼性の高い実装を実現する技術が開示されている。
特開２０００−１５０７２９号公報 特開２００２−２７０６４２号公報 By the way, in patent document 1, when it mounts using sealing resin optimal as characteristic values, such as a Young's modulus, when the chip | tip peeling etc. become difficult to generate | occur | produce, and the fillet part shape of sealing resin is formed favorably Preferred is disclosed.
Patent Document 2 discloses a technology that realizes highly reliable mounting by using ultrasonic vibration to improve the shape of the fillet portion of the underfill resin.
JP 2000-150729 A JP 2002-270642 A

しかし、特許文献１において、適正なフィレット部形状を形成するための具体的な方法は、開示されていない。
また、特許文献２のような実装方法は、超音波ボンダーヘッド等の特殊治具が必要となるという問題があった。
なお、隣接する電子部品間のブリッジ部の問題は検討されていない。 However, Patent Document 1 does not disclose a specific method for forming an appropriate fillet portion shape.
Further, the mounting method as disclosed in Patent Document 2 has a problem that a special jig such as an ultrasonic bonder head is required.
In addition, the problem of the bridge | bridging part between adjacent electronic components is not examined.

図１２は一例として基板上に隣接する電子部品間にブリッジ部が発生した場合を示したもので、１２０は基板、１２１・１２２は隣接する電子部品であるＩＣ（Integrated Circuit：集積回路）、１２３・１２４はＢＧＡ（Ball Grid Array）、１２５はアンダーフィル材、１２６はフィレット部、１２７はブリッジ部である。すなわち、基板１２０上に隣接するＩＣ１２１・１２２間には、それぞれのＢＧＡ１２３・１２４間に浸透したアンダーフィル材１２５が表面張力で繋がって硬化したブリッジ部１２７となっている。   FIG. 12 shows, as an example, a case where a bridge portion is generated between adjacent electronic components on a substrate. 120 is a substrate, 121 and 122 are ICs (Integrated Circuits) that are adjacent electronic components, 123. 124 is a BGA (Ball Grid Array), 125 is an underfill material, 126 is a fillet portion, and 127 is a bridge portion. That is, between the ICs 121 and 122 adjacent to each other on the substrate 120, a bridge portion 127 is formed in which the underfill material 125 that has permeated between the BGAs 123 and 124 is connected by surface tension and cured.

図１３は図１２の基板１２０に荷重がかかってブリッジ部１２７にクラック１２８が発生した場合を示したもので、図示のように、基板１２０に背面から荷重がかかり、基板１２０が撓むことで、隣接するＩＣ１２１・１２２が離れる方向に変形しようとし、その間のブリッジ部１２７において、引張方向の高い歪が発生し、クラック１２８が入る。このクラック１２８が、図示のように、例えばＢＧＡ１２３接合部に至り、断線等の不具合を引き起こす。   FIG. 13 shows a case where a load is applied to the substrate 120 of FIG. 12 and a crack 128 is generated in the bridge portion 127. As shown in the drawing, a load is applied to the substrate 120 from the back, and the substrate 120 is bent. The adjacent ICs 121 and 122 try to be deformed in a direction away from each other, and a high strain in the tensile direction is generated in the bridge portion 127 therebetween, and the crack 128 enters. As shown in the figure, this crack 128 reaches, for example, the BGA 123 joint and causes problems such as disconnection.

本発明の課題は、基板上に隣接させて接着する電子部品間の接着材の形状を所望の形状にして、信頼性を向上させることである。   An object of the present invention is to improve the reliability by making a shape of an adhesive material between electronic components to be bonded adjacent to each other on a substrate into a desired shape.

以上の課題を解決するため、請求項１に記載の発明は、基板と、当該基板に電気的に接続された隣接する電子部品との接続信頼性を向上させる電子部品の接着方法であって、前記隣接する電子部品の周囲に接着材を塗布する接着材塗布ステップと、当該接着材塗布ステップによって前記隣接する電子部品間に塗布された接着材の上から前記接着材の形状を所望のフィレット部形状に規定するための逆フィレット部形状の形成型を載置する型載置ステップと、当該型載置ステップによって逆フィレット部形状の形成型が載置された状態で前記接着材を硬化させる硬化ステップと、を含み、前記型載置ステップは、前記逆フィレット部形状の形成型を前記隣接する電子部品の少なくとも一方に接着する接着ステップを含むことを特徴とする。
請求項２に記載の発明は、請求項１に記載の電子部品の接着方法であって、前記逆フィレット部形状の形成型には、前記隣接する電子部品間の応力を緩和するためのスリットが設けられていることを特徴とする。
請求項３に記載の発明は、請求項１又は２に記載の電子部品の接着方法であって、前記逆フィレット部形状の形成型には、フェライトが混入されていることを特徴とする。 In order to solve the above problems, the invention described in claim 1 is an electronic component bonding method for improving connection reliability between a substrate and an adjacent electronic component electrically connected to the substrate, An adhesive application step for applying an adhesive around the adjacent electronic component, and a desired fillet portion from above the adhesive applied between the adjacent electronic components by the adhesive application step A mold placing step for placing a reverse fillet shape forming mold for defining the shape, and curing for curing the adhesive in a state where the reverse fillet shape forming mold is placed by the mold placing step. And the mold placing step includes a bonding step of bonding the inverted fillet-shaped forming mold to at least one of the adjacent electronic components.
A second aspect of the present invention is the electronic component bonding method according to the first aspect, wherein the reverse fillet forming die has a slit for relaxing stress between the adjacent electronic components. It is provided.
According to a third aspect of the invention, a method for bonding electronic components according to claim 1 or 2, in the form type of the reverse fillet shape, wherein the ferrite is mixed.

請求項４に記載の発明は、請求項１から３のいずれか一項に記載の電子部品の接着方法であって、前記逆フィレット部形状の形成型は、前記隣接する電子部品間に形成されるブリッジ部の発生を抑制する形状であることを特徴とする。 A fourth aspect of the present invention is the electronic component bonding method according to any one of the first to third aspects , wherein the reverse fillet-shaped forming mold is formed between the adjacent electronic components. It is a shape which suppresses generation | occurrence | production of the bridge | bridging part.

請求項５に記載の発明は、請求項１から４のいずれか一項に記載の電子部品の接着方法であって、前記型載置ステップは、前記隣接する電子部品間に形成される所望のフィレット部形状を安定的に規定するための加圧ステップを含むことを特徴とする。 A fifth aspect of the present invention is the electronic component bonding method according to any one of the first to fourth aspects , wherein the mold placing step is a desired one formed between the adjacent electronic components. A pressurizing step for stably defining the fillet shape is included.

請求項６に記載の発明は、請求項１から５のいずれか一項に記載の電子部品の接着方法であって、前記接着材は、前記基板と前記電子部品と隙間に入り込むアンダーフィル材であることを特徴とする。 Invention of Claim 6 is the adhesion method of the electronic component as described in any one of Claim 1-5, Comprising : The said adhesive material is an underfill material which penetrates into the said board | substrate and the said electronic component, and is into a clearance gap. It is characterized by being.

請求項７に記載の発明は、請求項１から６のいずれか一項に記載の電子部品の接着方法であって、前記逆フィレット部形状の形成型は、前記隣接する電子部品間の応力を緩和する弾性部材により形成されていることを特徴とする。 The invention according to claim 7 is the electronic component adhesion method according to any one of claims 1 to 6 , wherein the reverse fillet-shaped forming mold is configured to reduce stress between the adjacent electronic components. It is formed of an elastic member that relaxes.

請求項８に記載の発明は、請求項１から７のいずれか一項に記載の電子部品の接着方法によって接着された隣接する電子部品を備える回路基板を特徴とする。 According to an eighth aspect of the present invention, there is provided a circuit board including adjacent electronic components bonded by the electronic component bonding method according to any one of the first to seventh aspects.

請求項９に記載の発明は、請求項８に記載の回路基板を備える電子機器を特徴とする。 According to a ninth aspect of the present invention, there is provided an electronic apparatus including the circuit board according to the eighth aspect.

本発明によれば、隣接する電子部品間の接着材の形状を所望の形状にさせることができるので、回路基板の信頼性を向上させることができる。   According to the present invention, since the shape of the adhesive between adjacent electronic components can be changed to a desired shape, the reliability of the circuit board can be improved.

以下、図を参照して本発明を実施するための最良の形態を詳細に説明する。
図１は本発明を適用した電子機器の一実施形態の構成として携帯電話を開いた使用状態を示したもので、１は第１の筐体、２は第２の筐体、３はヒンジ部、４は操作部、５は表示部である。
図示のように、第１の筐体１と第２の筐体２はヒンジ部３を介して折り畳み自在（開閉自在）に結合され、第１の筐体１に操作部４が設けられて、第２の筐体２に表示部５が設けられている。 Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a use state in which a mobile phone is opened as a configuration of an embodiment of an electronic apparatus to which the present invention is applied. 1 is a first casing, 2 is a second casing, and 3 is a hinge portion. Reference numeral 4 denotes an operation unit, and 5 denotes a display unit.
As shown in the figure, the first housing 1 and the second housing 2 are foldably coupled (openable and closable) via the hinge portion 3, and the operation portion 4 is provided in the first housing 1. A display unit 5 is provided in the second housing 2.

図２は携帯電話を折り畳んだ状態として内部の基板接続構成例を示したもので、６はメイン回路基板、７はサブ回路基板、８はアンテナ基板、９・１０はフレキシブル接続基板である。
図示例において、第１の筐体１内にメイン回路基板６が設けられて、第２の筐体２内にサブ回路基板７が設けられ、さらに、第１の筐体２内にはアンテナ基板８が設けられている。第１の筐体１内のメイン回路基板６と第２の筐体２内のサブ回路基板７は、ヒンジ部３内に配置したフレキシブル接続基板９を介して電気的接続され、第１の筐体１内のアンテナ基板８はメイン回路基板６にフレキシブル接続基板１０を介して接続されている。 FIG. 2 shows an example of an internal board connection configuration in a state in which the cellular phone is folded, 6 is a main circuit board, 7 is a sub circuit board, 8 is an antenna board, and 9 and 10 are flexible connection boards.
In the illustrated example, a main circuit board 6 is provided in the first casing 1, a sub circuit board 7 is provided in the second casing 2, and an antenna board is further provided in the first casing 2. 8 is provided. The main circuit board 6 in the first housing 1 and the sub circuit board 7 in the second housing 2 are electrically connected via a flexible connection board 9 disposed in the hinge portion 3, and the first housing 1. The antenna board 8 in the body 1 is connected to the main circuit board 6 via a flexible connection board 10.

（実施形態１）
図３は本発明により基板上に隣接する電子部品を接着した実施形態１を示すもので、３０は基板、３１・３２は隣接するＩＣ（電子部品）、３３・３４はＢＧＡ、３５はアンダーフィル材（接着材）、３６はフィレット部、４１は逆フィレット部形状の形成型である。
なお、基板３０は、前述した携帯電話のメイン回路基板６の一部を構成する。 (Embodiment 1)
FIG. 3 shows a first embodiment in which adjacent electronic components are bonded on a substrate according to the present invention, 30 is a substrate, 31 and 32 are adjacent ICs (electronic components), 33 and 34 are BGA, and 35 is underfill. A material (adhesive material), 36 is a fillet portion, and 41 is a forming die having an inverted fillet portion shape.
The board 30 constitutes a part of the main circuit board 6 of the mobile phone described above.

図示のように、実施形態１において、基板３０上には、隣接する電子部品であるＩＣ３１・３２が、ＢＧＡ３３・３４をそれぞれ介して搭載されている。隣接するＩＣ３１・３２は、接着材であるアンダーフィル材３５を介して基板３０上に接着されている。アンダーフィル材３５は、隣接するＩＣ３１・３２の周辺に塗布されて毛細管現象によりＢＧＡ３３・３４間に浸透し、表面張力により隣接するＩＣ３１・３２の周囲に、図示のように、肉厚を漸次減少して表面が円弧状のフィレット部３６を形成して熱硬化する。   As shown in the drawing, in the first embodiment, adjacent electronic components ICs 31 and 32 are mounted on the substrate 30 via BGAs 33 and 34, respectively. The adjacent ICs 31 and 32 are bonded onto the substrate 30 via an underfill material 35 that is an adhesive. The underfill material 35 is applied to the periphery of the adjacent ICs 31 and 32, penetrates between the BGAs 33 and 34 by capillary action, and gradually decreases in thickness around the adjacent ICs 31 and 32 due to surface tension as shown in the figure. Then, a fillet portion 36 having a circular arc surface is formed and thermally cured.

そして、隣接するＩＣ３１・３２間には、ブリッジ部の発生を抑制する形状で逆フィレット部形状の形成型４１が配置されている。この逆フィレット部形状の形成型４１によって、隣接するＩＣ３１・３２間にもフィレット部３６が形成されている。図示例において、逆フィレット部形状の形成型４１は、上面が低い方のＩＣ３２に重なって上面が高い方のＩＣ３１と一様な上面となる平板部４２を一体に有している。   Between the adjacent ICs 31 and 32, a reverse fillet-shaped forming die 41 is arranged in a shape that suppresses the generation of a bridge portion. A fillet portion 36 is also formed between the adjacent ICs 31 and 32 by the reverse fillet forming die 41. In the illustrated example, the reverse fillet-shaped forming die 41 integrally has a flat plate portion 42 that overlaps with the IC 32 with the lower upper surface and the IC 31 with the higher upper surface and the uniform upper surface.

なお、逆フィレット部形状の形成型４１は、隣接するＩＣ３１・３２間の応力を緩和する弾性を具備するとともに、アンダーフィル材３５の熱硬化温度でも形状を維持できる耐熱性を具備するもので、例えばシリコンゴム等のゴム材料や樹脂材料等の弾性部材により形成されている。また、隣接するＩＣ３１・３２から発生するノイズが回路性能に悪影響を与えるノイズ対策として、逆フィレット部形状の形成型４１の弾性部材にフェライトを混入しておくことが望ましい。   The inverted fillet-shaped forming die 41 has elasticity to relieve stress between adjacent ICs 31 and 32, and has heat resistance capable of maintaining the shape even at the thermosetting temperature of the underfill material 35. For example, it is formed of an elastic member such as a rubber material such as silicon rubber or a resin material. Further, as a noise countermeasure in which noise generated from adjacent ICs 31 and 32 adversely affects circuit performance, it is desirable to mix ferrite in the elastic member of the forming mold 41 having the inverted fillet shape.

図４は電子部品の電気的接続工程及び接着工程を示したフローチャートである。
図示のように、先ず、電気的接続工程は、基板３０をマウンタにマウントするマウントステップＳ１、その基板３０上に半田ペーストを印刷する印刷ステップＳ２、その基板３０上に隣接するＩＣ３１・３２を含む電子部品を搭載する部品搭載ステップＳ３、こうして電子部品を搭載した基板３０をリフロー処理するリフローステップＳ４の順で行われる。 FIG. 4 is a flowchart showing an electrical connection process and an adhesion process of electronic components.
As shown in the figure, first, the electrical connection process includes a mounting step S1 for mounting the substrate 30 on the mounter, a printing step S2 for printing solder paste on the substrate 30, and ICs 31 and 32 adjacent to the substrate 30. The component mounting step S3 for mounting the electronic component and the reflow step S4 for reflowing the substrate 30 mounted with the electronic component are performed in this order.

そして、次の信頼性向上のための接着工程は、基板３０上の隣接するＩＣ３１・３２を含む電子部品の周囲にディスペンサによるアンダーフィル材３５を塗布する接着材塗布ステップＳ５、その隣接するＩＣ３１・３２間に逆フィレット部形状の形成型４１を載置する型載置ステップＳ６、アンダーフィル材３５を熱硬化処理する硬化ステップＳ７、隣接するＩＣ３１・３２間から逆フィレット部形状の形成型４１を取り外す離型ステップＳ８の順で行われる。   Then, the next bonding process for improving the reliability includes an adhesive application step S5 in which an underfill material 35 is applied around the electronic component including the adjacent ICs 31 and 32 on the substrate 30, and the adjacent ICs 31 and 32 are adjacent to each other. A mold placement step S6 for placing a reverse fillet-shaped forming die 41 between 32, a curing step S7 for thermally curing the underfill material 35, and a reverse fillet-shaped forming mold 41 between adjacent ICs 31 and 32. It is performed in the order of the release step S8 to be removed.

ここで、型載置ステップＳ６において、必要に応じ、隣接するＩＣ３１・３２間に形成される所望のフィレット部形状を安定的に規定するための加圧ステップが含まれる（実施形態４の図８参照）。
また、型載置ステップＳ６は、必要に応じ、逆フィレット部形状の形成型４１の平板部４２を隣接するＩＣ３１・３２の少なくとも一方の上面に接着する接着ステップが含まれる（実施形態１の図３、実施形態２の図６、実施形態３の図７参照）。 Here, the mold placing step S6 includes a pressurizing step for stably defining a desired fillet shape formed between the adjacent ICs 31 and 32 as necessary (FIG. 8 of the fourth embodiment). reference).
Further, the mold placement step S6 includes an adhesion step of adhering the flat plate part 42 of the inverted fillet-shaped forming mold 41 to at least one upper surface of the adjacent ICs 31 and 32 as required (FIG. 1 of the first embodiment). 3. See FIG. 6 of Embodiment 2 and FIG. 7 of Embodiment 3.

なお、接着材塗布ステップＳ５、型載置ステップＳ６の順序を基本とするが、逆でも良い。
また、硬化ステップＳ７において、熱硬化としたが、紫外線硬化等の光硬化でも良い。
また、離型ステップＳ８は必要に応じて行われる（実施形態６の図１０参照）。 In addition, although the order of the adhesive material application step S5 and the mold placement step S6 is basic, the reverse may be possible.
In the curing step S7, thermosetting is used, but photocuring such as ultraviolet curing may be used.
Moreover, mold release step S8 is performed as needed (refer FIG. 10 of Embodiment 6).

以上、実施形態１によれば、逆フィレット部形状の形成型４１により、隣接するＩＣ３１・３２間のアンダーフィル材３５の形状を所望のフィレット部形状にさせることができる。   As described above, according to the first embodiment, the shape of the underfill material 35 between the adjacent ICs 31 and 32 can be changed to a desired fillet shape by the reverse fillet shape forming die 41.

図５は本発明による隣接する電子部品間にブリッジ部なし品と比較例のブリッジ部あり品との歪測定結果例を示した荷重‐歪線図である。
すなわち、例えば図１２に示したような基板１２０上に隣接するＩＣ１２１・１２２間にアンダーフィル材１２５が表面張力で繋がって硬化したブリッジ部１２７があるものでは、ブリッジ部１２７で基板剛性が上がるので、図５に示すように、歪は小さくなる。しかし、例えば図１３に示したような基板１２０に荷重がかかってブリッジ部１２７にクラック１２８が入ると、図５に示したように、急激に歪が増えて、ＢＧＡ１２３・１２４の許容歪を超え破損に至る。 FIG. 5 is a load-strain diagram showing an example of strain measurement results for a product without a bridge portion between adjacent electronic components according to the present invention and a product with a bridge portion of a comparative example.
That is, for example, when there is a bridge portion 127 in which the underfill material 125 is connected by surface tension between the adjacent ICs 121 and 122 on the substrate 120 as shown in FIG. As shown in FIG. 5, the distortion is reduced. However, for example, when a load is applied to the substrate 120 as shown in FIG. 13 and a crack 128 enters the bridge portion 127, as shown in FIG. 5, the strain rapidly increases and exceeds the allowable strain of the BGA 123/124. It leads to damage.

これに対し、実施形態１の隣接するＩＣ３１・３２間のアンダーフィル材３５の形状を逆フィレット部形状の形成型４１で所望のフィレット部形状にさせたブリッジ部なし品は、図５に示したように、クラックの発生がない。
このように、隣接するＩＣ３１・３２間にブリッジ部が形成されないので、その隣接するＩＣ３１・３２の接続信頼性を向上させることができる。 On the other hand, the product without the bridge portion in which the shape of the underfill material 35 between the adjacent ICs 31 and 32 of the first embodiment is formed into a desired fillet portion shape with the reverse fillet shape forming die 41 is shown in FIG. As shown, there is no occurrence of cracks.
As described above, since the bridge portion is not formed between the adjacent ICs 31 and 32, the connection reliability of the adjacent ICs 31 and 32 can be improved.

従って、携帯電話において、隣接するＩＣ３１・３２を含む電子部品を搭載したメイン回路基板６の信頼性を向上させることができる。   Therefore, in the mobile phone, the reliability of the main circuit board 6 on which electronic components including the adjacent ICs 31 and 32 are mounted can be improved.

また、型載置ステップＳ６に含まれる接着ステップにおいて、逆フィレット部形状の形成型４１の平板部４２を一方のＩＣ３２の上面に接着することにより、逆フィレット部形状の形成型４１の浮きが防げるので、確実に所望のフィレット部形状を形成することができる。   Further, in the bonding step included in the mold placing step S6, the flat fill portion 42 of the reverse fillet-shaped forming die 41 is bonded to the upper surface of one IC 32, thereby preventing the reverse fillet-shaped forming die 41 from floating. Therefore, a desired fillet part shape can be formed reliably.

また、接着材塗布ステップＳ５において、アンダーフィル材３５を用いることで、隣接するＩＣ３１・３２のＢＧＡ３３・３４に好適に適用することができる。   Further, by using the underfill material 35 in the adhesive application step S5, it can be suitably applied to the BGAs 33 and 34 of the adjacent ICs 31 and 32.

また、逆フィレット部形状の形成型４１を、隣接するＩＣ３１・３２間の応力を緩和する弾性部材により形成したことで、逆フィレット部形状の形成型４１を残した場合、隣接するＩＣ３１・３２間の応力を緩和でき、接続信頼性を向上させることができる。   In addition, when the reverse fillet-shaped forming die 41 is formed of an elastic member that relieves stress between the adjacent ICs 31 and 32, when the reverse fillet-shaped forming die 41 remains, between the adjacent ICs 31 and 32. Stress can be relaxed, and connection reliability can be improved.

また、逆フィレット部形状の形成型４１のフェライト混入により隣接するＩＣ３１・３２のノイズ低減を兼ねるので、ノイズ低減用の別部品を設ける場合と比較して、コストを低減することができる。   Moreover, since the noise of adjacent ICs 31 and 32 is also reduced by mixing the ferrite in the forming mold 41 having the inverted fillet shape, the cost can be reduced as compared with the case where another component for noise reduction is provided.

（実施形態２）
図６は本発明により基板上に隣接する電子部品を接着した実施形態２を示すもので、前述した実施形態１の図３と同様、３０は基板、３１・３２は隣接するＩＣ、３３・３４はＢＧＡ、３５はアンダーフィル材、３６はフィレット部、４１は逆フィレット部形状の形成型、４２は平板部であって、４３はスリットである。 (Embodiment 2)
FIG. 6 shows a second embodiment in which adjacent electronic components are bonded on a substrate according to the present invention. As in FIG. 3 of the first embodiment described above, 30 is a substrate, 31 and 32 are adjacent ICs, and 33 and 34. Is a BGA, 35 is an underfill material, 36 is a fillet part, 41 is a forming mold of an inverted fillet part shape, 42 is a flat plate part, and 43 is a slit.

実施形態２では、図示のように、前述した実施形態１の図３と同様の構成において、その逆フィレット形状部（逆フィレット部形状の部分）に、上面に開放されて隣接するＩＣ３１・３２間の応力を緩和するために弾性を具備させるためのスリット４３を形成する。   In the second embodiment, as shown in the drawing, in the same configuration as that of FIG. 3 of the first embodiment described above, the reverse fillet shape portion (the portion of the reverse fillet portion shape) is opened between the adjacent ICs 31 and 32 by being opened on the upper surface. In order to relieve the stress, a slit 43 for providing elasticity is formed.

以上、実施形態２によれば、前述した実施形態１による作用効果の他、次の作用効果が得られる。
すなわち、形成型４１の逆フィレット形状部に応力を緩和するためのスリット４３を形成したことで、逆フィレット部形状の形成型４１を残した場合、形成型４１の逆フィレット形状部がスリット４３の存在により弾性を具備するため、隣接するＩＣ３１・３２間の応力を緩和でき、接続信頼性を向上させることができる。 As described above, according to the second embodiment, the following operational effects can be obtained in addition to the operational effects of the first embodiment.
That is, by forming the slit 43 for relieving stress in the reverse fillet-shaped portion of the forming die 41, when the reverse fillet-shaped forming die 41 is left, the reverse fillet-shaped portion of the forming die 41 becomes the slit 43 Due to the presence of elasticity, the stress between the adjacent ICs 31 and 32 can be relaxed, and the connection reliability can be improved.

ここで、隣接するＩＣ３１・３２と前記第１の筐体１との間に緩衝材を入れる場合は、隣接するＩＣ３１・３２の上面に、緩衝材を兼ねるフェライト入りのシートを貼っておくことで、隣接するＩＣ３１・３２に対する緩衝とノイズ低減が行える。   Here, when a buffer material is put between the adjacent ICs 31 and 32 and the first casing 1, a ferrite-containing sheet that also serves as a buffer material is pasted on the upper surface of the adjacent ICs 31 and 32. Buffering and noise reduction for adjacent ICs 31 and 32 can be performed.

（実施形態３）
図７は本発明により基板上に隣接する電子部品を接着した実施形態３を示すもので、前述した実施形態１の図３と同様、３０は基板、３１・３２は隣接するＩＣ、３３・３４はＢＧＡ、３５はアンダーフィル材、３６はフィレット部、４１は逆フィレット部形状の形成型、４２は平板部である。 (Embodiment 3)
FIG. 7 shows a third embodiment in which adjacent electronic components are bonded on a substrate according to the present invention. Similar to FIG. 3 of the first embodiment, 30 is a substrate, 31 and 32 are adjacent ICs, and 33 and 34. Is a BGA, 35 is an underfill material, 36 is a fillet portion, 41 is an inverted fillet-shaped forming mold, and 42 is a flat plate portion.

実施形態３では、図示のように、隣接するＩＣ３１・３２の高さが同じ場合において、その隣接するＩＣ３１・３２を跨ぐように平板部４２を逆フィレット形状部の両側に設けた形成型４１を用いる。   In the third embodiment, as shown in the figure, when the adjacent ICs 31 and 32 have the same height, the forming die 41 in which the flat plate portions 42 are provided on both sides of the inverted fillet shape portion so as to straddle the adjacent ICs 31 and 32 is provided. Use.

以上、実施形態３によれば、前述した実施形態１による作用効果の他、次の作用効果が得られる。
すなわち、型載置ステップＳ６に含まれる接着ステップにおいて、逆フィレット部形状の形成型４１の平板部４２を隣接する両方のＩＣ３１・３２の上面に接着することにより、逆フィレット部形状の形成型４１の浮きが防げるので、確実に所望のフィレット部形状を形成することができる。 As described above, according to the third embodiment, the following operational effects can be obtained in addition to the operational effects of the first embodiment described above.
That is, in the bonding step included in the mold placing step S6, the reverse fillet-shaped forming die 41 is bonded by bonding the flat plate portion 42 of the reverse fillet-shaped forming die 41 to the upper surfaces of both adjacent ICs 31 and 32. Therefore, a desired fillet portion shape can be reliably formed.

（実施形態４）
図８は本発明により基板上に隣接する電子部品を接着した実施形態４を示すもので、前述した実施形態１の図３と同様、３０は基板、３１・３２は隣接するＩＣ、３３・３４はＢＧＡ、３５はアンダーフィル材、３６はフィレット部、４１は逆フィレット部形状の形成型であって、４５は冶具である。 (Embodiment 4)
FIG. 8 shows a fourth embodiment in which adjacent electronic components are bonded on a substrate according to the present invention. Similar to FIG. 3 of the first embodiment, 30 is a substrate, 31 and 32 are adjacent ICs, and 33 and 34. Is a BGA, 35 is an underfill material, 36 is a fillet portion, 41 is an inverted fillet-shaped forming mold, and 45 is a jig.

実施形態４では、図示のように、平板部のない逆フィレット形状部のみの形成型４１を用い、この逆フィレット形状部のみの形成型４１を冶具４５で上方から加圧する。   In the fourth embodiment, as shown in the figure, a forming die 41 having only a reverse fillet-shaped portion without a flat plate portion is used, and the forming die 41 having only a reverse fillet-shaped portion is pressed from above with a jig 45.

以上、実施形態４によれば、前述した実施形態１による作用効果の他、次の作用効果が得られる。
すなわち、型載置ステップＳ６に含まれる加圧ステップにおいて、逆フィレット部形状のみの形成型４１を冶具４５で加圧することにより、隣接するＩＣ３１・３２間のアンダーフィル材３５を確実に押し出せるので、確実に所望のフィレット部形状を形成することができる。 As described above, according to the fourth embodiment, the following operational effects can be obtained in addition to the operational effects of the first embodiment described above.
That is, in the pressurizing step included in the mold placing step S6, the underfill material 35 between the adjacent ICs 31 and 32 can be reliably pushed out by pressing the forming mold 41 having only the reverse fillet shape with the jig 45. The desired fillet shape can be surely formed.

（実施形態５）
図９は本発明により基板上に隣接する電子部品を接着した実施形態５を示すもので、前述した実施形態１の図３と同様、３０は基板、３１・３２は隣接するＩＣ、３３・３４はＢＧＡ、３５はアンダーフィル材、３６はフィレット部、４１は逆フィレット部形状の形成型であって、４３はスリットである。 (Embodiment 5)
FIG. 9 shows a fifth embodiment in which adjacent electronic components are bonded on a substrate according to the present invention. Similar to FIG. 3 of the first embodiment, 30 is a substrate, 31 and 32 are adjacent ICs, and 33 and 34. Is a BGA, 35 is an underfill material, 36 is a fillet portion, 41 is an inverted fillet-shaped forming mold, and 43 is a slit.

実施形態５では、図示のように、平板部のない逆フィレット部形状のみの形成型４１を、前述した実施形態２と同様、前述した実施形態１の弾性部材とは異なる樹脂材料で形成して、その逆フィレット形状部に、上面に開放されて隣接するＩＣ３１・３２間の応力を緩和するために弾性を具備させるためのスリット４３を形成する。   In the fifth embodiment, as shown in the drawing, a forming mold 41 having only a reverse fillet shape without a flat plate portion is formed of a resin material different from the elastic member of the first embodiment, as in the second embodiment. In the inverted fillet-shaped portion, a slit 43 is formed for providing elasticity to relieve stress between the adjacent ICs 31 and 32 opened to the upper surface.

以上、実施形態５によれば、前述した実施形態２と同様、次の作用効果が得られる。
すなわち、形成型４１の逆フィレット形状部に応力を緩和するためのスリット４３を形成したことで、逆フィレット部形状の形成型４１を残した場合、形成型４１の逆フィレット形状部がスリット４３の存在により弾性を具備するため、隣接するＩＣ３１・３２間の応力を緩和でき、接続信頼性を向上させることができる。 As described above, according to the fifth embodiment, the following functions and effects can be obtained as in the second embodiment.
That is, by forming the slit 43 for relieving stress in the reverse fillet-shaped portion of the forming die 41, when the reverse fillet-shaped forming die 41 is left, the reverse fillet-shaped portion of the forming die 41 becomes the slit 43 Due to the presence of elasticity, the stress between the adjacent ICs 31 and 32 can be relaxed, and the connection reliability can be improved.

ここで、隣接するＩＣ３１・３２と前記第１の筐体１との間に緩衝材を入れる場合は、隣接するＩＣ３１・３２の上面に、前述した実施形態２と同様に、緩衝材を兼ねるフェライト入りのシートを貼っておくことで、隣接するＩＣ３１・３２に対する緩衝とノイズ低減が行える。   Here, in the case where a buffer material is inserted between the adjacent ICs 31 and 32 and the first casing 1, the ferrite serving as the buffer material is formed on the upper surface of the adjacent ICs 31 and 32 as in the second embodiment. By sticking the sheet in, the buffering and noise reduction for the adjacent ICs 31 and 32 can be performed.

（実施形態６）
図１０は本発明により基板上に隣接する電子部品を接着した実施形態６を示すもので、前述した実施形態１の図３と同様、３０は基板、３１・３２は隣接するＩＣ、３３・３４はＢＧＡ、３５はアンダーフィル材、３６はフィレット部である。 (Embodiment 6)
FIG. 10 shows a sixth embodiment in which adjacent electronic components are bonded on a substrate according to the present invention. Similar to FIG. 3 of the first embodiment, 30 is a substrate, 31 and 32 are adjacent ICs, and 33 and 34. Is a BGA, 35 is an underfill material, and 36 is a fillet portion.

実施形態６では、図示のように、前述した実施形態１の隣接するＩＣ３１・３２間から逆フィレット部形状の形成型４１を取り外す。   In the sixth embodiment, as shown in the drawing, the reverse fillet-shaped forming die 41 is removed from between the adjacent ICs 31 and 32 of the first embodiment described above.

図１１は図１０の隣接する電子部品を上方から示したもので、隣接するＩＣ３１・３２の四周には、その間も含めて所定のフィレット部３６がそれぞれ形成される。   FIG. 11 shows the adjacent electronic components of FIG. 10 from above, and predetermined fillet portions 36 are formed on the four circumferences of the adjacent ICs 31 and 32, respectively.

以上、実施形態６によれば、前述した実施形態１による作用効果とは異なる点として、次の作用効果が得られる。
すなわち、図４の離型ステップＳ８において、隣接するＩＣ３１・３２間から逆フィレット部形状の形成型４１を取り外すので、逆フィレット部形状の形成型４１として、テフロン（登録商標）等の堅い型を用いることができ、従って、その型を繰り返し使うことができる。 As described above, according to the sixth embodiment, the following operational effects are obtained as points different from the operational effects according to the first embodiment.
That is, in the mold release step S8 of FIG. 4, since the reverse fillet-shaped forming die 41 is removed from between the adjacent ICs 31 and 32, a rigid mold such as Teflon (registered trademark) is used as the reverse fillet-shaped forming die 41. Can be used, and therefore the type can be used repeatedly.

（変形例）
なお、以上の実施形態においては、携帯電話としたが、本発明はこれに限定されるものではなく、デジタルカメラ、ビデオカメラ、ＰＤＡ、ノートパソコン、ウェアラブルパソコン、電卓、電子辞書などの電子機器すべてに用いることができる。
また、実施形態では、ＩＣのＢＧＡ実装でのアンダーフィル材の塗布による接着としたが、ＩＣ、ＢＧＡ、アンダーフィル材に限らず、他の電子部品を含む任意の接着材による接着であっても良い。
さらに、スリットの形状等も任意であり、その他、具体的な細部構造等についても適宜に変更可能であることは勿論である。 (Modification)
In the above embodiment, the cellular phone is used. However, the present invention is not limited to this, and all electronic devices such as a digital camera, a video camera, a PDA, a notebook computer, a wearable computer, a calculator, and an electronic dictionary are used. Can be used.
In the embodiment, the bonding is performed by applying the underfill material in the BGA mounting of the IC. However, the bonding is not limited to the IC, the BGA, and the underfill material, but may be performed by any adhesive including other electronic components. good.
Furthermore, the shape of the slits and the like are arbitrary, and it is needless to say that other specific detailed structures can be appropriately changed.

本発明を適用した電子機器の一実施形態の構成を示すもので、携帯電話を開いた使用状態を示した正面図（ａ）と側面図（ｂ）である。BRIEF DESCRIPTION OF THE DRAWINGS The structure of one Embodiment of the electronic device to which this invention is applied is shown, (a) and the side view (b) which showed the use condition which opened the mobile telephone. 図１の携帯電話を折り畳んだ状態として内部の基板接続構成例を示した側面図である。It is the side view which showed the example of an internal board | substrate connection structure as the state which folded the mobile telephone of FIG. 本発明により基板上に隣接する電子部品を接着した実施形態１を示す断面図である。It is sectional drawing which shows Embodiment 1 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 図３の電子部品の電気的接続工程及び接着工程を示したフローチャートである。It is the flowchart which showed the electrical connection process and adhesion process of the electronic component of FIG. 本発明による隣接する電子部品間にブリッジ部なし品と比較例のブリッジ部あり品との歪測定結果例を示した荷重‐歪線図である。It is a load-strain diagram showing an example of a strain measurement result of a product without a bridge portion between adjacent electronic components according to the present invention and a product with a bridge portion of a comparative example. 本発明により基板上に隣接する電子部品を接着した実施形態２を示す断面図である。It is sectional drawing which shows Embodiment 2 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 本発明により基板上に隣接する電子部品を接着した実施形態３を示す断面図である。It is sectional drawing which shows Embodiment 3 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 本発明により基板上に隣接する電子部品を接着した実施形態４を示す断面図である。It is sectional drawing which shows Embodiment 4 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 本発明により基板上に隣接する電子部品を接着した実施形態５を示す断面図である。It is sectional drawing which shows Embodiment 5 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 本発明により基板上に隣接する電子部品を接着した実施形態６を示す断面図である。It is sectional drawing which shows Embodiment 6 which adhere | attached the electronic component adjacent on a board | substrate by this invention. 図１０の隣接する電子部品を上方から示した平面図である。It is the top view which showed the adjacent electronic component of FIG. 10 from upper direction. 一例として基板上に隣接する電子部品間にブリッジ部が発生した場合を示した断面図である。It is sectional drawing which showed the case where the bridge | bridging part generate | occur | produced between the electronic components adjacent on a board | substrate as an example. 図１２の基板に荷重がかかってブリッジ部にクラックが発生した場合を示した図である。It is the figure which showed the case where a load applied to the board | substrate of FIG. 12 and the crack generate | occur | produced in the bridge part.

符号の説明Explanation of symbols

１・２ 筐体
６・７ 回路基板
３０ 基板
３１・３２ 隣接する電子部品
３３・３４ ＢＧＡ
３５ アンダーフィル材（接着材）
３６ フィレット部
４１ 逆フィレット部形状の形成型
４２ 平板部
４３ スリット
４５ 冶具
１２７ ブリッジ部
１２８ クラック 1.2 Case 6/7 Circuit board 30 Board 31/32 Adjacent electronic parts 33/34 BGA
35 Underfill material (adhesive)
36 Fillet portion 41 Reverse fillet forming die 42 Flat plate portion 43 Slit 45 Jig 127 Bridge portion 128 Crack

Claims (9)

基板と、当該基板に電気的に接続された隣接する電子部品との接続信頼性を向上させる
電子部品の接着方法であって、
前記隣接する電子部品の周囲に接着材を塗布する接着材塗布ステップと、
当該接着材塗布ステップによって前記隣接する電子部品間に塗布された接着材の上から前記接着材の形状を所望のフィレット部形状に規定するための逆フィレット部形状の形成型を載置する型載置ステップと、
当該型載置ステップによって逆フィレット部形状の形成型が載置された状態で前記接着材を硬化させる硬化ステップと、
を含み、
前記型載置ステップは、前記逆フィレット部形状の形成型を前記隣接する電子部品の少
なくとも一方に接着する接着ステップを含むことを特徴とする電子部品の接着方法。 An electronic component bonding method for improving connection reliability between a substrate and an adjacent electronic component electrically connected to the substrate,
An adhesive application step of applying an adhesive around the adjacent electronic component;
A mold for placing a reverse fillet-shaped forming mold for defining the shape of the adhesive into a desired fillet shape from above the adhesive applied between the adjacent electronic components in the adhesive application step. Placing step;
A curing step of curing the adhesive in a state where the forming mold of the inverted fillet shape is placed by the mold placing step;
Including
The mold mounting step includes an adhesion step of adhering the reverse fillet-shaped forming mold to at least one of the adjacent electronic components. 前記逆フィレット部形状の形成型には、前記隣接する電子部品間の応力を緩和するためのスリットが設けられていることを特徴とする請求項１に記載の電子部品の接着方法。 The formation type front Kigyaku fillet shape, method for bonding an electronic component according to claim 1, characterized in that the slits for reducing the stress between an electronic component to the adjacent are provided. 前記逆フィレット部形状の形成型には、フェライトが混入されていることを特徴とする請求項１又は２に記載の電子部品の接着方法。 The formation type front Kigyaku fillet shape, method for bonding an electronic component according to claim 1 or 2, characterized in that the ferrite is mixed. 前記逆フィレット部形状の形成型は、前記隣接する電子部品間に形成されるブリッジ部の発生を抑制する形状であることを特徴とする請求項１から３のいずれか一項に記載の電子部品の接着方法。   The electronic component according to any one of claims 1 to 3, wherein the reverse fillet-shaped forming die is a shape that suppresses generation of a bridge portion formed between the adjacent electronic components. Bonding method. 前記型載置ステップは、前記隣接する電子部品間に形成される所望のフィレット部形状を安定的に規定するための加圧ステップを含むことを特徴とする請求項１から４のいずれか一項に記載の電子部品の接着方法。   5. The mold placing step includes a pressurizing step for stably defining a desired fillet portion shape formed between the adjacent electronic components. The adhesion method of the electronic component as described in 2. 前記接着材は、前記基板と前記電子部品と隙間に入り込むアンダーフィル材であることを特徴とする請求項１から５のいずれか一項に記載の電子部品の接着方法。   6. The electronic component bonding method according to claim 1, wherein the adhesive is an underfill material that enters a gap between the substrate and the electronic component. 7. 前記逆フィレット部形状の形成型は、前記隣接する電子部品間の応力を緩和する弾性部材により形成されていることを特徴とする請求項１から６のいずれか一項に記載の電子部品の接着方法。   The adhesion part for an electronic component according to any one of claims 1 to 6, wherein the reverse fillet-shaped forming die is formed by an elastic member that relieves stress between the adjacent electronic components. Method. 請求項１から７のいずれか一項に記載の電子部品の接着方法によって接着された隣接する電子部品を備えることを特徴とする回路基板。 Circuit board, characterized in that it comprises an electronic component adjacent adhered by a method of bonding an electronic component according to any one of claims 1 to 7. 請求項８に記載の回路基板を備えることを特徴とする電子機器。 An electronic apparatus comprising the circuit board according to claim 8 .
JP2008213683A 2008-08-22 2008-08-22 Electronic component bonding method, circuit board, and electronic apparatus Expired - Fee Related JP5234761B2 (en)

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