JP5207422B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device.

  In recent years, flat display devices have been actively developed, and among them, liquid crystal display devices have been applied to various fields by taking advantage of features such as light weight, thinness, and low power consumption. In particular, liquid crystal display devices in the horizontal electric field mode, such as IPS (In-Plane Switching) mode and FFS (Fringe-Field Switching) mode, have excellent viewing angle characteristics (change in image quality when the display device is tilted from the front. Is used in many portable devices.

  For example, according to Patent Document 1, a first substrate on which a common electrode, a pixel electrode, and a ground electrode are formed, and a conductive layer is formed on a surface opposite to the first substrate side, and the conductive layer side A second substrate having a through-hole penetrating from the surface to the surface on the first substrate side, and an electro-optical material sandwiched between the first substrate and the second substrate, and the conductive layer is disposed in the through-hole A lateral electric field type electro-optical device electrically connected to a grounding electrode through a conductive member or the like is disclosed.

JP 2009-8971 A

  A liquid crystal display device in a horizontal electric field mode such as an IPS mode or an FFS mode has an electrode for forming a horizontal electric field in the array substrate, whereas the counter substrate does not have an electrode. For this reason, when charge flows from the outside into the liquid crystal display panel or is charged as it is driven, there is a risk of adversely affecting the display quality such as occurrence of uneven brightness and increased flicker. For this reason, in order to suppress such a phenomenon, the structure which installs a shield electrode between a counter substrate and a polarizing plate is employ | adopted a lot.

  An object of the present invention is to provide a liquid crystal display device in a horizontal electric field mode, which has a good display quality.

According to this embodiment,
A first substrate including a first insulating substrate, a pixel electrode and a counter electrode disposed above the first insulating substrate, a second insulating substrate, and the first substrate of the second insulating substrate facing each other. A first light-shielding layer having a frame portion formed in a frame shape on the inner side of the substrate end portion of the second insulating substrate, and the first insulating layer disposed on the side of the second insulating substrate facing the first substrate. A second substrate including a second light-shielding layer spaced from the light-shielding layer and extending to a substrate end of the second insulating substrate; and a liquid crystal layer held between the first substrate and the second substrate And a third light-shielding layer that shields light between the first light-shielding layer and the second light-shielding layer, and a substrate end disposed on a surface of the second insulating substrate opposite to the side facing the first substrate. And a conductive shield member having optical transparency extending to the portion. The liquid crystal display device is provided.

  According to the present invention, it is possible to provide a liquid crystal display device in a horizontal electric field mode, which has a good display quality.

FIG. 1 schematically shows a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG. FIG. 3 is a schematic plan view of the pixel structure of the array substrate shown in FIG. 2 as viewed from the counter substrate side. FIG. 4 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel in which the pixel shown in FIG. 3 is cut along the line AB. FIG. 5 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel in which the pixel shown in FIG. 3 is cut along line CD. FIG. 6 shows a main part of the liquid crystal display panel LPN1 in which the first light shielding layer formed on the counter substrate does not extend to the end of the substrate, and the liquid crystal display panel LPN2 in which the first light shielding layer extends to the end of the substrate. It is a top view which shows roughly the principal part. FIG. 7 is a schematic plan view of the configuration of the liquid crystal display panel in the present embodiment as viewed from the counter substrate side. FIG. 8 is a schematic plan view showing an example of a first light shielding layer and a second light shielding layer applicable to the liquid crystal display panel shown in FIG. FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel shown in FIG. 7 taken along line EF. FIG. 10 is a diagram illustrating an example of measurement results of the flicker rate of the liquid crystal display panel LPN2 illustrated in FIG. 6 and the liquid crystal display panel LPN of the present embodiment. FIG. 11 is an enlarged schematic cross-sectional view of the structure of the region P in the liquid crystal display panel shown in FIG. FIG. 12 is an enlarged schematic cross-sectional view of another structure of the region P in the liquid crystal display panel shown in FIG. FIG. 13 is a plan view schematically showing an arrangement example of the third light shielding layer facing the slit. FIG. 14 is a cross-sectional view schematically showing another cross-sectional structure of the liquid crystal display panel shown in FIG. 7 cut along line EF. FIG. 15 is a cross-sectional view schematically showing another cross-sectional structure of the liquid crystal display panel shown in FIG. 7 cut along line EF. FIG. 16 is a cross-sectional view schematically illustrating a configuration example for applying a fixed potential to the first light shielding layer. FIG. 17 is a schematic plan view showing another example of the first light shielding layer and the second light shielding layer applicable to the liquid crystal display panel shown in FIG. FIG. 18 is a diagram for describing writing of an image signal in the pixel display mode. FIG. 19 is a diagram for explaining detection signal writing and detection operations in the detection mode.

  Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 and a flexible wiring board 3 connected to the liquid crystal display panel LPN, a backlight 4 that illuminates the liquid crystal display panel LPN, and the like. .

  The liquid crystal display panel LPN is held between an array substrate (first substrate) AR, a counter substrate (second substrate) CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown). Such a liquid crystal display panel LPN includes an active area (screen part) ACT for displaying an image. The active area ACT is composed of a plurality of pixels PX arranged in a matrix of m × n (where m and n are positive integers).

  The backlight 4 is disposed on the back side of the array substrate AR. As such a backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) as a light source or a cold cathode tube (CCFL) is applicable. Description of the detailed structure is omitted.

  In the liquid crystal display device 1 of the present embodiment, a display surface is formed on the counter substrate CT side. Further, in the liquid crystal display device 1 of the type in which the touch panel function is built in the liquid crystal display panel LPN, a display surface is formed on the counter substrate CT side and a detection surface for detecting contact is formed.

  FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG.

  The array substrate AR and the counter substrate CT are substantially rectangular, for example. The array substrate AR has a first side AR1, a second side AR2, a third side AR3, and a fourth side AR4. The counter substrate CT has a first side CT1, a second side CT2, a third side CT3, and a fourth side CT4. The second side CT2 of the counter substrate CT is located immediately above the second side AR2 of the array substrate AR, and similarly, the third side CT3 of the counter substrate CT is located immediately above the third side AR3 of the array substrate AR. The fourth side CT4 of the substrate CT is located immediately above the fourth side AR4 of the array substrate AR. The first side CT1 of the counter substrate CT is located inside the first side AR1 of the array substrate AR, that is, on the active area ACT side.

  Note that the first side CT1, the second side CT2, the third side CT3, and the fourth side CT4 in the counter substrate CT correspond to substrate end portions of a second insulating substrate, which will be described later, constituting the counter substrate CT.

  In the active area ACT, the array substrate AR includes n gate wirings G (G1 to Gn) and n capacitance lines C (C1 to Cn) that extend along the X direction, and a Y direction that intersects the X direction. In each pixel PX, m source wirings S (S1 to Sm) extending along the line, and m × n switching elements SW electrically connected to the gate wiring G and the source wiring S in each pixel PX There are provided m × n pixel electrodes PE electrically connected to the switching element SW, a counter electrode CE that is a part of the capacitor line C and faces the pixel electrode PE, and the like. The storage capacitor Cs is formed between the capacitor line C and the pixel electrode PE. The liquid crystal layer LQ is interposed between the pixel electrode PE and the counter electrode CE.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. Each capacitance line C is drawn outside the active area ACT and connected to the third drive circuit CD. At least a part of the first drive circuit GD, the second drive circuit SD, and the third drive circuit CD is formed on the array substrate AR and is electrically connected to the drive IC chip 2.

  In the illustrated example, the driving IC chip 2 is mounted on the array substrate AR outside the active area ACT. The driving IC chip 2 is located between the first side CT1 of the counter substrate CT and the first side AR1 of the array substrate AR. In addition, illustration of a flexible wiring board is abbreviate | omitted and the terminal T for connecting a flexible wiring board is formed in array board | substrate AR. The terminals T are arranged side by side on the first side AR1 of the array substrate AR. Among the terminals T, the common terminal Tcom is connected to a common wiring Vcom having a common potential. The common wiring Vcom passes outside the first drive circuit GD and the third drive circuit CD, and is disposed along the second side AR2, the third side AR3, and the fourth side AR4 of the array substrate AR.

  The driving IC chip 2 includes an image signal writing circuit 2A that performs control necessary for writing an image signal to the pixel electrode PE of each pixel PX in an image display mode in which an image is displayed in the active area ACT. Further, in the type having a built-in touch panel function, the driving IC chip 2 includes the static signal between the capacitor line C and the source line S in the detection mode for detecting contact of an object on the detection surface in addition to the image signal writing circuit 2A. A detection circuit 2B that detects a change in capacitance is provided. Details will be described later.

  FIG. 3 is a schematic plan view of the structure of the pixel PX in the array substrate AR shown in FIG. 2 as viewed from the counter substrate CT side. In this case, the array substrate AR includes the pixel electrode PE and the counter electrode CE, and the liquid crystal layer is mainly formed by utilizing a lateral electric field (that is, an electric field substantially parallel to the main surface of the substrate) formed between them. A configuration to which an FFS mode for switching liquid crystal molecules is applied will be described.

  Each of the gate lines G extends in the X direction. Each of the source lines S extends in the Y direction. The Y direction is a direction orthogonal to the X direction. The switching element SW is disposed in the vicinity of the intersection of the gate line G and the source line S, and is configured by, for example, a thin film transistor (TFT). The switching element SW includes a semiconductor layer SC. The semiconductor layer SC can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here.

  The gate electrode WG of the switching element SW is located immediately above the semiconductor layer SC and is electrically connected to the gate wiring G (in the illustrated example, the gate electrode WG is formed integrally with the gate wiring G. ) The source electrode WS of the switching element SW is electrically connected to the source line S (in the illustrated example, the source electrode WS is formed integrally with the source line S). The drain electrode WD of the switching element SW is electrically connected to the pixel electrode PE.

  The capacitance line C extends in the X direction. That is, the capacitor line C is disposed in each pixel PX and extends above the source line S, and is provided in common to each pixel PX adjacent in the X direction. The capacitance line C includes a counter electrode CE formed corresponding to each pixel PX. The counter electrode CE corresponds to a portion of the capacitor line C that generally faces the pixel electrode PE. The counter electrodes CE are electrically connected to each other above the source line S. In the illustrated example, the capacitor line C is provided in common to a plurality of pixels PX for one row arranged in the X direction between two gate lines G adjacent in the Y direction.

  The pixel electrode PE of each pixel PX is disposed above the counter electrode CE. Each pixel electrode PE is formed in an island shape corresponding to the pixel shape in each pixel PX, for example, a substantially square shape. Each of these pixel electrodes PE is connected to the drain electrode WD of the switching element SW. Each pixel electrode PE has a slit PSL. In the illustrated example, four slits PSL extend in the Y direction per pixel electrode PE. Of course, these slits PSL are located above the counter electrode CE.

  FIG. 4 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel LPN obtained by cutting the pixel PX shown in FIG. 3 along the line AB.

  That is, the array substrate AR is formed by using a first insulating substrate 20 having a light transmission property such as a glass plate. The array substrate AR includes a switching element SW, a capacitor line C including a counter electrode CE, and a pixel electrode PE on the inner surface of the first insulating substrate 20 (that is, the surface facing the liquid crystal layer LQ). The switching element SW shown here is a top-gate thin film transistor.

  The semiconductor layer SC is disposed on the first insulating substrate 20. Such a semiconductor layer SC is covered with the gate insulating film 21. The gate insulating film 21 is also disposed on the first insulating substrate 20. Although not shown, an undercoat layer that is an insulating film may be interposed between the first insulating substrate 20 and the semiconductor layer SC.

  The gate electrode WG of the switching element SW is disposed on the gate insulating film 21 and is located immediately above the semiconductor layer SC. Although not shown, the gate wiring is also disposed on the gate insulating film 21 and is formed of the same material as the gate electrode WG. Such a gate electrode WG and a gate wiring are covered with a first interlayer insulating film 22. The first interlayer insulating film 22 is also disposed on the gate insulating film 21. The gate insulating film 21 and the first interlayer insulating film 22 are made of an inorganic material such as silicon nitride (SiN), for example.

  The source electrode WS and the drain electrode WD of the switching element SW are disposed on the first interlayer insulating film 22. The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the gate insulating film 21 and the first interlayer insulating film 22. The source wiring S is also disposed on the first interlayer insulating film 22 and is formed of the same material as the source electrode WS. These gate electrode WG, source electrode WS, and drain electrode WD are formed of a light-shielding (or physical property that hardly transmits light) conductive material such as molybdenum, aluminum, tungsten, or titanium, for example.

  The source electrode WS, the drain electrode WD, and the source line S are covered with the second interlayer insulating film 23. The second interlayer insulating film 23 is also disposed on the first interlayer insulating film 22. Such a second interlayer insulating film 23 is formed of various resin materials such as an ultraviolet curable resin and a thermosetting resin.

  The capacitor line C or the counter electrode CE is disposed on the second interlayer insulating film 23. The capacitor line C or the counter electrode CE is covered with the third interlayer insulating film 24. The third interlayer insulating film 24 is also disposed on the second interlayer insulating film 23. Such a third interlayer insulating film 24 is formed of the above-described inorganic material or resin material.

  The pixel electrode PE is disposed on the third interlayer insulating film 24. The pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 23 and the third interlayer insulating film 24. A slit PSL is formed in the pixel electrode PE. The slits PSL of the pixel electrode PE are formed with a pitch of 5 to 6 μm, for example.

  The capacitive line C or the counter electrode CE and the pixel electrode PE are both electrically transparent conductive materials, for example, almost transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). Is formed by. The pixel electrode PE and the counter electrode CE facing each other via the third interlayer insulating film 24 form a storage capacitor Cs. The pixel electrode PE is covered with the first alignment film 25. The first alignment film 25 is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass plate. The counter substrate CT includes a first light shielding layer 51 and a color filter layer 32 on the inner surface of the second insulating substrate 30 (that is, the surface facing the liquid crystal layer LQ).

  The first light shielding layer 51 is disposed on the second insulating substrate 30. The first light shielding layer 51 includes a partition portion (or sometimes referred to as a black matrix) 511 that partitions each pixel PX. The partition portion 511 is arranged so as to face the wiring portions such as the gate wiring G and the source wiring S provided on the array substrate AR, and further the switching element SW, and is formed in a substantially lattice shape.

The first light shielding layer 51 is made of, for example, a resin material exhibiting black color in which carbon black or the like is dispersed, or a light shielding metal material such as chromium (Cr). In addition, the first light shielding layer 51 has conductivity (in this case, including a very wide range from several Ω / cm ² to 10 ¹² Ω / cm ² or more which is an antistatic level).

  The color filter layer 32 is disposed on the second insulating substrate 30. More specifically, the color filter layer 32 may be disposed on the inner side surrounded by the partition portion 511, and a part of the color filter layer 32 may overlap the partition portion 511. Such a color filter layer 32 is formed of resin materials colored in a plurality of different colors, for example, three primary colors such as red, blue, and green.

  In the horizontal electric field mode liquid crystal display panel LPN as described above, it is desirable that the surface of the counter substrate CT in contact with the liquid crystal layer LQ is flat, and the counter substrate CT further includes the first light shielding layer 51 and the color filter layer 32. Is provided with an overcoat layer 33 for flattening the surface irregularities. In the illustrated example, the overcoat layer 33 is disposed on the first light shielding layer 51 and the color filter layer 32. Such an overcoat layer 33 is formed of a resin material having optical transparency. The overcoat layer 33 is covered with the second alignment film 34. The second alignment film 34 is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT. The first alignment film 25 and the second alignment film 34 are made of polyimide, for example.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 25 and the second alignment film 34 face each other. At this time, a spacer (not shown) (for example, a columnar spacer integrally formed on one substrate with a resin material) is disposed between the array substrate AR and the counter substrate CT, whereby a predetermined cell gap is formed. It is formed. The array substrate AR and the counter substrate CT are bonded to each other with a seal member in a state where a predetermined cell gap is formed.

  The liquid crystal layer LQ is composed of a liquid crystal composition sealed in a cell gap formed between the first alignment film 25 of the array substrate AR and the second alignment film 34 of the counter substrate CT. The cell gap between the array substrate AR and the counter substrate CT, that is, the layer thickness of the liquid crystal layer LQ between the first alignment film 25 and the second alignment film 34 is, for example, 3 μm.

  A first polarizing plate PL1 is disposed on one outer surface of the liquid crystal display panel LPN, that is, on the outer surface of the first insulating substrate 20 constituting the array substrate AR. Further, a light transmissive shield member SE is disposed on the other outer surface of the liquid crystal display panel LPN, that is, the outer surface of the second insulating substrate 30 constituting the counter substrate CT. Two polarizing plates PL2 are arranged.

  The shield member SE may be a so-called shield electrode formed of a light-transmitting conductive material such as ITO, or a conductive paste for adhering the second polarizing plate PL2 to the outer surface of the second insulating substrate 30. It may be. Although not shown, the shield member SE is electrically connected to a shield wiring formed on the array substrate AR via a conductive member. The shield wiring is grounded, for example. Such a shield member SE shields an electrical element such as static electricity from the outside which is unnecessary for driving the liquid crystal molecules. That is, by disposing the shield member SE, it is possible to suppress an undesired electric field from entering the liquid crystal layer LQ.

  FIG. 5 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel LPN in which the three pixels PX shown in FIG. 3 are cut along the line CD. The same components as those described with reference to FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. Here, a case will be described in which the three pixels PX shown in FIG. 3 are a red pixel PXR, a green pixel PXG, and a blue pixel PXB in order from the left side.

  Each source line S is disposed on the first interlayer insulating film 22. These source lines S are covered with a second interlayer insulating film 23. Such a source line S is located between the pixels PX adjacent in the X direction on the array substrate AR. Above the source wiring S, the partition part 511 of the first light shielding layer 51 formed on the counter substrate CT is located.

  The capacitor line C including the counter electrode CE is disposed on the second interlayer insulating film 23. The pixel electrode PE faces the counter electrode CE of the capacitor line C on the third interlayer insulating film 24 covering the capacitor line C.

  The counter substrate CT includes, as the color filter layer 32, a color filter layer 32R that exhibits red, a color filter layer 32G that exhibits green, and a color filter layer 32B that exhibits blue. The color filter layer 32R is disposed corresponding to the red pixel PXR. The color filter layer 32G is arranged corresponding to the green pixel PXG. The color filter layer 32B is disposed corresponding to the blue pixel PXB. The partition portions 511 of the first light shielding layer 51 are respectively between the red pixel PXR and the green pixel PXG, between the green pixel PXG and the blue pixel PXB, and between the red pixel PXR and the blue pixel PXB (not shown). The pixels PX are partitioned to block light between adjacent pixels PX.

  FIG. 6 shows the main part of the liquid crystal display panel LPN1 in which the first light shielding layer 51 formed on the counter substrate CT does not extend to the substrate end, and the liquid crystal in which the first light shielding layer 51 extends to the substrate end. 4 is a plan view schematically showing main parts of a display panel LPN2. FIG.

  In the liquid crystal display panel LPN1, the first light shielding layer 51 is formed inside any one of the first side CT1, the second side CT2, the third side CT3, and the fourth side CT4 of the counter substrate CT. . On the other hand, in the liquid crystal display panel LPN2, the first light shielding layer 51 extends to the first side CT1, the second side CT2, the third side CT3, and the fourth side CT4 of the counter substrate CT. That is, in the liquid crystal display panel LPN2, the first light shielding layer 51 is exposed from the substrate end of the counter substrate CT.

  As shown in the figure, when the liquid crystal display panel LPN1 and the liquid crystal display panel LPN2 are compared, the latter liquid crystal display panel LPN2 is more advantageous for downsizing (especially narrow frame). In addition, in various electronic devices such as display devices and portable devices that employ such a liquid crystal display panel LPN2, it is possible to expect miniaturization and improvement in appearance (designability).

  However, in the liquid crystal display panel LPN2, since the first light shielding layer 51 has conductivity as described above, it is exposed when a human finger or a module member on the electronic device side comes into contact with the edge of the substrate. Charges in and out of the first light shielding layer 51 easily occur. Since the first light shielding layer 51 is electrically connected to the partition portion 511 disposed in the active area ACT, the first light shielding layer 51 is non-uniform in the active area ACT due to the entry and exit of charges from the edge of the substrate. A charge distribution may be formed. For this reason, even if the shield member SE is installed to shield the external electric field, the display quality may be adversely affected due to the non-uniform charge distribution in the active area ACT.

  More specifically, for example, when a human finger or the like touches the edge of the substrate, display unevenness or flicker fluctuation occurs. In particular, when flicker fluctuations occur, when adjusting the flicker by adjusting the potential of the capacitance line C, an adjustment deviation occurs, and the product performance may be impaired.

  It should be noted that when a conductive foreign object adheres to the edge of the substrate, or a conductive material for electrically connecting a shield member (not shown) disposed on the outer surface of the counter substrate CT and the shield wiring formed on the array substrate AR. Even when the member comes into contact with the first light shielding layer 51 at the edge of the substrate, or when a conductive foreign substance is interposed between the conductive member and the edge of the substrate and shorts with the first light shielding layer 51, the above-mentioned Problems may occur.

  FIG. 7 is a schematic plan view of the configuration of the liquid crystal display panel LPN in the present embodiment as viewed from the counter substrate CT side.

  The drive IC chip 2 and the flexible wiring board 3 are connected to the array substrate AR. A shield wiring 60 is formed on the array substrate AR. For example, the shield wiring 60 is electrically connected to the flexible wiring board 3 and grounded.

  A shield member SE is formed on the counter substrate CT. In the illustrated example, the shield member SE extends to the first side CT1, the second side CT2, the third side CT3, and the fourth side CT4 of the counter substrate CT. The shield member SE is electrically connected to the shield wiring 60 via a conductive member 61 such as a conductive tape or a conductive paste in the vicinity of the first side CT1. On such a shield member SE, a second polarizing plate PL2 is arranged.

  FIG. 8 is a schematic plan view showing an example of the first light shielding layer 51 and the second light shielding layer 52 applicable to the liquid crystal display panel LPN shown in FIG.

  The first light shielding layer 51 and the second light shielding layer 52 formed on the side of the counter substrate CT facing the array substrate AR are electrically insulated from each other. That is, the first light shielding layer 51 includes a partition part 511 and a frame part 512 connected to the partition part 511. That is, the partition part 511 and the frame part 512 are electrically connected. The partition unit 511 is disposed at a position corresponding to the active area ACT. The partition portion 511 extends in the X direction and the Y direction, and is formed in a lattice shape. The frame part 512 is connected to each terminal part of the partition part 511. The frame portion 512 is arranged along the periphery of the active area ACT and is formed in a frame shape. Such a frame part 512 is formed inside the first side CT1, the second side CT2, the third side CT3, and the fourth side CT4 of the counter substrate CT. That is, the frame portion 512 is formed inside the substrate end portion of the second insulating substrate 30 that constitutes the counter substrate CT.

  On the other hand, the second light shielding layer 52 is disposed away from the first light shielding layer 51 and outside the first light shielding layer 51. That is, the second light shielding layer 52 is not disposed in the active area ACT. In the illustrated example, the second light shielding layer 52 is formed in a frame shape outside the first light shielding layer 51, and the first side CT1, the second side CT2, the third side CT3, and the first side CT3 of the counter substrate CT. It extends to 4 sides CT4. That is, the second light shielding layer 52 extends to the substrate end portion of the second insulating substrate 30 constituting the counter substrate CT. In other words, a loop-shaped slit SL is formed between the first light shielding layer 51 and the second light shielding layer 52. The width of the slit SL is set to a distance sufficient to electrically insulate the first light shielding layer 51 and the second light shielding layer 52, and is about 10 μm, for example.

  Similar to the first light-shielding layer 51, the second light-shielding layer 52 is made of, for example, a resin material exhibiting black in which carbon black or the like is dispersed or a light-shielding metal material such as chromium (Cr). The first light-shielding layer 51 and the second light-shielding layer 52 may be formed of different light-shielding materials, but the first light-shielding layer 51 and the second light-shielding layer are used in order to reduce the number of manufacturing steps and improve the material utilization efficiency. It is desirable that 52 be formed collectively by a photolithography process using the same light-shielding material. When the 1st light shielding layer 51 and the 2nd light shielding layer 52 are formed in a lump, these each film thickness is substantially the same.

  FIG. 9 is a cross-sectional view schematically showing a cross-sectional structure of the liquid crystal display panel LPN shown in FIG. In FIG. 9, only the main parts necessary for explanation are shown.

  That is, the array substrate AR and the counter substrate CT constituting the liquid crystal display panel LPN are bonded together by the seal member SM. A liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT. The first polarizing plate PL1 is disposed on the outer surface of the array substrate AR, while the second polarizing plate PL2 is disposed on the outer surface of the counter substrate CT, that is, the outer surface of the second insulating substrate 30, via the shield member SE. . The first polarizing plate PL1 and the second polarizing plate PL2 cover at least the active area ACT. The shield member SE is electrically connected to the shield wiring 60 via the conductive member 61.

  In the counter substrate CT, the first light shielding layer 51 having the color filter layer 32, the partition portion 511, and the frame portion 512, and the second light shielding layer 52 are formed on the inner surface of the second insulating substrate 30 on the side facing the array substrate AR. Has been. In the illustrated example, the second light shielding layer 52 extends to the substrate end portion of the second insulating substrate 30 corresponding to the first side CT1 and the third side CT3 of the counter substrate CT. A slit SL penetrating to the second insulating substrate 30 is formed between the first light shielding layer 51 and the second light shielding layer 52. The overcoat layer 33 is disposed on the color filter layer 32, the first light shielding layer 51 having the partition part 511 and the frame part 512, and the second light shielding layer 52. In the illustrated example, the overcoat layer 33 further covers the slit SL.

  The array substrate AR includes a third light shielding layer 53 that shields light between the first light shielding layer 51 and the second light shielding layer 52. That is, the third light shielding layer 53 faces the slit SL formed between the first light shielding layer 51 and the second light shielding layer 52. The third light shielding layer 53 is formed of a light-shielding conductive material that forms various wirings provided in the array substrate AR, for example, the same material as at least one of the gate wiring and the source wiring. For this reason, the 3rd light shielding layer 53 has prevented that the backlight light from the backlight 4 leaks through the slit SL.

  According to the present embodiment having such a configuration, the first light shielding layer 51 including the partitioning portion 511 arranged corresponding to the active area ACT is not exposed at the substrate end, and extends to the substrate end. The second light shielding layer 52 and the first light shielding layer 51 disposed inside thereof are electrically insulated. For this reason, even if the charge enters and leaves the second light shielding layer 52 at the edge of the substrate, it is difficult to form a non-uniform charge distribution in the active area ACT, and the influence on the display quality can be reduced. It becomes possible. Therefore, it is possible to provide a liquid crystal display device that is compact and has excellent design and good display quality.

  FIG. 10 is a diagram illustrating an example of measurement results of the flicker rate of the liquid crystal display panel LPN2 illustrated in FIG. 6 and the liquid crystal display panel LPN of the present embodiment. In the figure, the horizontal axis represents time (minutes) and the vertical axis represents the flicker rate. The flicker rate is the flicker rate according to the VESA (Video Electronics Standards Association) standard (the flicker amplitude of the waveform when an electric signal obtained by photoelectrically converting the optical output of the liquid crystal display panel is input to an oscilloscope (p- p) and the average luminance (DC component) ratio), and is defined by the formula flicker rate = (flicker amplitude) / (average luminance).

  As shown in the figure, according to the liquid crystal display panel LPN of this embodiment, the fluctuation of the flicker rate with the passage of time can be suppressed as compared with the liquid crystal display panel LPN2 in which the first light shielding layer 51 is exposed at the edge of the substrate. Was confirmed.

  FIG. 11 is an enlarged schematic sectional view of the structure of the region P in the liquid crystal display panel LPN shown in FIG.

  The array substrate AR includes a third light shielding layer 53 formed on the gate insulating film 21. The third light shielding layer 53 is formed using the same material as the gate wiring (not shown), that is, a light shielding conductive material. That is, the third light shielding layer 53 is arranged in the same layer as the gate wiring. Such a third light shielding layer 53 is formed together with the gate wiring and the like by a photolithography process. The third light shielding layer 53 formed in this way is covered with the first interlayer insulating film 22.

  The width of the third light shielding layer 53 is desirably set larger than the width of the slit SL, that is, the distance between the first light shielding layer 51 and the second light shielding layer 52. At this time, it is desirable that the third light shielding layer 53 is disposed so as to face not only the slit SL but also the frame portion 512 of the first light shielding layer 51 and the second light shielding layer 52. Accordingly, it is possible to reliably block the backlight light from the oblique direction toward the slit SL, and it is possible to secure a sufficient margin for the misalignment between the array substrate AR and the counter substrate CT.

  In the illustrated example, the counter substrate CT includes a color filter layer 32 </ b> X between the first light shielding layer 51 and the second light shielding layer 52. That is, the color filter layer 32X is filled in the slit SL. Here, the thickness of the color filter layer 32X is the same as the thickness of the first light shielding layer 51 and the second light shielding layer 52, and the surface of the color filter layer 32X is the first light shielding layer 51 and the second light shielding layer 52. Although the same plane as the surface is formed, the thickness of the color filter layer 32 </ b> X is not necessarily the same as the thickness of the first light shielding layer 51 and the second light shielding layer 52. In addition, part of the color filter layer 32 </ b> X may overlap the first light shielding layer 51 and the second light shielding layer 52. In any case, it is desirable that the color filter layer 32X is disposed so as to fill the slit SL without any gap. The color filter layer 32 </ b> X, the first light shielding layer 51, and the second light shielding layer 52 are covered with the overcoat layer 33.

  Such a color filter layer 32X is formed of the same material as any color filter layer disposed in the active area ACT. As described above, when the active area ACT includes the color filter layer 32R that exhibits red, the color filter layer 32G that exhibits green, and the color filter layer 32B that exhibits blue, the color filter layer 32X has a visual sensitivity. It is formed of the same material as the blue color filter layer 32B which is the lowest color or the color having the lowest transmittance. The color filter layer 32 </ b> B and the color filter layer 32 </ b> X are desirably formed collectively by a photolithography process in order to reduce the number of manufacturing steps and improve the utilization efficiency of materials.

  Thus, by arranging the color filter layer 32X in the slit SL, a step difference between the surface of the first light shielding layer 51 and the second light shielding layer 52 and the surface of the second insulating substrate 30 (that is, the bottom surface of the slit SL) is reduced. can do. Further, even if the light shielding by the third light shielding layer 53 is insufficient, the color filter layer 32X can suppress light leakage from the slit SL.

  In the example shown in FIG. 11, the case where the third light shielding layer 53 is formed in the same layer as the gate wiring using the light shielding conductive material which is the same material as the gate wiring has been described. The light-shielding conductive material which is the same material may be used and formed in the same layer as the source wiring. In this case, the third light shielding layer 53 is formed together with the source wiring and the like by a photolithography process.

  FIG. 12 is an enlarged schematic sectional view of another structure of the region P in the liquid crystal display panel LPN shown in FIG.

  The illustrated example is different from the example illustrated in FIG. 11 in that the third light shielding layer 53 provided in the array substrate AR has a two-layer structure. That is, the third light shielding layer 53 includes a first segment 531 formed on the gate insulating film 21 and a second segment 532 formed on the first interlayer insulating film 22.

  The first segment 531 is formed in the same layer as the gate wiring using a light-shielding conductive material which is the same material as the gate wiring. The first segment 531 is covered with the first interlayer insulating film 22. The second segment 532 is formed in the same layer as the source wiring using a light-shielding conductive material that is the same material as the source wiring. Such a second segment 532 is covered with the second interlayer insulating film 23.

  In such a configuration, the widths of the first segment 531 and the second segment 532 are not necessarily set larger than the width of the slit SL. In the illustrated example, the first segment 531 is disposed so as to face the slit SL and the first light shielding layer 51, and the second segment 532 faces the first segment 531, the slit SL, and the second light shielding layer 52. Is arranged. That is, a part of the first light shielding layer 51 and a part of the second light shielding layer 52 are overlapped with each other via the first interlayer insulating film 22.

  Even in such a configuration, the same effect as described with reference to FIG. 11 can be obtained.

  FIG. 13 is a plan view schematically showing an arrangement example of the third light shielding layer 53 facing the slit SL.

  The third light shielding layer 53 formed on the array substrate AR faces substantially the entire slit SL formed on the counter substrate CT. In the illustrated example, the third light shielding layer 53 is formed in a frame shape so as to face the slit SL formed in a loop shape. The third light shielding layer 53 does not have to be formed as a single layer as a whole, and, for example, along the second side CT2, the third side CT3, and the fourth side CT4 of the counter substrate CT. The portion facing the formed slit SL is formed by the first segment 531 as shown in FIG. 12, and the portion facing the slit SL formed along the first side CT1 is the first segment shown in FIG. It may be formed with two segments 532.

  Since the third light shielding layer 53 is formed of a conductive material, it is necessary to prevent a short circuit with various wirings of the array substrate AR. For this reason, when the third light shielding layer 53 is formed on the array substrate AR, which of the first segment 531 and the second segment 532 is applied depends on the wiring and the third light shielding layer at a portion intersecting with the wiring. As appropriate, an interlayer insulating film is interposed between the first and second layers.

  The third light shielding layer 53 may be electrically floating, or may be a part of a wiring to which a predetermined potential is supplied. For example, at least a part of the third light shielding layer 53 may be the common wiring Vcom shown in FIG.

  FIG. 14 is a cross-sectional view schematically showing another cross-sectional structure of the liquid crystal display panel LPN shown in FIG. 7 cut along the line E-F.

  The illustrated example is different from the example illustrated in FIG. 9 in that the counter substrate CT includes a third light shielding layer 53.

  That is, in the counter substrate CT, the third light shielding layer 53 is formed on the inner surface of the second insulating substrate 30 on the side facing the array substrate AR. The third light shielding layer 53 is formed inside each side of the counter substrate CT and is not exposed from the substrate end of the second insulating substrate 30. Such a third light shielding layer 53 is covered with a first overcoat layer 331.

  The first light-shielding layer 51 and the second light-shielding layer 52 having the color filter layer 32, the partition part 511 and the frame part 512 are formed on the first overcoat layer 331 and covered with the second overcoat layer 332. ing. The second overcoat layer 332 also covers the slit SL between the first light shielding layer 51 and the second light shielding layer 52. The first overcoat layer 331 and the second overcoat layer 332 are formed of a light-transmitting resin material, like the overcoat layer 33 described above.

  In the example shown here, the first overcoat layer 331 corresponds to an interlayer insulating film interposed between the third light shielding layer 53 and the first light shielding layer 51 and the second light shielding layer 52. A third light shielding layer 53 is located immediately above the slit SL formed between the first light shielding layer 51 and the second light shielding layer 52.

  Even in such a configuration, the same effect as described with reference to FIG. 9 can be obtained. Further, since the third light shielding layer 53 is formed on the counter substrate CT, the possibility of intersecting with the wiring is extremely low as compared with the example of FIG. 9 formed on the array substrate AR, and the degree of freedom in layout is improved. it can.

  Note that the first light shielding layer 51 and the second light shielding layer 52 are disposed between the second insulating substrate 30 and the first overcoat layer 331, and the third light shielding layer 53 is the first overcoat layer 331 and the second overcoat. It may be arranged between the layer 332.

  FIG. 15 is a cross-sectional view schematically showing another cross-sectional structure of the liquid crystal display panel LPN shown in FIG. 7 cut along the line EF.

  The illustrated example is different from the example shown in FIG. 14 in that the third light shielding layer is omitted without forming a slit between the first light shielding layer 51 and the second light shielding layer 52. Yes.

  That is, in the counter substrate CT, the second light shielding layer 52 is formed on the inner surface of the second insulating substrate 30 on the side facing the array substrate AR. The second light shielding layer 52 extends to each side of the counter substrate CT and is exposed from the substrate end of the second insulating substrate 30. Such a second light shielding layer 52 is covered with a first overcoat layer 331.

  The color filter layer 32 and the first light shielding layer 51 having the partition part 511 and the frame part 512 are formed on the first overcoat layer 331 and covered with the second overcoat layer 332. In the example shown here, the first overcoat layer 331 corresponds to an interlayer insulating film interposed between the second light shielding layer 52 and the first light shielding layer 51.

  As shown in the enlarged view in the figure, the frame portion 512 of the first light shielding layer 51 is formed on the inner side of each side of the counter substrate CT, and at least the outer edge portion 512O of the first light-shielding layer 51 forms the first overcoat layer 331. Via the inner edge 52I of the second light shielding layer 52. That is, the counter substrate CT includes a stacked portion LM in which the outer edge portion 512O, the first overcoat layer 331, and the inner edge portion 52I are stacked.

  According to such a configuration, although the third light shielding layer is omitted, light leakage from between the first light shielding layer 51 and the second light shielding layer 52 that are electrically insulated can be prevented. . Therefore, the same effect as described with reference to FIG. 9 can be obtained.

  The first light shielding layer 51 is disposed between the second insulating substrate 30 and the first overcoat layer 331, and the second light shielding layer 52 is disposed between the first overcoat layer 331 and the second overcoat layer 332. It may be arranged.

  In the present embodiment described above, the first light shielding layer 51 is in an electrically floating state, but a fixed potential may be applied to the first light shielding layer 51.

  FIG. 16 is a cross-sectional view schematically showing a configuration example for applying a fixed potential to the first light shielding layer 51.

  Compared with the example shown in FIG. 9, the illustrated example includes the array substrate AR including the connection electrode 70, and further includes the conductive member 71 that electrically connects the first light shielding layer 51 and the connection electrode 70. It is different in point.

  That is, the connection electrode 70 faces the first light shielding layer 51. A fixed potential is applied to the connection electrode 70. The surface of the connection electrode 70 is exposed. On the other hand, in the overcoat layer 33 that covers the first light shielding layer 51, a through hole TH that penetrates to the first light shielding layer 51 is formed. The through hole TH faces the connection electrode 70. The conductive member 71 is, for example, a conductive paste or the like, and contacts the connection electrode 70 and contacts the first light shielding layer 51 through the through hole TH to electrically connect them.

  According to such a configuration, the same effect as described with reference to FIG. 9 can be obtained, and the state of the liquid crystal display panel LPN can be further stabilized.

  Note that the method of applying a fixed potential to the first light shielding layer 51 is not limited to the form in which the third light shielding layer 53 is formed on the array substrate AR as shown in FIG. 9, but the counter substrate CT as shown in FIG. The third light-shielding layer 53 is formed, and the first light-shielding layer 51 and the second light-shielding layer 52 are electrically insulated while omitting the third light-shielding layer as shown in FIG. Applicable.

  In the present embodiment described above, the second light shielding layer 52 is formed in a frame shape outside the first light shielding layer 51, but may not be disposed along the four sides of the counter substrate CT. That is, in the present embodiment, when the second light shielding layer 52 extending to the edge of the substrate is disposed along at least one side of the counter substrate CT, the second light shielding layer 52, the first light shielding layer 51, and Are electrically insulated.

  FIG. 17 is a schematic plan view showing another example of the first light shielding layer 51 and the second light shielding layer 52 applicable to the liquid crystal display panel LPN shown in FIG.

  The illustrated example is different from the example illustrated in FIG. 8 in that the second light shielding layer 52 along the third side CT3 of the counter substrate CT is omitted. That is, the first light shielding layer 51 includes a partition portion 511 and a frame-shaped frame portion 512. On the other hand, the second light shielding layer 52 is separated from the first light shielding layer 51 and outside the first light shielding layer 51, the first side CT1, the second side CT2, and the fourth side CT4 of the counter substrate CT. It extends to. That is, there is no second light shielding layer between the third side CT3 of the counter substrate CT and the frame portion 512 of the first light shielding layer 51. A substantially U-shaped slit SL is formed between the first light shielding layer 51 and the second light shielding layer 52.

  Even in such a configuration, the same effect as described with reference to FIG. 9 can be obtained.

  Next, the case where the liquid crystal display device of the present embodiment is a type in which a touch panel function is built in the liquid crystal display panel LPN will be described.

  FIG. 18 is a diagram for describing writing of an image signal in the pixel display mode.

  The image signal writing circuit 2A of the driving IC chip 2 controls the first driving circuit GD and outputs a control signal for turning on the switching element SW (not shown) to each gate wiring G. Further, the image signal writing circuit 2A controls the second drive circuit SD and outputs an image signal to each source line S. The image signal output to the source line S is written to the pixel electrode PE (not shown) via the switching element SW in the on state. On the other hand, the image signal writing circuit 2A controls the third drive circuit CD to apply a common voltage to each capacitor line C.

  As a result, a voltage corresponding to an image signal is applied to the liquid crystal layer LQ between the pixel electrode PE and the counter electrode CE of the capacitor line C. In the liquid crystal layer LQ, the liquid crystal molecules are aligned according to the applied voltage, and the modulation factor for the light transmitted through the liquid crystal layer LQ changes. Therefore, the backlight light emitted from the backlight 4 and incident on the liquid crystal display panel LPN selectively passes through the second polarizing plate PL2 depending on the voltage between the pixel electrode PE and the counter electrode CE. As a result, an image corresponding to the image signal is displayed on the display surface.

  FIG. 19 is a diagram for explaining detection signal writing and detection operations in the detection mode. In the detection mode, the pixel electrode PE is in a floating state.

  The detection circuit 2B of the drive IC chip 2 controls the third drive circuit CD to write a detection signal to the capacitor line C. Here, the detection signal is, for example, an AC signal. At this time, the third drive circuit CD simultaneously writes detection signals to the plurality of capacitor lines C, in the illustrated example, four adjacent capacitor lines C. In this method, a plurality of capacitive lines C are bundled to form a block, and these capacitive lines C are used as detection elements. Although not described in detail, the third drive circuit CD includes, for example, one or more switches connected to each capacitor line C, and in the image display mode, the switches are sequentially turned on to apply a common voltage to the capacitor line C. On the other hand, in the detection mode, the switches connected to the plurality of capacitance lines C are simultaneously turned on to write the detection signal.

  On the other hand, the detection circuit 2B controls the second drive circuit SD to precharge each source line S. Since an AC detection signal is written into the capacitor line C, the potential of the source wiring S varies. The detection circuit 2B reads the potential fluctuation of the source line S at this time. When an object approaches or comes in contact with the detection surface, the capacitance between the capacitance line C and the source line S changes. Along with such a change in capacitance, the potential fluctuation of the source wiring S also changes. For this reason, in the detection circuit 2B, by monitoring the change in the potential of the source line S or the change in the current value, the change in the capacitance between the capacitance line C and the source line S, that is, the change to the detection surface. An approach or contact of an object is detected.

  Note that the second drive circuit SD simultaneously reads potential fluctuations or current value fluctuations from a plurality of source lines S, in the illustrated example, twelve adjacent source lines S. In this method, a plurality of source lines S are bundled to form a block, and these source lines S are used as detection elements. Although not described in detail, the second drive circuit SD includes, for example, one or more switches connected to each source line S. In the image display mode, the second drive circuit SD is sequentially turned on to write an image signal to the source line S. On the other hand, in the detection mode, potential fluctuations or current fluctuations are read after the switches connected to the plurality of source lines S are simultaneously turned on and precharged.

  In the illustrated example, the detection signal is written to the capacitor line C and the potential fluctuation accompanying the change in the capacitance is read from the source line S. However, the detection signal is written to the source line S and the capacitance line C You may read the electric potential fluctuation | variation accompanying the change of a capacity | capacitance. In the detection mode, the number of the bundled capacitor lines C and source lines S is appropriately set according to the required detection sensitivity.

  In this detection mode, the combination of the capacitive line C and the source wiring S that are detection elements may be changed at each timing. For example, in the first timing, a plurality of adjacent detection elements (capacitor line C and source line S) are bundled, and in the second timing, the combination of bundling is changed to improve detection accuracy. Can do. For example, a plurality of detection elements that are bundled first and a plurality of adjacent detection elements may be bundled in half, every other detection element may be bundled, and every other detection element may be bundled. Such a bundling combination can be freely changed by a combination of switches connected to each detection element.

  Thus, in the liquid crystal display panel LPN having a built-in touch panel function using the electrodes (capacitor lines C and source lines S in the example shown) formed on the array substrate AR as capacitance detection electrodes, When the light shielding layer 51 is exposed at the edge of the substrate, the detection capacitance value changes due to the entry / exit of charges, etc., so that the detection sensitivity as a touch panel is remarkably lowered, and external noise is reduced. Since it is picked up, detection performance is impaired.

  On the other hand, according to the present embodiment, the second light shielding layer 52 exposed at the edge of the substrate is electrically insulated from the first light shielding layer 51 located in the active area, and also the first light shielding layer. Since the layer 51 is in a floating state, stable detection is possible.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

  Although the liquid crystal display device to which the FFS mode is applied has been described in the present embodiment, it is needless to say that the above configuration can be applied to a liquid crystal display device to which a lateral electric field mode such as the IPS mode is applied as well as the FFS mode.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 2 ... Drive IC chip 2A ... Image signal writing circuit 2B ... Detection circuit LPN ... Liquid crystal display panel AR ... Array substrate CT ... Opposite substrate LQ ... Liquid crystal layer ACT ... Active area PX ... Pixel G ... Gate wiring S ... source wiring PE ... pixel electrode C ... capacitor line CE ... counter electrode SL ... slit 51 ... first light shielding layer 511 ... partition part 512 ... frame part 52 ... second light shielding layer 53 ... third light shielding layer SE ... shielding member 60 ... Shield wiring 61 ... Conductive member 70 ... Connection electrode 71 ... Conductive member

Claims (5)

A first substrate comprising: a first insulating substrate; and a pixel electrode and a counter electrode disposed above the first insulating substrate;
A first light-shielding layer having a second insulating substrate and a frame portion formed in a frame shape inside the substrate end portion of the second insulating substrate on a side facing the first substrate of the second insulating substrate; A second substrate comprising: a second light shielding layer disposed on a side of the second insulating substrate facing the first substrate and spaced from the first light shielding layer and extending to a substrate end of the second insulating substrate;
A liquid crystal layer held between the first substrate and the second substrate;
A third light shielding layer that shields light between the first light shielding layer and the second light shielding layer;
A conductive shielding member having light transmissivity disposed on the surface of the second insulating substrate opposite to the side facing the first substrate and extending to the end of the substrate;
A liquid crystal display device comprising:   The liquid crystal display device according to claim 1, wherein the first substrate further includes shield wiring electrically connected to the shield member.   The liquid crystal display device according to claim 2, further comprising a flexible wiring board electrically connected to the shield wiring.   The liquid crystal display device according to claim 1, wherein the shield member is made of ITO or conductive glue.   The liquid crystal display device according to claim 1, further comprising a polarizing plate disposed on the shield member.

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