JP2012247542A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device having both a touch sensing function and a shielding function against an external electric field.SOLUTION: A liquid crystal display device comprises: a first substrate including in an active area displaying an image, a common electrode formed across a plurality of pixels, an insulation film covering the common electrode, a pixel electrode provided for each pixel on the insulation film, facing the common electrode, and having a slit, and a capacitive touch sensing wire; a second substrate including an insulation substrate; an optical element including a polarization plate disposed in the active area on the insulation substrate; a conductive layer disposed in the active area on the optical element; a ground potential pad formed in an extension part of the first substrate which extends outward beyond an end of the second substrate; and a connection member for electrically connecting the pad and the conductive layer exposed out of the optical element.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In recent years, a configuration in which a liquid crystal display panel for displaying an image has a touch sensing function has been disclosed.

JP 2010-231773 A JP 2011-054199 A

  An object of the present embodiment is to provide a liquid crystal display device having both a touch sensing function and a shielding function against an external electric field.

According to this embodiment,
In an active area for displaying an image, a common electrode formed over a plurality of pixels, an insulating film covering the common electrode, and formed on each pixel on the insulating film so as to face the common electrode and form a slit A first substrate having a pixel electrode and a capacitance touch sensing wiring, a second substrate having an insulating substrate, and a liquid crystal held between the first substrate and the second substrate An optical element including a layer, a polarizing plate disposed in the active area on the insulating substrate, a conductive layer disposed in the active area on the optical element, and an outer side than an end of the second substrate A pad having a ground potential formed on the extending portion of the first substrate extending to the first substrate, and a connecting member for electrically connecting the conductive layer exposed from the optical element and the pad. The liquid crystal display device is provided, wherein.

According to this embodiment,
In an active area for displaying an image, a common electrode formed over a plurality of pixels, an insulating film covering the common electrode, and formed on each pixel on the insulating film so as to face the common electrode and form a slit A first substrate having a pixel electrode and a capacitance touch sensing wiring; an insulating substrate; and an outer surface of the insulating substrate opposite to the inner surface facing the first substrate. A second substrate having a conductive layer disposed thereon, a liquid crystal layer held between the first substrate and the second substrate, and disposed in the active area on the conductive layer and the conductive layer An optical element including a part of the layer, including a polarizing plate, a ground potential pad formed on an extending portion of the first substrate extending outward from an end portion of the second substrate, and Optical element The liquid crystal display device comprising: the connecting member for electrically connecting, comprising the there is provided a to the conductive layer exposed and the pad from.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel constituting the liquid crystal display device of the present embodiment. FIG. 2 is a schematic plan view of the pixel structure in the array substrate shown in FIG. 1 as viewed from the counter substrate side. FIG. 3 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel in which the pixel shown in FIG. 2 is cut along the line AB. FIG. 4 is a plan view schematically showing the configuration of the liquid crystal display panel shown in FIG. FIG. 5 is a cross-sectional view schematically showing a cross section including the pad of the liquid crystal display panel shown in FIG. FIG. 6 is a plan view schematically showing the configuration of another liquid crystal display panel in the liquid crystal display device of the present embodiment. FIG. 7 is a cross-sectional view schematically showing a cross section including a pad of the liquid crystal display panel shown in FIG.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a liquid crystal display panel LPN constituting the liquid crystal display device of the present embodiment.

  That is, the liquid crystal display device includes an active matrix type liquid crystal display panel LPN. The liquid crystal display panel LPN is held between an array substrate (first substrate) AR, a counter substrate (second substrate) CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer LQ. Such a liquid crystal display panel LPN includes an active area ACT for displaying an image. The active area ACT is composed of a plurality of pixels PX arranged in a matrix of m × n (where m and n are positive integers).

  In the active area ACT, the array substrate AR includes n gate wirings G (G1 to Gn) and n capacitance lines C (C1 to Cn) that extend in the first direction X in the first direction X, respectively. M source lines S (S1 to Sm) each extending along the intersecting second direction Y, and mxn switching elements electrically connected to the gate line G and the source line S in each pixel PX SW, m × n pixel electrodes PE electrically connected to the switching element SW in each pixel PX, a common electrode CE which is a part of the capacitor line C and faces the pixel electrode PE, and the like. The storage capacitor Cs is formed between the capacitor line C and the pixel electrode PE.

  Each gate line G is drawn outside the active area ACT and is connected to the first drive circuit GD. Each source line S is drawn outside the active area ACT and connected to the second drive circuit SD. Each capacitance line C is drawn outside the active area ACT and connected to the third drive circuit CD. The first drive circuit GD, the second drive circuit SD, and the third drive circuit CD are formed on the array substrate AR and connected to the drive IC chip 2. In the illustrated example, the drive IC chip 2 is mounted on the array substrate AR outside the active area ACT of the liquid crystal display panel LPN.

  In the present embodiment, the driving IC chip 2 includes an image signal writing circuit 2A that performs control necessary for writing an image signal to the pixel electrode PE of each pixel PX in an image display mode in which an image is displayed in the active area ACT. In the touch sensing mode in which contact of an object is detected on the detection surface, the capacitance of the capacitive touch sensing wiring (capacitance between the capacitive line C and the source wiring S in the example shown here) is changed. And a detection circuit 2B for detecting.

  Further, the liquid crystal display panel LPN of the illustrated example includes the pixel electrode PE and the common electrode CE on the array substrate AR, and is substantially parallel to the main surface of the substrate in the lateral electric field (particularly the fringe electric field) formed therebetween. A fringe field switching (FFS) mode is employed in which the liquid crystal molecules constituting the liquid crystal layer LQ are switched using mainly a small electric field.

  FIG. 2 is a schematic plan view of the structure of the pixel PX in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side.

  The gate line G extends along the first direction X. The source line S extends along the second direction Y. The switching element SW is disposed in the vicinity of the intersection of the gate line G and the source line S, and is configured by, for example, a thin film transistor (TFT). The switching element SW includes a semiconductor layer SC. The semiconductor layer SC can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here.

  The gate electrode WG of the switching element SW is located immediately above the semiconductor layer SC and is electrically connected to the gate wiring G (in the illustrated example, the gate electrode WG is formed integrally with the gate wiring G. ) The source electrode WS of the switching element SW is electrically connected to the source line S (in the illustrated example, the source electrode WS is formed integrally with the source line S). The drain electrode WD of the switching element SW is electrically connected to the pixel electrode PE.

  The capacitance line C extends along the first direction X. That is, the capacitor line C is disposed in each pixel PX, extends above the source line S, and is formed in common across a plurality of pixels PX adjacent in the first direction X. The capacitor line C includes a common electrode CE formed corresponding to each pixel PX.

  The pixel electrode PE of each pixel PX is disposed above the common electrode CE. Each pixel electrode PE is formed in an island shape corresponding to the pixel shape in each pixel PX, for example, a substantially square shape. Each pixel electrode PE has a plurality of slits PSL facing the common electrode CE.

  FIG. 3 is a diagram schematically showing a cross-sectional structure of a liquid crystal display panel LPN obtained by cutting the pixel PX shown in FIG. 2 along the line AB.

  That is, the array substrate AR is formed by using a first insulating substrate 20 having optical transparency such as a glass substrate. The array substrate AR includes a switching element SW on the inner surface of the first insulating substrate 20 (that is, the surface facing the counter substrate CT). The switching element SW shown here is a top-gate thin film transistor. The semiconductor layer SC is formed on the first insulating substrate 20. Such a semiconductor layer SC is covered with the gate insulating film 21. The gate insulating film 21 is also disposed on the first insulating substrate 20.

  The gate electrode WG of the switching element SW is formed on the gate insulating film 21 and is located immediately above the semiconductor layer SC. Such a gate electrode WG is covered with a first interlayer insulating film 22. The first interlayer insulating film 22 is also disposed on the gate insulating film 21.

  The source electrode WS and the drain electrode WD of the switching element SW are formed on the first interlayer insulating film 22. The source electrode WS and the drain electrode WD are in contact with the semiconductor layer SC through contact holes that penetrate the gate insulating film 21 and the first interlayer insulating film 22. The source electrode WS and the drain electrode WD are covered with the second interlayer insulating film 23. The second interlayer insulating film 23 is also disposed on the first interlayer insulating film 22.

  The capacitor line C or the common electrode CE is formed on the second interlayer insulating film 23. The capacitor line C or the common electrode CE is covered with the third interlayer insulating film 24. The third interlayer insulating film 24 is also disposed on the second interlayer insulating film 23.

  The pixel electrode PE is formed on the third interlayer insulating film 24. The pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 23 and the third interlayer insulating film 24. Both the capacitor line C or the common electrode CE and the pixel electrode PE are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE and the common electrode CE facing each other through the third interlayer insulating film 24 form a storage capacitor CS. In addition, a slit PSL is formed in the pixel electrode PE. The slit PSL is located immediately above the common electrode CE. The pixel electrode PE is covered with the first alignment film 25. The first alignment film 25 is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  The source wiring S is formed on the first interlayer insulating film 22 and is covered with the second interlayer insulating film 23. A capacitor line C is located immediately above the source line S.

  On the other hand, the counter substrate CT is formed using a second insulating substrate 30 having optical transparency such as a glass substrate. The counter substrate CT includes a black matrix 31, a color filter 32, an overcoat layer 33, and the like that partition each pixel PX on the inner surface of the second insulating substrate 30 (that is, the surface facing the array substrate AR).

  The black matrix 31 is formed on the second insulating substrate 30 so as to face the gate wiring G and the source wiring S provided on the array substrate AR, and further to the wiring section such as the switching element SW. The color filter 32 is formed on the second insulating substrate 30 and is formed of a resin material colored in a plurality of different colors, for example, three primary colors such as red, blue, and green. The resin material colored red is arranged corresponding to the red pixel. Similarly, the resin material colored blue is arranged corresponding to the blue pixel, and the resin material colored green corresponds to the green pixel. Are arranged.

  The overcoat layer 33 is formed on the black matrix 31 and the color filter 32. The overcoat layer 33 flattens the unevenness of the surfaces of the black matrix 31 and the color filter 32. The overcoat layer 33 is covered with the second alignment film 34. The second alignment film 34 is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 25 and the second alignment film 34 face each other. At this time, a spacer (not shown) (for example, a columnar spacer integrally formed on one substrate with a resin material) is disposed between the array substrate AR and the counter substrate CT, thereby forming a predetermined gap. Is done. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a predetermined gap is formed. The liquid crystal layer LQ is composed of a liquid crystal composition sealed in a gap formed between the alignment film 25 of the array substrate AR and the alignment film 34 of the counter substrate CT.

  A backlight BL is arranged on the back side of the liquid crystal display panel LPN having such a configuration. A first optical element OD1 including a first polarizing plate PL1 is disposed on one outer surface of the liquid crystal display panel LPN, that is, the outer surface of the first insulating substrate 20 constituting the array substrate AR. The second optical element OD2 including the second polarizing plate PL2 is disposed on the other outer surface of the liquid crystal display panel LPN, that is, the outer surface of the second insulating substrate 30 constituting the counter substrate CT. In the illustrated example, the surface of the cover glass CG disposed above the first optical element OD1 serves as a detection surface. Note that a conductive layer described later is interposed between the second insulating substrate 30 and the second optical element OD2 or between the second optical element OD2 and the cover glass CG. Omitted.

  Next, an example of the image display mode and the touch sensing mode in the liquid crystal display device including the liquid crystal display panel LPN having the above-described configuration will be briefly described.

  In the pixel display mode, the image signal writing circuit 2A controls the first drive circuit GD to output a control signal for turning on the switching element SW of each pixel PX to each gate line G. Further, the image signal writing circuit 2A controls the second drive circuit SD and outputs an image signal to each source line S. The image signal output to the source line S is written to the pixel electrode PE through the switching element SW in the on state. On the other hand, the image signal writing circuit 2A controls the third drive circuit CD to apply a common voltage to each capacitor line C.

  As a result, a voltage corresponding to an image signal is applied to the liquid crystal layer LQ between the pixel electrode PE and the common electrode CE of the capacitor line C. In the liquid crystal layer LQ, the liquid crystal molecules are aligned according to the applied voltage, and the modulation factor for the light transmitted through the liquid crystal layer LQ changes. That is, in a state where no electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are substantially parallel to the main surface of the substrate due to the alignment regulating force of the first alignment film 25 and the second alignment film 34. The initial orientation is in a predetermined orientation in the plane. In a state where a fringe electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are aligned in a direction different from the initial alignment in a plane substantially parallel to the main surface of the substrate. The modulation factor with respect to the light transmitted through the liquid crystal layer LQ varies depending on the orientation direction of the liquid crystal molecules. For this reason, the backlight light emitted from the backlight BL and incident on the liquid crystal display panel LPN selectively passes through the polarizing plate PL2 depending on the voltage between the pixel electrode PE and the common electrode CE. As a result, an image corresponding to the image signal is displayed on the display surface.

  In the present embodiment, as an example of the touch sensing mode, the capacitance line C and the source wiring S are used as capacitance touch sensing wiring. That is, in the touch sensing mode, the detection circuit 2B controls the third drive circuit CD to write a detection signal to the capacitance line C. Here, the detection signal is, for example, an AC signal. On the other hand, the detection circuit 2B controls the second drive circuit SD to precharge each source line S. Since an AC detection signal is written into the capacitor line C, the potential of the source wiring S varies. The detection circuit 2B reads the potential fluctuation of the source line S at this time. When an object approaches or comes in contact with the detection surface, the capacitance between the capacitance line C and the source line S changes. Along with such a change in capacitance, the potential fluctuation of the source wiring S also changes. For this reason, in the detection circuit 2B, by monitoring the change in the potential of the source line S or the change in the current value, the change in the capacitance between the capacitance line C and the source line S, that is, the change to the detection surface. An approach or contact of an object is detected.

  Note that, here, a detection signal is written to the capacitor line C, and a potential variation accompanying a change in capacitance is read from the source line S. However, a detection signal is written to the source line S and the capacitance line C You may read the electric potential fluctuation | variation accompanying a change. In the touch sensing mode, a detection signal may be simultaneously written in a plurality of capacitance lines C to form a capacitive touch sensing wiring block including a plurality of capacitance lines C, or a plurality of sources. A block of capacitance touch sensing wiring composed of a plurality of source wirings S may be formed by simultaneously reading potential fluctuation or current value fluctuation from the wiring S. Further, here, the capacitive line C and the source line S are used as the capacitive touch sensing wiring. However, the capacitive line C and the source line S are not limited to this combination, and other wirings constituting the liquid crystal display panel LPN may be used. Alternatively, another wiring may be provided as the capacitive touch sensing wiring.

  FIG. 4 is a plan view schematically showing the configuration of the liquid crystal display panel LPN shown in FIG.

  The array substrate AR constituting the liquid crystal display panel LPN has an extending part ARE that extends outward from the end part CTE of the counter substrate CT. A driving IC chip 2 and a flexible printed circuit (FPC) substrate 3 are mounted on the extending portion ARE. In addition, a pad PD having a ground potential is formed in the extending portion ARE. Although not described in detail, the pad PD is grounded via the drive IC chip 2 and the FPC board 3.

  The second optical element OD2 is disposed over the entire active area ACT on the outer surface of the counter substrate CT. The size of the second optical element OD2 in the XY plane is often smaller than the size of the counter substrate CT in the XY plane. In this case, the end portion ODE of the second optical element OD2 does not overlap immediately above the end portion CTE of the counter substrate CT, but is positioned closer to the active area ACT side than the end portion CTE of the counter substrate CT. In the illustrated example, the end portion ODE of the second optical element OD2 having a quadrangular shape in the XY plane is positioned on the active area ACT side with respect to the end portion CTE of the counter substrate CT. That is, the vicinity of the four ends of the counter substrate CT is exposed from the second optical element OD2.

  The conductive layer CDF is disposed over the entire active area ACT on the second optical element OD2. In the example illustrated, the conductive layer CDF is formed over substantially the entire surface of the second optical element OD2. That is, the size of the second optical element OD2 in the XY plane is equal to the size of the conductive layer CDF in the XY plane. In the case of the illustrated example, the end portion CDFE of the conductive layer CDF is located immediately above the end portion ODE of the second optical element OD2, and is located closer to the active area ACT side than the end portion CTE of the counter substrate CT. .

  Note that the size of the conductive layer CDF in the XY plane may be smaller than the size of the second optical element OD2 in the XY plane. In this case, the end portion CDFE of the conductive layer CDF is located on the active area ACT side with respect to the end portion ODE of the second optical element OD2, and is located on the active area ACT side with respect to the end portion CTE of the counter substrate CT. To do.

  Such a conductive layer CDF is electrically connected to the pad PD by the connection member PST.

  FIG. 5 is a cross-sectional view schematically showing a cross section including the pad PD of the liquid crystal display panel LPN shown in FIG.

  A detailed description of the structure of the array substrate AR on the inner surface facing the counter substrate CT is omitted, but a pad PD is formed in the extended portion ARE. The first optical element OD1 is bonded to the outer surface of the first insulating substrate 20 constituting the array substrate AR. Note that an adhesive for bonding the first optical element OD1 to the first insulating substrate 20 is not shown.

  Although the detailed description of the structure of the counter substrate CT on the inner surface facing the array substrate AR is omitted, a frame-shaped peripheral light shielding layer SHD surrounding the active area ACT is formed around the second insulating substrate 30. . For example, the peripheral light shielding layer SHD is formed of the same material as that of the black matrix BM. The second optical element OD2 is bonded to the outer surface 30B opposite to the inner surface 30A of the second insulating substrate 30 constituting the counter substrate CT. In addition, illustration of the adhesive agent for adhere | attaching 2nd optical element OD2 on the 2nd insulated substrate 30 is abbreviate | omitted.

  The array substrate AR and the counter substrate CT are bonded together by a sealing material SE, and a liquid crystal layer LQ is held between them.

  The conductive layer CDF is disposed over the entire active area ACT on the outer surface ODB of the second optical element OD2. Since such a conductive layer CDF overlaps with the active area ACT for displaying an image, it is formed of a transparent conductive material, for example, an oxide conductive material such as ITO or IZO, or an organic conductive material. Further, such a conductive layer CDF is desirably formed of a material having a surface resistance value of, for example, 700 MΩ / □ or less.

  The connection member PST that connects the conductive layer CDF and the pad PD is formed of, for example, a conductive paste containing conductive particles such as silver, a conductive seal, or the like.

  According to such a configuration, when a discharge occurs on the surface of the cover glass CG, the invading charges are diffused in the plane of the active area ACT in the conductive layer CDF, and the ground potential pad is connected via the connection member PST. It flows into PD. For this reason, it is possible to suppress the intrusion of charges into the liquid crystal display panel LPN.

  In a configuration in which a conductive film such as an electrode is not formed on the counter substrate CT side such as the FFS mode described in this embodiment, undesired charges are likely to enter the liquid crystal display panel LPN. If an undesired voltage is applied to the liquid crystal layer LQ due to the intrusion of electric charges, there is a possibility that it will be visually recognized as display unevenness.

  According to the present embodiment, since the conductive layer CDF is formed on the surface of the second optical element OD2 disposed on the front side of the liquid crystal display panel LPN, the charges that have entered from the outside toward the liquid crystal display panel LPN Even if it is shielded to some extent by the conductive layer CDF, or even if a charge enters the liquid crystal display panel LPN, it is discharged through the conductive layer CDF, so that it is possible to eliminate visible display irregularities in a short time. It becomes.

  Further, according to the present embodiment, the conductive layer CDF has a relatively high resistance. That is, for the FFS mode liquid crystal display panel LPN, it is effective to dispose the conductive layer CDF on the front surface of the liquid crystal display panel LPN in order to secure a shielding function against an external electric field. In addition, in the liquid crystal display panel LPN having a function of performing touch sensing using a change in capacitance in the active area ACT, it is required to maintain sufficient sensitivity. For this reason, it is desirable that the conductive layer CDF covering the active area ACT has a high resistance.

  The inventor conducted the following investigation. That is, a sample in which a conductive layer CDF is formed using a plurality of conductive materials having different surface resistance values is prepared, and discharge is generated on the surface of the cover glass for each sample, and the time until display unevenness is eliminated is measured. did. Note that such measurement was performed respectively when black display in which display unevenness was particularly noticed was performed and when gray display with low gradation was performed.

  It was confirmed that the sample in which the conductive layer CDF was formed using a material having a surface resistance value of 700 MΩ / □ or less can meet the specifications required that the display unevenness elimination time is within 1 second.

  From such knowledge, according to the present embodiment, the surface resistance value of the conductive layer CDF has an upper limit value of 700 MΩ from the viewpoint of ensuring the shielding function against the external electric field and maintaining the sensitivity of the capacitive touch sensing function. / □.

  In the present embodiment, the arrangement position of the conductive layer CDF is not limited to the examples as shown in FIGS.

  FIG. 6 is a plan view schematically showing a configuration of another liquid crystal display panel LPN in the liquid crystal display device of the present embodiment.

  The example shown in FIG. 6 is different from the example shown in FIG. 4 in that the conductive layer CDF is disposed over the entire active area ACT on the counter substrate CT. In addition, about the same structure as the example shown in FIG. 4, the same referential mark is attached | subjected and detailed description is abbreviate | omitted.

  In the illustrated example, the conductive layer CDF is formed over substantially the entire surface of the counter substrate CT. That is, the size of the counter substrate CT in the XY plane is equal to the size of the conductive layer CDF in the XY plane.

  The second optical element OD2 is disposed over the entire active area ACT on the conductive layer CDF. The second optical element OD2 exposes a part of the conductive layer CDF. That is, the size of the second optical element OD2 in the XY plane is smaller than the size of the conductive layer CDF in the XY plane. In this case, the end portion ODE of the second optical element OD2 does not overlap immediately above the end portion CDFE of the conductive layer CDF, but is positioned closer to the active area ACT than the end portion CDFE of the conductive layer CDF. In the illustrated example, the end portion ODE of the quadrangular second optical element OD2 in the XY plane is located on the active area ACT side with respect to the end portion CDFE of the conductive layer CDF in the four directions. That is, the vicinity of the four ends of the end portion CDFE of the conductive layer CDF is exposed from the second optical element OD2.

  In the illustrated example, the end portion CDFE of the conductive layer CDF is positioned immediately above the end portion CTE of the counter substrate CT, and the end portion CTE of the counter substrate CT is higher than the end portion ODE of the second optical element OD2. Located on the side.

  Note that the size of the conductive layer CDF in the XY plane may be smaller than the size of the counter substrate CT in the XY plane. In this case, the end portion CDFE of the conductive layer CDF is located on the active area ACT side with respect to the end portion CTE of the counter substrate CT, and is the end portion of the counter substrate CT with respect to the end portion ODE of the second optical element OD2. Located on the CTE side.

  A portion of the conductive layer CDF exposed from the second optical element OD2 is electrically connected to the pad PD by the connection member PST.

  FIG. 7 is a cross-sectional view schematically showing a cross section including the pad PD of the liquid crystal display panel LPN shown in FIG.

  On the outer surface 30B of the second insulating substrate 30 constituting the counter substrate CT, the conductive layer CDF is formed over the entire active area ACT. The material for forming such a conductive layer CDF is as described with reference to FIG. The second optical element OD2 is bonded to the conductive layer CDF. In addition, illustration of the adhesive agent for adhere | attaching 2nd optical element OD2 on the conductive layer CDF is abbreviate | omitted.

  Outside the active area ACT, the conductive layer CDF is exposed from the second optical element OD2. Thus, the conductive layer CDF exposed from the second optical element OD2 and the pad PD are connected by the connection member PST.

  Also in such a configuration example, the same effect as the above configuration example can be obtained.

  As described above, according to this embodiment, it is possible to provide a liquid crystal display device having both a touch sensing function and a shielding function against an external electric field.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate ACT ... Active area PX ... Pixel PE ... Pixel electrode PSL ... Slit CE ... Common electrode LQ ... Liquid crystal layer OD1 ... First optical element OD2 ... Second optical element PD ... Pad PST ... Connection member CDF ... Conductive layer

Claims (6)

In an active area for displaying an image, a common electrode formed over a plurality of pixels, an insulating film covering the common electrode, and formed on each pixel on the insulating film so as to face the common electrode and form a slit A first substrate comprising a pixel electrode and a capacitance touch sensing wiring;
A second substrate comprising an insulating substrate;
A liquid crystal layer held between the first substrate and the second substrate;
An optical element including a polarizing plate disposed in the active area on the insulating substrate;
A conductive layer disposed in the active area on the optical element;
A ground potential pad formed on the extending portion of the first substrate extending outward from the end portion of the second substrate;
A connection member that electrically connects the conductive layer exposed from the optical element and the pad;
A liquid crystal display device comprising:   The end portion of the conductive layer is located immediately above the end portion of the optical element or closer to the active area side than the end portion of the optical element, and closer to the active area side than the end portion of the second substrate. The liquid crystal display device according to claim 1. In an active area for displaying an image, a common electrode formed over a plurality of pixels, an insulating film covering the common electrode, and formed on each pixel on the insulating film so as to face the common electrode and form a slit A first substrate comprising a pixel electrode and a capacitance touch sensing wiring;
A second substrate comprising: an insulating substrate; and a conductive layer disposed in the active area on an outer surface of the insulating substrate opposite to the inner surface facing the first substrate;
A liquid crystal layer held between the first substrate and the second substrate;
An optical element disposed on the conductive layer in the active area and exposing a part of the conductive layer, including a polarizing plate;
A ground potential pad formed on the extending portion of the first substrate extending outward from the end portion of the second substrate;
A connection member that electrically connects the conductive layer exposed from the optical element and the pad;
A liquid crystal display device comprising:   The end portion of the conductive layer is located immediately above the end portion of the second substrate or closer to the active area than the end portion of the second substrate, and more than the end portion of the optical element. The liquid crystal display device according to claim 3, wherein the liquid crystal display device is located on an end side.   The liquid crystal display device according to claim 1, wherein the conductive layer is formed of a transparent conductive material.   6. The liquid crystal display device according to claim 1, wherein a surface resistance value of the conductive layer is 700 MΩ / □ or less.

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