JP5203032B2 - Pressure contact type semiconductor device - Google Patents

Pressure contact type semiconductor device Download PDF

Info

Publication number
JP5203032B2
JP5203032B2 JP2008117564A JP2008117564A JP5203032B2 JP 5203032 B2 JP5203032 B2 JP 5203032B2 JP 2008117564 A JP2008117564 A JP 2008117564A JP 2008117564 A JP2008117564 A JP 2008117564A JP 5203032 B2 JP5203032 B2 JP 5203032B2
Authority
JP
Japan
Prior art keywords
columnar electrode
electrode
semiconductor elements
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008117564A
Other languages
Japanese (ja)
Other versions
JP2009267246A (en
Inventor
雄二郎 冨永
敬祐 芝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Original Assignee
Honda Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd filed Critical Honda Motor Co Ltd
Priority to JP2008117564A priority Critical patent/JP5203032B2/en
Publication of JP2009267246A publication Critical patent/JP2009267246A/en
Application granted granted Critical
Publication of JP5203032B2 publication Critical patent/JP5203032B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pressure contact semiconductor device, in which, as the whole semiconductor device, a low profile can be achieved, without preparing special another component, such as intermediate terminal board or the like, in the structure of the pressure contact semiconductor device, and the contact between semiconductor elements and a terminal board can be ensured, when a plurality of the semiconductor elements are mounted simultaneously by pressure contact, and the variation in the thickness of the semiconductor elements can be reduced, even if the variation in the thickness of the semiconductor elements is large. <P>SOLUTION: A pressure contact semiconductor device 10 has a structure with a plurality of semiconductor elements 11 and 12, and two terminal boards 22 and 23 which press to get in contact with each of a plurality of the semiconductor elements from both front and rear sides. A plurality of columnar electrode parts 21 are formed in the surfaces of electrodes 11A and 12A of the semiconductor elements, and heat sinks 57 and 59 hold two terminal boards, respectively, while pressing them. A plurality of columnar electrode parts 21 are plastically deformed to get in contact with the terminal board 22. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、圧接型半導体装置に関し、特に、複数の縦型半導体素子を同時に圧接実装する際、各半導体素子とその表裏面の各端子板との接触状態を確実に確保し得る圧接型半導体装置に関する。   The present invention relates to a pressure contact type semiconductor device, and in particular, when a plurality of vertical semiconductor elements are simultaneously pressure contact mounted, a pressure contact type semiconductor device capable of reliably ensuring a contact state between each semiconductor element and each terminal plate on the front and back surfaces thereof. About.

各種電気機器に必要な電力を供給するための電力系電気回路ではパワー半導体モジュールが使用される。パワー半導体モジュールの一例としてIGBTを含む。IGBTはスイッチング素子として使用される半導体装置である。IGBTの等価回路はバイポーラトランジスタとMOSFETを並列接合した電気回路で表現される。IGBT等の半導体素子(「半導体チップ」または「チップ」ともいう)は表裏のチップ面を有する。IGBTがオンしたとき表裏の方向(縦方向)に電流が流れる。この意味でIGBT等は縦型半導体素子と呼ばれる。IGBTは、例えば表面から見ると、同一の半導体構造を有する複数のチップ要素に分離されている。IGBTは複数のチップ要素の集合体として構成されている。IGBTでは、複数のチップ要素のそれぞれがスイッチング素子として機能することにより全体としてオン・オフする。   A power semiconductor module is used in a power system electrical circuit for supplying necessary power to various electrical devices. An IGBT is included as an example of the power semiconductor module. An IGBT is a semiconductor device used as a switching element. An equivalent circuit of the IGBT is expressed by an electric circuit in which a bipolar transistor and a MOSFET are connected in parallel. Semiconductor elements such as IGBTs (also referred to as “semiconductor chips” or “chips”) have front and back chip surfaces. When the IGBT is turned on, a current flows in the front and back direction (vertical direction). In this sense, the IGBT or the like is called a vertical semiconductor element. The IGBT is separated into a plurality of chip elements having the same semiconductor structure when viewed from the surface, for example. The IGBT is configured as an aggregate of a plurality of chip elements. In the IGBT, each of a plurality of chip elements functions as a switching element, thereby turning on and off as a whole.

IGBTやダイオード等の半導体素子を含むパワー半導体モジュールの構造では、一般的に、半導体素子の下部電極(裏面側電極)を下部基板にダイハンダで接合し、半導体素子の上部電極(表面側電極)を樹脂ケース等に設けられた外部端子にワイヤボンディングで接合している。   In the structure of a power semiconductor module including a semiconductor element such as an IGBT or a diode, generally, the lower electrode (back surface side electrode) of the semiconductor element is bonded to the lower substrate by die soldering, and the upper electrode (front surface side electrode) of the semiconductor element is bonded. It is bonded to an external terminal provided on a resin case or the like by wire bonding.

従来のパワー半導体モジュールでは、半導体素子の裏面側のみに放熱を行う冷却構造部を備えるのが一般的であった。この構造によれば、その放熱性能に依存して、半導体素子に流すことができる電流の量が制限される。半導体素子に流れる電流量を増加するためには、半導体素子の両面を冷却する等の更なる放熱性能の向上を図ることが必要である。またパワー半導体モジュールの半導体素子ではその電極部に多数のボンディングワイヤが接続されている。この半導体素子の電極部に結線を行うとき、接合工程に時間がかかる。さらに上記のパワー半導体モジュールを自動車等の車両に搭載する場合、走行中の車両では振動が生じるから、当該振動に対する信頼性を高めることも要求される。   Conventional power semiconductor modules generally include a cooling structure that radiates heat only on the back side of the semiconductor element. According to this structure, the amount of current that can flow through the semiconductor element is limited depending on the heat dissipation performance. In order to increase the amount of current flowing through the semiconductor element, it is necessary to further improve the heat dissipation performance such as cooling both sides of the semiconductor element. In the semiconductor element of the power semiconductor module, a large number of bonding wires are connected to the electrode portions. When connecting to the electrode part of this semiconductor element, it takes time for the joining process. Further, when the above power semiconductor module is mounted on a vehicle such as an automobile, vibration is generated in a traveling vehicle, and thus it is required to improve reliability against the vibration.

パワー半導体モジュールに対する上記の各要望を満たす圧接型の半導体装置が知られている。圧接型の半導体装置は、複数の半導体素子の例えば表裏の両面に端子板を加圧接触させ、面接触による電気的接続を形成する構造を有する。圧接型の半導体装置では、複数の半導体素子を設ける場合、複数の半導体素子の寸法バラツキ等に起因する接触状態の不均一を解消するため、複数の半導体素子(IGBTとダイオード等)の各々と上部端子板との間に導電性および弾性を有する中間端子体を配置した構造が提案されている(特許文献1)。
特許第2991010号公報
2. Description of the Related Art A pressure contact type semiconductor device that satisfies the above requirements for a power semiconductor module is known. A pressure-contact type semiconductor device has a structure in which a terminal plate is brought into pressure contact with, for example, both front and back surfaces of a plurality of semiconductor elements to form electrical connection by surface contact. In a pressure-contact type semiconductor device, when a plurality of semiconductor elements are provided, each of the plurality of semiconductor elements (IGBT, diode, etc.) and an upper portion are removed in order to eliminate non-uniformity of the contact state caused by dimensional variation of the plurality of semiconductor elements. A structure in which an intermediate terminal body having conductivity and elasticity is arranged between the terminal board and the terminal board has been proposed (Patent Document 1).
Japanese Patent No. 2991010

特許文献1に開示された半導体装置の構造によれば、複数の半導体素子(IGBTとダイオード等)の各々と上部端子板との間に、各半導体素子の厚みのバラツキを緩和するための中間端子体が配置される。複数の中間端子体は、半導体素子に対して別部材として用意される。パワー半導体モジュールに対して、半導体素子ごとに中間端子体を設けることは、上記パワー半導体モジュールすなわち圧接型半導体装置の部品点数が増大することになる。また中間端子体を製作することは余分なコストがかさむ。中間端子体は、材質的に弾性による変形特性を有する部材を利用して特定の形状に形成される。加圧して圧接するときに中間端子体の材質の弾性変形を利用することにより、中間端子体を変形させ、各半導体素子の厚みのバラツキを吸収している。このため、特許文献1に開示された圧接型半導体装置の構造によれば、中間端子体が部品として厚くかつ大きくなり、電気抵抗や熱抵抗の特性が低下するおそれがあった。   According to the structure of the semiconductor device disclosed in Patent Document 1, an intermediate terminal for reducing variation in thickness of each semiconductor element between each of a plurality of semiconductor elements (IGBT, diode, etc.) and the upper terminal plate. The body is placed. The plurality of intermediate terminal bodies are prepared as separate members with respect to the semiconductor element. Providing an intermediate terminal for each semiconductor element in the power semiconductor module increases the number of parts of the power semiconductor module, that is, the pressure contact type semiconductor device. Also, the production of the intermediate terminal body adds extra cost. The intermediate terminal body is formed into a specific shape using a member having a deformation characteristic due to elasticity in terms of material. By utilizing the elastic deformation of the material of the intermediate terminal body when pressed and pressed, the intermediate terminal body is deformed and the variation in the thickness of each semiconductor element is absorbed. For this reason, according to the structure of the pressure-contact type semiconductor device disclosed in Patent Document 1, the intermediate terminal body is thick and large as a component, and there is a possibility that the characteristics of electric resistance and thermal resistance are deteriorated.

本発明の目的は、上記の課題に鑑み、圧接型の半導体装置の構造で中間端子板等の特別な別部品を用意することなく、半導体装置全体として薄型を実現し、複数の半導体素子を同時に圧接実装する際に、半導体素子と端子板との接触を確実にし、半導体素子の厚みバラツキが大きい場合でも当該厚みバラツキを緩和することができ、電気抵抗や熱抵抗の特性を良好にできる圧接型半導体装置を提供することにある。   An object of the present invention is to realize a thin semiconductor device as a whole without preparing special separate parts such as an intermediate terminal board in the structure of a pressure-contact type semiconductor device in view of the above-described problems, and simultaneously a plurality of semiconductor elements. When mounting by pressure welding, the contact between the semiconductor element and the terminal plate is ensured, and even when the thickness variation of the semiconductor element is large, the thickness variation can be reduced, and the electrical resistance and thermal resistance characteristics can be improved. It is to provide a semiconductor device.

本発明に係る圧接型半導体装置は、上記の目的を達成するため、次のように構成される。   In order to achieve the above object, a pressure contact type semiconductor device according to the present invention is configured as follows.

第1の圧接型半導体装置(請求項1に対応)は、複数の半導体素子と、複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える構造を有しており、各半導体素子の電極の表面に複数の柱状電極部が形成されており、2つの端子板の各々を加圧状態で保持する放熱板を備え、さらに、複数の前記柱状電極部が塑性変形して端子板に接触する構成であり、複数の柱状電極部のそれぞれは円柱形状を有し、柱状電極部における端子板側の部分は、端子板に近づくにつれて径が小さくなる、ように構成される。 The first pressure-contact type semiconductor device (corresponding to claim 1) has a structure including a plurality of semiconductor elements and two terminal plates that press-contact each of the plurality of semiconductor elements from both the front and back surfaces. A plurality of columnar electrode portions are formed on the surfaces of the electrodes of the respective semiconductor elements, and each of the two terminal plates is provided with a heat radiating plate for holding it in a pressurized state, and the plurality of columnar electrode portions are plastically deformed. Each of the plurality of columnar electrode portions has a cylindrical shape, and the portion on the terminal plate side of the columnar electrode portion is configured such that the diameter decreases as it approaches the terminal plate. .

上記の第1の圧接型半導体装置の構造によれば、厚みが異なる2以上の半導体素子(半導体チップ)をパワー半導体モジュールとして加圧し圧接実装する際に、縦型の各半導体素子の表面等に設けられている電極に予め複数の柱状電極部を形成しておき、これらの柱状電極部の塑性変形を利用して端子板に接触させるようにする。これにより複数の半導体素子の厚みにバラツキがある場合に、このバラツキを緩和し、各半導体素子の電極と端子板との接触を確実にする。また、複数の柱状電極部のそれぞれは円柱形状を有することで、半導体素子と端子板を低荷重で圧接組立てすることが可能となる。更に、柱状電極部における端子板側の部分は、端子板に近づくにつれて径が小さくなることで、半導体素子と端子板を低荷重で圧接組立てすることが可能となり、さらに柱状電極部の倒れも少なくなる。 According to the structure of the first pressure-contact type semiconductor device, when two or more semiconductor elements (semiconductor chips) having different thicknesses are pressed and mounted by pressure as a power semiconductor module, the surface of each vertical semiconductor element or the like is mounted. A plurality of columnar electrode portions are formed in advance on the provided electrodes, and are brought into contact with the terminal board by utilizing plastic deformation of these columnar electrode portions. As a result, when there are variations in the thickness of the plurality of semiconductor elements, the variations are alleviated and the contact between the electrode of each semiconductor element and the terminal plate is ensured. In addition, since each of the plurality of columnar electrode portions has a cylindrical shape, the semiconductor element and the terminal plate can be pressure-welded and assembled with a low load. Furthermore, the diameter of the portion on the terminal plate side in the columnar electrode portion becomes smaller as it approaches the terminal plate, so that the semiconductor element and the terminal plate can be assembled by pressure contact with a low load, and the columnar electrode portion is less likely to collapse. Become.

第2の圧接型半導体装置(請求項2に対応)は、上記の構成において、好ましくは、少なくとも2つの半導体素子はその厚みが異なり、2つの半導体素子の各々の表面に設けられた電極の表面に柱状電極部が形成されており、2つの端子板によって圧接実装される際に、2つの半導体素子の各々の表面側の電極の柱状電極部の塑性変形によって2つの半導体素子の厚みの違いを吸収することを特徴とする。この構成によれば、厚みが異なる2つの半導体素子を圧接実装によって圧接型のパワー半導体モジュールとして構築するとき、電極の表面に複数の柱状電極部を予め形成し、その塑性変形を利用して2つの半導体素子の厚みの相違を吸収し各半導体素子と端子板との接触を確実なものとしている。   In the second press-contact type semiconductor device (corresponding to claim 2), in the above configuration, preferably, at least two semiconductor elements have different thicknesses, and surfaces of electrodes provided on surfaces of the two semiconductor elements, respectively. The columnar electrode portion is formed on the two terminal plates, and when the two terminal plates are pressure-welded, the difference in thickness between the two semiconductor elements is caused by plastic deformation of the columnar electrode portions of the electrodes on the surface side of each of the two semiconductor elements. It is characterized by absorbing. According to this configuration, when two semiconductor elements having different thicknesses are constructed as pressure contact type power semiconductor modules by pressure contact mounting, a plurality of columnar electrode portions are formed in advance on the surface of the electrode, and the plastic deformation is used to make 2 The difference in thickness between the two semiconductor elements is absorbed, and the contact between each semiconductor element and the terminal plate is ensured.

第3の圧接型半導体装置(請求項3に対応)は、上記の構成において、好ましくは、半導体素子の電極の表面に形成される複数の柱状電極部は、電極と同一の金属材料を用いかつ成膜技術に基づき電極の表面に形成されることを特徴とする。この構成によれば、小型の形状を有する半導体素子の電極の表面に高い精度で複数の柱状電極部を作り込むことができ、かつ電極と柱状電極部との結合性も良好になる。 In the third press-contact type semiconductor device (corresponding to claim 3), in the above configuration, preferably, the plurality of columnar electrode portions formed on the surface of the electrode of the semiconductor element use the same metal material as the electrode, and It is formed on the surface of an electrode based on a film forming technique. According to this configuration, a plurality of columnar electrode portions can be formed with high accuracy on the surface of the electrode of the semiconductor element having a small shape, and the connectivity between the electrode and the columnar electrode portion is also improved.

第4の圧接型半導体装置(請求項4に対応)は、上記の構成において、好ましくは、複数の柱状電極部のそれぞれは、隣接する柱状電極部との間で、等間隔で配置されていることを特徴とする。この構成によれば、隣接する柱状電極部同士の間に隙間を設けることにより各柱状電極部の塑性変形による接触を確実なものとする。さらに、これにより、圧接状態における各半導体素子と端子板との間の片当たりの発生を低減し、略均一な接触状態を得ることができ、半導体素子における表裏電極間の電流の流れにおいて偏りを低減することができる。 In the fourth press-contact type semiconductor device (corresponding to claim 4), preferably, each of the plurality of columnar electrode portions is arranged at equal intervals between the adjacent columnar electrode portions. It is characterized by that. According to this structure, the contact by plastic deformation of each columnar electrode part is ensured by providing a gap between adjacent columnar electrode parts. In addition, this reduces the occurrence of contact between each semiconductor element and the terminal plate in the pressure contact state, can obtain a substantially uniform contact state, and biases the current flow between the front and back electrodes in the semiconductor element. Can be reduced.

第5の圧接型半導体装置(請求項5に対応)は、複数の半導体素子と、複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える構造を有しており、各半導体素子の電極の表面に複数の柱状電極部が形成されており、2つの端子板の各々を加圧状態で保持する放熱板を備え、さらに、複数の前記柱状電極部が塑性変形して端子板に接触する構成であり、半導体素子の電極表面における複数の柱状電極部の配置密度は、電極表面の中央部の配置密度よりも電極表面の周辺部の配置密度が高いことを特徴とする。 The fifth pressure-contact type semiconductor device (corresponding to claim 5) has a structure comprising a plurality of semiconductor elements and two terminal plates that press- contact each of the plurality of semiconductor elements from both the front and back surfaces. A plurality of columnar electrode portions are formed on the surfaces of the electrodes of the respective semiconductor elements, and each of the two terminal plates is provided with a heat radiating plate for holding it in a pressurized state, and the plurality of columnar electrode portions are plastically deformed. The arrangement density of the plurality of columnar electrode portions on the electrode surface of the semiconductor element is higher than the arrangement density of the central portion of the electrode surface and the arrangement density of the peripheral portion of the electrode surface To do.

上記の第5の圧接型半導体装置の構造によれば、厚みが異なる2以上の半導体素子(半導体チップ)をパワー半導体モジュールとして加圧し圧接実装する際に、縦型の各半導体素子の表面等に設けられている電極に予め複数の柱状電極部を形成しておき、これらの柱状電極部の塑性変形を利用して端子板に接触させるようにする。これにより複数の半導体素子の厚みにバラツキがある場合に、このバラツキを緩和し、各半導体素子の電極と端子板との接触を確実にする。また、半導体素子の全面で略均一な温度分布が生じ、高温となる半導体素子中央部での性能劣化を低減でき、半導体素子の寿命を向上することができる。According to the structure of the fifth pressure-contact type semiconductor device, when two or more semiconductor elements (semiconductor chips) having different thicknesses are pressed as a power semiconductor module and pressure-welded and mounted on the surface of each vertical semiconductor element, etc. A plurality of columnar electrode portions are formed in advance on the provided electrodes, and are brought into contact with the terminal board by utilizing plastic deformation of these columnar electrode portions. As a result, when there are variations in the thickness of the plurality of semiconductor elements, the variations are alleviated and the contact between the electrode of each semiconductor element and the terminal plate is ensured. In addition, a substantially uniform temperature distribution is generated on the entire surface of the semiconductor element, so that deterioration in performance at the central part of the semiconductor element that becomes high temperature can be reduced, and the life of the semiconductor element can be improved.

の圧接型半導体装置(請求項に対応)は、複数の半導体素子と、複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える構造を有しており、各半導体素子の電極の表面に複数の柱状電極部が形成されており、2つの端子板の各々を加圧状態で保持する放熱板を備え、さらに、複数の前記柱状電極部が塑性変形して端子板に接触する構成であり、半導体素子の電極表面における複数の柱状電極部の横断面の面積の大きさは、電極表面の中央部に位置する柱状電極部の面積よりも電極表面の周辺部に位置する柱状電極部の面積が大きいことを特徴とする。 A sixth pressure-contact type semiconductor device (corresponding to claim 6 ) has a structure including a plurality of semiconductor elements and two terminal plates that press- contact each of the plurality of semiconductor elements from both the front and back surfaces. A plurality of columnar electrode portions are formed on the surfaces of the electrodes of the respective semiconductor elements, and each of the two terminal plates is provided with a heat radiating plate for holding it in a pressurized state, and the plurality of columnar electrode portions are plastically deformed. The area of the cross section of the plurality of columnar electrode portions on the electrode surface of the semiconductor element is larger in the periphery of the electrode surface than the area of the columnar electrode portion located in the central portion of the electrode surface. The columnar electrode part located in the part has a large area.

上記の第6の圧接型半導体装置の構造によれば、厚みが異なる2以上の半導体素子(半導体チップ)をパワー半導体モジュールとして加圧し圧接実装する際に、縦型の各半導体素子の表面等に設けられている電極に予め複数の柱状電極部を形成しておき、これらの柱状電極部の塑性変形を利用して端子板に接触させるようにする。これにより複数の半導体素子の厚みにバラツキがある場合に、このバラツキを緩和し、各半導体素子の電極と端子板との接触を確実にする。また、半導体素子の全面で略均一な温度分布が生じ、高温となる半導体素子中央部での性能劣化を低減でき、半導体素子の寿命を向上することができる。 According to the structure of the sixth pressure-contact type semiconductor device described above, when two or more semiconductor elements (semiconductor chips) having different thicknesses are pressed as a power semiconductor module and pressure-welded and mounted on the surface of each vertical semiconductor element, etc. A plurality of columnar electrode portions are formed in advance on the provided electrodes, and are brought into contact with the terminal board by utilizing plastic deformation of these columnar electrode portions. As a result, when there are variations in the thickness of the plurality of semiconductor elements, the variations are alleviated and the contact between the electrode of each semiconductor element and the terminal plate is ensured. In addition, a substantially uniform temperature distribution is generated on the entire surface of the semiconductor element, so that deterioration in performance at the central part of the semiconductor element that becomes high temperature can be reduced, and the life of the semiconductor element can be improved.

本発明によれば、少なくとも2つの半導体素子を含む圧接型半導体装置において、各半導体素子の電極の表面に複数の柱状電極部を形成し、圧接実装の際には柱状電極部の塑性変形によって厚み調整を行うようにしたため、中間端子板等の中間部材を用意することなく、半導体装置全体として薄型を実現し、複数の半導体素子を同時に圧接実装する際に、半導体素子と端子板との接触を確実にし、半導体素子の厚みバラツキが大きい場合でも当該厚みバラツキを緩和することができる。さらに電極と同じ材質の柱状電極部を利用することにより、電気抵抗や熱抵抗の特性を良好にできる。   According to the present invention, in a pressure contact type semiconductor device including at least two semiconductor elements, a plurality of columnar electrode portions are formed on the surface of the electrode of each semiconductor element, and the thickness is increased by plastic deformation of the columnar electrode portions during pressure contact mounting. Since adjustment is performed, the thickness of the entire semiconductor device is realized without preparing intermediate members such as intermediate terminal plates, and when a plurality of semiconductor elements are simultaneously pressed and mounted, the contact between the semiconductor elements and the terminal plate is achieved. Even if the semiconductor element has a large thickness variation, the thickness variation can be reduced. Furthermore, by using a columnar electrode portion made of the same material as the electrode, the electrical resistance and thermal resistance characteristics can be improved.

以下に、本発明の好適な実施形態(実施例)を添付図面に基づいて説明する。   DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

図1を参照して、本発明に係る圧接型半導体装置の基本的な構造を説明する。図1は、圧接型半導体装置の要部の縦断面図を示しており、かつ特徴的構造が明確になるように概略的にかつ模式的に示している。実際の圧接型半導体装置に比して、図1に示した構造では、寸法や厚みは誇張して示している。   With reference to FIG. 1, a basic structure of a pressure contact type semiconductor device according to the present invention will be described. FIG. 1 is a longitudinal sectional view of a main part of a pressure contact type semiconductor device, and schematically and schematically showing a characteristic structure. Compared to an actual press-contact type semiconductor device, the size and thickness are exaggerated in the structure shown in FIG.

図1に示した圧接型半導体装置10は、上下面側からの加圧に基づいて圧接実装がなされた状態の構造例を示している。   The pressure contact type semiconductor device 10 shown in FIG. 1 shows a structural example in a state where pressure contact mounting is performed based on pressure applied from the upper and lower surfaces.

図1の例では、パワー半導体モジュールを形成する圧接型半導体装置10は、例えば2つの半導体素子11,12を備えている。半導体素子の数は2つに限定されず、2つ以上であってもよい。半導体素子11,12は、パワーデバイスとしての半導体素子であり、例えばIGBTやダイオードである。これらの半導体素子11,12は、パワーデバイスであっていわゆる縦型の構造を有する。半導体素子11,12では、それぞれ、その表面(図1では上面)と裏面(図1では下面)に電極11A,11B,12A,12Bが設けられている。各半導体素子11,12において、電極はその素子構造に応じて任意の数を設けることができる。しかしながら、図1では、説明の便宜上、半導体素子11,12の上下面のそれぞれに1つずつ電極11A,11B,12A,12Bを示している。電極11A,11B,12A,12Bの材料は、導電性を有するアルミニウム(Al)等の金属である。   In the example of FIG. 1, the press contact type semiconductor device 10 forming the power semiconductor module includes, for example, two semiconductor elements 11 and 12. The number of semiconductor elements is not limited to two and may be two or more. The semiconductor elements 11 and 12 are semiconductor elements as power devices, and are, for example, IGBTs or diodes. These semiconductor elements 11 and 12 are power devices and have a so-called vertical structure. In the semiconductor elements 11 and 12, electrodes 11A, 11B, 12A, and 12B are provided on the front surface (upper surface in FIG. 1) and the back surface (lower surface in FIG. 1), respectively. In each of the semiconductor elements 11 and 12, an arbitrary number of electrodes can be provided according to the element structure. However, in FIG. 1, for convenience of explanation, one electrode 11A, 11B, 12A, 12B is shown on each of the upper and lower surfaces of the semiconductor elements 11, 12. The material of the electrodes 11A, 11B, 12A, and 12B is a metal such as aluminum (Al) having conductivity.

上記において、半導体素子11,12の平面形状は矩形である。各半導体素子11,12の矩形の表裏面において望ましい領域に上記の電極11A,11B,12A,12Bが設けられている。電極11A,11B,12A,12Bのそれぞれの平面形状も好ましくは矩形である。   In the above, the planar shape of the semiconductor elements 11 and 12 is a rectangle. The electrodes 11A, 11B, 12A, and 12B are provided in desirable regions on the rectangular front and back surfaces of the semiconductor elements 11 and 12, respectively. The planar shape of each of the electrodes 11A, 11B, 12A, and 12B is also preferably rectangular.

図1に示されるように、2つの半導体素子11,12は、異なる種類の半導体素子であるので、その厚みd1,d2(d1<d2)が異なっている。通常的に、半導体装置10が2以上の複数の半導体素子を備えている場合、それらの半導体素子の厚みは異なる。半導体素子11の厚みd1は例えば0.1〜0.3mmである。他方、半導体素子12の厚みd2は厚みd1よりも大きい寸法を有している。   As shown in FIG. 1, since the two semiconductor elements 11 and 12 are different types of semiconductor elements, their thicknesses d1 and d2 (d1 <d2) are different. Usually, when the semiconductor device 10 includes two or more semiconductor elements, the thicknesses of the semiconductor elements are different. The thickness d1 of the semiconductor element 11 is, for example, 0.1 to 0.3 mm. On the other hand, the thickness d2 of the semiconductor element 12 has a dimension larger than the thickness d1.

2つの半導体素子11,12のそれぞれの電極11A,11B,12A,12Bの厚みの関係に関しては、通常、次の関係を有している。半導体素子11,12の表面側の電極11A,12Aは略同じ厚みを有しており、例えば15〜20μmである。また半導体素子11,12の裏面側の電極11B,12Bも好ましくは略同じ厚みを有している。電極11B,12Bの厚みは、電極11A,12Aの厚みと同じであってもよいし、異なるものであってもよい。   Regarding the relationship between the thicknesses of the respective electrodes 11A, 11B, 12A, 12B of the two semiconductor elements 11, 12, the following relationship is usually provided. The electrodes 11A and 12A on the surface side of the semiconductor elements 11 and 12 have substantially the same thickness, for example, 15 to 20 μm. The electrodes 11B and 12B on the back surface side of the semiconductor elements 11 and 12 preferably have substantially the same thickness. The thickness of the electrodes 11B and 12B may be the same as or different from the thickness of the electrodes 11A and 12A.

図1に示した構造例では、さらに、2つの半導体素子11,12のそれぞれの表面側の電極11A,12Aに対して複数の柱状電極部21が形成されている。図1の図示例では、前述した通り、図1中上側に位置する圧接用端子板22と下側に位置する電極用端子板23とによって圧接実装が完了しており、端子板23は複数の柱状電極部21に押し付けられた状態にある。その結果、複数の柱状電極部21の各々は、端子板22との接触する部分で塑性変形に基づく潰れ部21aが形成されている。圧接前の柱状電極部21の形状は好ましくは円柱体であり、その軸方向の長さ(高さ)は10〜20μmより大きく、例えば15〜25μmである。電極11A,12Aの各々に形成された円柱形状の複数の柱状電極部は、電極と材料と同じ材料を用いて、後述する同じ技術によって形成され、同一の軸方向長さを有している。他方、圧接実装時には、同時に端子板22が電極11A,12Aの各々の柱状電極部21に押し付けられるため、複数の柱状電極部21の上端部分で塑性変形に基づく潰れ部21aが形成されることになる。図1において、寸法d3は例えば略10〜20μmである。その結果、電極11Aの柱状電極部21では、半導体素子11の厚みd1に応じた潰れ部21aが形成される。同様に、電極12Aの柱状電極部21でも、寸法d3に拘束されかつ半導体素子12の厚みd2に応じて潰れ部21aが形成される。半導体素子12の厚みd2が半導体素子11の厚みd1よりも大きい分、電極12Aの柱状電極部21の潰れ部21aの潰れ量は、電極11Aの柱状電極部21の潰れ部21aの潰れ量よりも大きくなる。   In the structure example shown in FIG. 1, a plurality of columnar electrode portions 21 are further formed for the electrodes 11A and 12A on the surface side of the two semiconductor elements 11 and 12, respectively. In the illustrated example of FIG. 1, as described above, the pressure contact mounting is completed by the pressure contact terminal plate 22 located on the upper side and the electrode terminal plate 23 located on the lower side in FIG. It is in a state of being pressed against the columnar electrode portion 21. As a result, each of the plurality of columnar electrode portions 21 is formed with a crushed portion 21 a based on plastic deformation at a portion in contact with the terminal plate 22. The shape of the columnar electrode part 21 before the press contact is preferably a cylindrical body, and its axial length (height) is larger than 10 to 20 μm, for example, 15 to 25 μm. A plurality of columnar columnar electrode portions formed on each of the electrodes 11A and 12A are formed by the same technique described later using the same material as the electrode and have the same axial length. On the other hand, since the terminal plate 22 is simultaneously pressed against the columnar electrode portions 21 of the electrodes 11A and 12A at the time of pressure welding, a crushing portion 21a based on plastic deformation is formed at the upper end portions of the plurality of columnar electrode portions 21. Become. In FIG. 1, the dimension d3 is about 10-20 micrometers, for example. As a result, in the columnar electrode portion 21 of the electrode 11A, a collapsed portion 21a corresponding to the thickness d1 of the semiconductor element 11 is formed. Similarly, also in the columnar electrode portion 21 of the electrode 12A, a crushing portion 21a is formed depending on the thickness d2 of the semiconductor element 12 while being restricted by the dimension d3. Since the thickness d2 of the semiconductor element 12 is larger than the thickness d1 of the semiconductor element 11, the collapse amount of the collapsed portion 21a of the columnar electrode portion 21 of the electrode 12A is larger than the collapse amount of the collapsed portion 21a of the columnar electrode portion 21 of the electrode 11A. growing.

以上のように、半導体素子11,12の裏面側において電極用端子板23を配置し、それに半導体素子11,12の裏面側の電極11B,12Bを接触させると共に、半導体素子11,12の表面側において圧接用端子板22を配置し、半導体素子11,12の表面側の電極11A,12Aの柱状電極部21に接触させて加圧すると、圧接実装がなされ、圧接型半導体装置10が形成される。このとき、半導体素子11,12の厚みが異なる場合にも、表面側の電極11A,12Aに形成された複数の柱状電極部21の接触側先端部が半導体素子11,12の各々の厚み応じてその塑性変形に基づいて適宜な潰れ量で潰れ、端子板22,23間の厚みを均一な一定厚みに保持すると共に、電極11A,12Aと端子板22との接触を確実なものとする。電極11A,12Aの表面に形成される複数の柱状電極部21は、当該電極の材料を同じ材料を用いて、半導体製造プロセスであるスパッタ法あるいはガスデポジッション法等の高い成膜技術に基づく表面処理方法によって形成される。ここでガスデポジッション法は、気化金属をエアロゾル化し、高成膜レートで金属膜を形成する方法である。圧接用端子板22が例えばモリブデン(Mo)やモリブデン銅(CuMo)の場合には、柱状電極部21の高さ(軸方向の長さ)はアルミニウム(Al)を用いて少なくとも略10〜20μm程度の寸法で形成される。実際には、柱状電極部21の高さは、同時に圧接実装する半導体素子11,12の有する厚みの差を十分に吸収・緩和できる値に最適化される。また柱状電極部21の1つ当たりの端子板22との接触部分の面積は、上述した塑性変形を生じさせることを目的とすることを考慮すると、小さければ小さいほど望ましい。しかし実際を考慮すると、半導体素子の有する電流密度や発熱量等の特性に応じて接触部分の面積を最適化することが必要である。 As described above, the electrode terminal plate 23 is arranged on the back surface side of the semiconductor elements 11 and 12, the electrodes 11 B and 12 B on the back surface side of the semiconductor elements 11 and 12 are brought into contact with it, and the surface side of the semiconductor elements 11 and 12 is contacted. The pressure contact terminal plate 22 is disposed and pressed against the columnar electrode portions 21 of the electrodes 11A and 12A on the surface side of the semiconductor elements 11 and 12, so that the pressure contact mounting is performed and the pressure contact type semiconductor device 10 is formed. . At this time, even when the semiconductor elements 11 and 12 have different thicknesses, the contact-side tip portions of the plurality of columnar electrode portions 21 formed on the surface-side electrodes 11A and 12A correspond to the thicknesses of the semiconductor elements 11 and 12, respectively. Then, it is crushed by an appropriate amount of crushing based on the plastic deformation, and the thickness between the terminal plates 22 and 23 is kept uniform and constant, and the contact between the electrodes 11A and 12A and the terminal plate 22 is ensured. The plurality of columnar electrode portions 21 formed on the surfaces of the electrodes 11A and 12A are surfaces based on a high film formation technique such as a sputtering method or a gas deposition method that is a semiconductor manufacturing process using the same material for the electrodes. It is formed by the processing method. Here, the gas deposition method is a method in which vaporized metal is aerosolized to form a metal film at a high film formation rate. When the pressure contact terminal plate 22 is, for example, molybdenum (Mo) or molybdenum copper (CuMo), the height of the columnar electrode portion 21 (the length in the axial direction) is at least about 10 to 20 μm using aluminum (Al). It is formed with the dimension. Actually, the height of the columnar electrode portion 21 is optimized to a value that can sufficiently absorb and mitigate the difference in thickness between the semiconductor elements 11 and 12 that are simultaneously pressed and mounted. In consideration of the purpose of causing the above-described plastic deformation, the area of the contact portion of each columnar electrode portion 21 with the terminal plate 22 is preferably as small as possible. However, considering the actual situation, it is necessary to optimize the area of the contact portion in accordance with the characteristics of the semiconductor element such as current density and calorific value.

一般的に、上述した柱状電極部21の軸方向長さ(高さ)、断面の径、配置密度等は、柱状電極部21が端子板22によって加圧されたときに柱状電極部21で塑性変形が生じ得るように最適される。   In general, the axial length (height), the cross-sectional diameter, the arrangement density, and the like of the columnar electrode unit 21 described above are plastic in the columnar electrode unit 21 when the columnar electrode unit 21 is pressed by the terminal plate 22. Optimized so that deformation can occur.

前述の実施形態の説明では、半導体素子11,12の表面側の電極11A,12Aに複数の柱状電極部21を形成した例を説明したが、同様な構造は、裏面側の電極11B,12Bにも設けることができる。   In the description of the above-described embodiment, the example in which the plurality of columnar electrode portions 21 are formed on the electrodes 11A and 12A on the front surface side of the semiconductor elements 11 and 12 has been described, but a similar structure is provided on the electrodes 11B and 12B on the back surface side. Can also be provided.

図2には、半導体素子11の表面側の電極11Aにおける複数の柱状電極部21の配置の一例を示す。図2において、複数の電極11Aの各々の上に形成された複数の柱状電極部21は、隣接する柱状電極部21同士の間隔がほぼ等しくなるように配置されている。この配置構成によって、各柱状電極部21の塑性変形による接触を確実にする。さらに、柱状電極部21同士の間隔を略等しくなるように配置し、圧接組立てし塑性変形した後の柱状電極部21同士を離間させることで、圧接状態における各半導体素子11,12と端子板22との間の片当たりの発生を低減し、略均一な接触状態を得ることができる。   FIG. 2 shows an example of the arrangement of the plurality of columnar electrode portions 21 in the electrode 11 </ b> A on the surface side of the semiconductor element 11. In FIG. 2, the plurality of columnar electrode portions 21 formed on each of the plurality of electrodes 11 </ b> A are arranged so that the intervals between adjacent columnar electrode portions 21 are substantially equal. By this arrangement configuration, contact by plastic deformation of each columnar electrode portion 21 is ensured. Further, the columnar electrode portions 21 are arranged so that the distances between the columnar electrode portions 21 are substantially equal, and the columnar electrode portions 21 after being pressed and assembled and plastically deformed are separated from each other, whereby the semiconductor elements 11 and 12 and the terminal plate 22 in the pressure contact state are separated. And the occurrence of per-piece contact with each other can be reduced, and a substantially uniform contact state can be obtained.

また半導体素子11,12の電極11A,12Aの表面における複数の柱状電極部21の配置密度は、電極表面の中央部の配置密度よりも電極表面の周辺部の配置密度を高くすることもできる。半導体素子の温度は周辺部より中央部が高温となるが、この配置構成によって、半導体素子の中央部より周辺部の抵抗を高くすることにより、半導体素子11,12の全面で略均一な温度分布が生じさせることができ、さらに高温となる半導体素子中央部での性能劣化を低減できる。   In addition, the arrangement density of the plurality of columnar electrode portions 21 on the surfaces of the electrodes 11A and 12A of the semiconductor elements 11 and 12 can be higher than the arrangement density of the central portion of the electrode surface. The temperature of the semiconductor element is higher in the central part than in the peripheral part. With this arrangement, the resistance of the peripheral part is made higher than that in the central part of the semiconductor element, so that the temperature distribution is substantially uniform over the entire surface of the semiconductor elements 11 and 12. Further, it is possible to reduce the performance deterioration at the central portion of the semiconductor element that becomes high temperature.

さらに、半導体素子11,12の電極11A,12Aの表面における複数の柱状電極部21の横断面(軸に直交する断面)の面積の大きさに関しては、電極表面の中央部に位置する柱状電極部の面積よりも電極表面の周辺部に位置する柱状電極部の面積が大きいことが望ましい。半導体素子の温度は周辺部より中央部が高温となるが、この構成によれば、半導体素子の中央部より周辺部の抵抗を高くすることにより、半導体素子の全面で略均一な温度分布が生じ、高温となる半導体素子中央部での性能劣化を低減できる。   Furthermore, regarding the size of the area of the cross section (cross section orthogonal to the axis) of the plurality of columnar electrode portions 21 on the surfaces of the electrodes 11A and 12A of the semiconductor elements 11 and 12, the columnar electrode portions located at the center of the electrode surface It is desirable that the area of the columnar electrode part located in the peripheral part of the electrode surface is larger than the area of. The temperature of the semiconductor element is higher in the central part than in the peripheral part, but according to this configuration, a substantially uniform temperature distribution is generated over the entire surface of the semiconductor element by increasing the resistance of the peripheral part from the central part of the semiconductor element. Therefore, it is possible to reduce the performance deterioration at the center of the semiconductor element that becomes high temperature.

図3に、上記の柱状電極部21の形状に関して4つの例を示す。図3では柱状電極部21の側面図を示している。図3において、(A)は前述した円柱形状の柱状電極部21を示し、(B)は円錐台形状の柱状電極部21を示し、(C)は先端部が略半球状の形状を有する柱状電極部21を示し、(D)は先端部が円錐台状の形状を有する柱状電極部21を示している。(B)−(D)の柱状電極部21は、上側の端子板に近づくにつれて、径が小さくなる先細りの形状をなしている。これにより、半導体素子と端子板を低荷重で圧接組立することが可能となり、さらに倒れも防止することができる。また、(B)の柱状電極部21は、成膜技術として一般的なスパッタ法での形成が容易であり最も好適な電極形状である。   FIG. 3 shows four examples regarding the shape of the columnar electrode portion 21 described above. FIG. 3 shows a side view of the columnar electrode portion 21. 3A shows the columnar electrode portion 21 having the columnar shape described above, FIG. 3B shows the columnar electrode portion 21 having a truncated cone shape, and FIG. 3C shows a columnar shape having a substantially hemispherical tip portion. The electrode part 21 is shown, (D) has shown the columnar electrode part 21 in which a front-end | tip part has a truncated cone shape. The columnar electrode portions 21 of (B) to (D) have a tapered shape with a diameter that decreases as the upper terminal plate is approached. As a result, the semiconductor element and the terminal plate can be pressure-welded and assembled with a low load, and further falling can be prevented. Further, the columnar electrode portion 21 of (B) is the most suitable electrode shape because it can be easily formed by a general sputtering method as a film forming technique.

次に図4を参照して、本発明に係る圧接型半導体装置の具体的なパワーモジュール構造を説明する。図4では、パワーモジュール構造の要部の縦断面図を示している。   Next, a specific power module structure of the pressure contact type semiconductor device according to the present invention will be described with reference to FIG. In FIG. 4, the longitudinal cross-sectional view of the principal part of a power module structure is shown.

図4において、31は縦型半導体素子であるIGBT、32はIGBT31の上面に形成されたエミッタ電極、33はIGBT31の下面に形成されたコレクタ電極、34はIGBT31の上面に形成されたゲート電極である。エミッタ電極32の表面には複数の柱状電極部35が形成されている。また41は他の縦型半導体素子であるダイオード、42はダイオード41の上面に形成されたアノード電極、43はダイオード41の下面に形成されたカソード電極である。アノード電極42の表面には複数の柱状電極部44が形成されている。   In FIG. 4, 31 is an IGBT which is a vertical semiconductor element, 32 is an emitter electrode formed on the upper surface of the IGBT 31, 33 is a collector electrode formed on the lower surface of the IGBT 31, and 34 is a gate electrode formed on the upper surface of the IGBT 31. is there. A plurality of columnar electrode portions 35 are formed on the surface of the emitter electrode 32. Reference numeral 41 denotes a diode which is another vertical semiconductor element, 42 denotes an anode electrode formed on the upper surface of the diode 41, and 43 denotes a cathode electrode formed on the lower surface of the diode 41. A plurality of columnar electrode portions 44 are formed on the surface of the anode electrode 42.

2つの半導体素子であるIGBT31とダイオード41は、位置決め枠51,52,53によって水平方向の位置決めがなされると共に、それらの上側と下側には外部端子54,55が配置され、これらの板状の外部端子54,55によって圧接実装されている。板状の外部端子54,55は、補助放熱板としての働きも兼ねている。上下の2つの外部端子54,55によってIGBT31とダイオード41は加圧されて挟み込まれ、圧接実装される。上側の外部端子54は複数の柱状電極部35,44のそれぞれに圧接している。以上の構造物に対して、さらに、上側には絶縁基板56を介して放熱板57が設けられ、下側には絶縁基板58を介して放熱板59が設けられる。2つの放熱板57,59の間には、例えば、4本の締結ボルト60とそれらの両端に螺合される締結ナット61とが設けられ、これらの締結手段によって連結される。絶縁基板56,58の間の部分に組み込まれるアセンブリは、外周器62,63でその周囲を囲まれ、保護される。下側の絶縁基板58にはゲート信号外部端子64が設けられる。このゲート信号外部端子64とゲート電極34との間にはゲート信号ワイヤ65が接続されている。ナット61と放熱板59との間に板バネ等の弾柱付与部材を配置し、所定の加圧力を保持するように圧接組立てしても良い。耐振動性が向上する。   The IGBT 31 and the diode 41, which are two semiconductor elements, are positioned in the horizontal direction by positioning frames 51, 52, and 53, and external terminals 54 and 55 are disposed on the upper and lower sides thereof, and these plate-like elements are arranged. The external terminals 54 and 55 are pressed and mounted. The plate-like external terminals 54 and 55 also serve as auxiliary heat sinks. The IGBT 31 and the diode 41 are pressed and sandwiched by the two upper and lower external terminals 54 and 55, and are pressed and mounted. The upper external terminal 54 is in pressure contact with each of the plurality of columnar electrode portions 35 and 44. In addition to the above structure, a heat radiating plate 57 is provided on the upper side via an insulating substrate 56, and a heat radiating plate 59 is provided on the lower side via an insulating substrate 58. Between the two heat sinks 57 and 59, for example, four fastening bolts 60 and fastening nuts 61 screwed to both ends thereof are provided, and are connected by these fastening means. The assembly incorporated in the portion between the insulating substrates 56 and 58 is surrounded and protected by the peripheral units 62 and 63. A gate signal external terminal 64 is provided on the lower insulating substrate 58. A gate signal wire 65 is connected between the gate signal external terminal 64 and the gate electrode 34. A bullet column imparting member such as a leaf spring may be disposed between the nut 61 and the heat radiating plate 59, and pressure contact assembly may be performed so as to maintain a predetermined pressure. Improves vibration resistance.

上記の圧接型半導体装置を含むパワーモジュール構造によれば、エミッタ電極32の複数の柱状電極部35とアノード電極42の複数の柱状電極部44を加圧・圧接する端子板として補助放熱板として機能する外部端子54,55が用いられる。さらに圧接型半導体装置がパワーモジュール構造に組み込まれるとき、当該圧接型半導体装置を含むアセンブリの部分に対して放熱板57,59が付設される。なお上記のパワーモジュール構造において、締結ボルト60等を用いる必要なく、その代わりに箱状の構造物を実現することができればよい。   According to the power module structure including the above-described pressure contact type semiconductor device, the plurality of columnar electrode portions 35 of the emitter electrode 32 and the plurality of columnar electrode portions 44 of the anode electrode 42 function as auxiliary heat sinks as terminal plates that pressurize and press contact. External terminals 54 and 55 are used. Further, when the pressure contact type semiconductor device is incorporated into the power module structure, the heat radiating plates 57 and 59 are attached to the part of the assembly including the pressure contact type semiconductor device. In addition, in said power module structure, it is not necessary to use the fastening bolt 60 grade | etc., And should just implement | achieve a box-shaped structure instead.

次に図5を参照して、本発明に係る圧接型半導体装置の具体的なパワーモジュール構造の他の実施例を説明する。図5は、図4と同様に、パワーモジュール構造の要部の縦断面図を示している。図5において、図4で説明した要素と実質的に同じ要素には同一の符号を付し、その説明を省略する。   Next, another embodiment of a specific power module structure of the pressure contact type semiconductor device according to the present invention will be described with reference to FIG. FIG. 5 shows a longitudinal sectional view of the main part of the power module structure, similar to FIG. In FIG. 5, elements that are substantially the same as those described in FIG. 4 are given the same reference numerals, and descriptions thereof are omitted.

図5に示したパワーモジュール構造では、IGBT31とダイオード41のそれぞれに対して、複数の柱状電極部35,44を圧接する部材として導電性圧接子71,72が設けられている。これらの導電性圧接子71,72の上側には補助放熱として兼用される外部端子73が配置される。この例では、IGBT31の厚みに比較してダイオード41の厚みが小さいものになっているため、これらの半導体素子の厚みのバラツキを吸収するため、厚みの異なる導電性圧接子71,72を設けるようにしている。その他の構造については、図4を参照して説明したパワーモジュール構造と同じである。このパワーモジュール構造によれば、IGBT31とダイオード41のエミッタ電極32とアノード電極42のそれぞれに対して、複数の柱状電極部35,44を圧接する部材として各半導体素子の厚みに応じた厚みを有する専用の導電性圧接子71,72を設けたため、圧接子の材質として最適な材質を選択することができ、さらに柱状電極部との接触を確実にしかつ柱状電極部の塑性変形に基づく圧接を確実に行うことができる。各々の柱状電極部35,44の塑性変形による潰れ量をほぼ等しくすることで、接触抵抗を均等にすることができる。   In the power module structure shown in FIG. 5, conductive pressure contacts 71 and 72 are provided as members for pressing the plurality of columnar electrode portions 35 and 44 against the IGBT 31 and the diode 41, respectively. An external terminal 73 that is also used as auxiliary heat dissipation is disposed on the upper side of these conductive pressers 71 and 72. In this example, since the thickness of the diode 41 is smaller than the thickness of the IGBT 31, the conductive pressure contacts 71 and 72 having different thicknesses are provided in order to absorb variations in the thickness of these semiconductor elements. I have to. The other structure is the same as the power module structure described with reference to FIG. According to the power module structure, the plurality of columnar electrode portions 35 and 44 are pressed against the IGBT 31 and the emitter electrode 32 and the anode electrode 42 of the diode 41, respectively, and have a thickness corresponding to the thickness of each semiconductor element. Since the dedicated conductive pressure contacts 71 and 72 are provided, it is possible to select an optimum material as the pressure contact material, and further ensure the contact with the columnar electrode portion and the pressure contact based on the plastic deformation of the columnar electrode portion. Can be done. Contact resistance can be made equal by making the amount of crushing by plastic deformation of the columnar electrode portions 35 and 44 substantially equal.

以上の実施形態で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、また数値および各構成の組成(材質)等については例示にすぎない。従って本発明は、説明された実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。   The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective components Is just an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

本発明に係る圧接型半導体装置は、自動車等に搭載されるパワー半導体モジュールの組込み構造部分として利用される。   The pressure contact type semiconductor device according to the present invention is used as a built-in structure portion of a power semiconductor module mounted on an automobile or the like.

本発明に係る圧接型半導体装置の基本的な構造を概略的に示し、圧接型半導体装置の要部の縦断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the longitudinal cross-sectional view of the principal part of a press-contact type semiconductor device which shows roughly the basic structure of the press-contact type semiconductor device which concerns on this invention. 本実施形態に係る圧接型半導体素子の表面側の電極における複数の柱状電極部の配置例を示す図である。It is a figure which shows the example of arrangement | positioning of the several columnar electrode part in the electrode of the surface side of the press-contact type semiconductor element which concerns on this embodiment. 本実施形態における柱状電極部の形状に関して4つの例を示す側面図である。It is a side view which shows four examples regarding the shape of the columnar electrode part in this embodiment. 本発明に係る圧接型半導体装置の具体的なパワーモジュール構造の要部の縦断面図である。It is a longitudinal cross-sectional view of the principal part of the concrete power module structure of the press-contact type semiconductor device which concerns on this invention. 本発明に係る圧接型半導体装置の具体的なパワーモジュール構造の他の実施例を示す縦断面図である。It is a longitudinal cross-sectional view which shows the other Example of the concrete power module structure of the press-contact type semiconductor device based on this invention.

符号の説明Explanation of symbols

10 圧接型半導体装置
11,12 半導体素子
11A,11B 電極
12A,12B 電極
21 柱状電極部
21a 潰れ部
22 圧接用端子板
23 電極用端子板
31 IGBT
32 エミッタ電極
35 柱状電極部
41 ダイオード
42 アノード電極
44 柱状電極部
57,59 放熱板
71,72 導電性圧接子
DESCRIPTION OF SYMBOLS 10 Pressure-contact type semiconductor device 11, 12 Semiconductor element 11A, 11B Electrode 12A, 12B Electrode 21 Columnar electrode part 21a Crush part 22 Pressure-contact terminal board 23 Electrode terminal board 31 IGBT
32 Emitter electrode 35 Columnar electrode part 41 Diode 42 Anode electrode 44 Columnar electrode part 57, 59 Heat sink 71, 72 Conductive pressure contactor

Claims (6)

複数の半導体素子と、前記複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える半導体装置であって、
前記半導体素子の電極の表面に複数の柱状電極部が形成され、
前記2つの端子板の各々を加圧状態で保持する放熱板を備え、
複数の前記柱状電極部が塑性変形して前記端子板に接触する構成であり、
複数の前記柱状電極部のそれぞれは円柱形状を有し、前記柱状電極部における前記端子板側の部分は、前記端子板に近づくにつれて径が小さくなる、ことを特徴とする圧接型半導体装置。
A semiconductor device comprising a plurality of semiconductor elements and two terminal plates that press-contact each of the plurality of semiconductor elements from both front and back surfaces,
A plurality of columnar electrode portions are formed on the surface of the electrode of the semiconductor element,
A heat sink for holding each of the two terminal plates in a pressurized state;
A plurality of the columnar electrode portions are plastically deformed and contact the terminal plate ;
Each of the plurality of columnar electrode portions has a cylindrical shape, and a diameter of a portion of the columnar electrode portion on the terminal plate side decreases as the terminal plate is approached .
少なくとも2つの前記半導体素子はその厚みが異なり、前記2つの半導体素子の各々の表面に設けられた電極の表面に前記柱状電極部が形成され、
前記2つの端子板によって圧接実装される際に、前記2つの半導体素子の各々の表面側の前記電極の前記柱状電極部の塑性変形によって前記2つの半導体素子の厚みの違いを吸収することを特徴とする請求項1記載の圧接型半導体装置。
At least two of the semiconductor elements have different thicknesses, and the columnar electrode portions are formed on the surfaces of the electrodes provided on the surfaces of the two semiconductor elements,
When the two terminal plates are mounted by pressure contact, the difference in thickness between the two semiconductor elements is absorbed by plastic deformation of the columnar electrode portion of the electrode on the surface side of each of the two semiconductor elements. The press-contact type semiconductor device according to claim 1.
前記半導体素子の電極の表面に形成される前記複数の柱状電極部は、前記電極と同一の金属材料を用いかつ成膜技術に基づき前記電極の前記表面に形成されることを特徴とする請求項1記載の圧接型半導体装置。 The plurality of columnar electrode portions formed on the surface of the electrode of the semiconductor element are formed on the surface of the electrode using the same metal material as the electrode and based on a film forming technique. 1 Symbol placement of pressure-contact type semiconductor device. 複数の前記柱状電極部のそれぞれは、隣接する前記柱状電極部との間で、等間隔で配置されていることを特徴とする請求項1記載の圧接型半導体装置。 Plurality of each of the columnar electrode portion, between the columnar electrode portion adjacent claim 1 Symbol placement of pressure-contact type semiconductor device characterized in that it is arranged at equal intervals. 複数の半導体素子と、前記複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える半導体装置であって、
前記半導体素子の電極の表面に複数の柱状電極部が形成され、
前記2つの端子板の各々を加圧状態で保持する放熱板を備え、
複数の前記柱状電極部が塑性変形して前記端子板に接触する構成であり、
前記半導体素子の前記電極表面における複数の前記柱状電極部の配置密度は、前記電極表面の中央部の配置密度よりも前記電極表面の周辺部の配置密度が高いことを特徴とする圧接型半導体装置。
A semiconductor device comprising a plurality of semiconductor elements and two terminal plates that press-contact each of the plurality of semiconductor elements from both front and back surfaces,
A plurality of columnar electrode portions are formed on the surface of the electrode of the semiconductor element,
A heat sink for holding each of the two terminal plates in a pressurized state;
A plurality of the columnar electrode portions are plastically deformed and contact the terminal plate;
The arrangement density of the plurality of the columnar electrode part in the electrode surface of the semiconductor element, pressure contact type than the arrangement density of the central portion of the electrode surface you characterized by a high arrangement density of the peripheral portion of the electrode surface Semiconductor device.
複数の半導体素子と、前記複数の半導体素子のそれぞれを表裏の両面から加圧接触する2つの端子板とを備える半導体装置であって、
前記半導体素子の電極の表面に複数の柱状電極部が形成され、
前記2つの端子板の各々を加圧状態で保持する放熱板を備え、
複数の前記柱状電極部が塑性変形して前記端子板に接触する構成であり、
前記半導体素子の前記電極表面における複数の前記柱状電極部の横断面の面積の大きさは、前記電極表面の中央部に位置する前記柱状電極部の前記面積よりも前記電極表面の周辺部に位置する前記柱状電極部の前記面積が大きいことを特徴とする圧接型半導体装置。
A semiconductor device comprising a plurality of semiconductor elements and two terminal plates that press-contact each of the plurality of semiconductor elements from both front and back surfaces,
A plurality of columnar electrode portions are formed on the surface of the electrode of the semiconductor element,
A heat sink for holding each of the two terminal plates in a pressurized state;
A plurality of the columnar electrode portions are plastically deformed and contact the terminal plate;
The size of the cross-sectional area of the plurality of columnar electrode portions on the electrode surface of the semiconductor element is located in the peripheral portion of the electrode surface rather than the area of the columnar electrode portion located in the central portion of the electrode surface pressure contact type you wherein an area of the columnar electrode portion is large for a semiconductor device.
JP2008117564A 2008-04-28 2008-04-28 Pressure contact type semiconductor device Expired - Fee Related JP5203032B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008117564A JP5203032B2 (en) 2008-04-28 2008-04-28 Pressure contact type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008117564A JP5203032B2 (en) 2008-04-28 2008-04-28 Pressure contact type semiconductor device

Publications (2)

Publication Number Publication Date
JP2009267246A JP2009267246A (en) 2009-11-12
JP5203032B2 true JP5203032B2 (en) 2013-06-05

Family

ID=41392686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008117564A Expired - Fee Related JP5203032B2 (en) 2008-04-28 2008-04-28 Pressure contact type semiconductor device

Country Status (1)

Country Link
JP (1) JP5203032B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5664475B2 (en) * 2011-06-22 2015-02-04 株式会社デンソー Semiconductor device
JP5702746B2 (en) * 2012-02-28 2015-04-15 株式会社豊田中央研究所 Inverter parts
US9706643B2 (en) 2014-06-19 2017-07-11 Panasonic Intellectual Property Management Co., Ltd. Electronic device and method for manufacturing the same
JP6804181B2 (en) * 2014-07-22 2020-12-23 日産自動車株式会社 Semiconductor module for electric power and its mounting method
WO2016189953A1 (en) * 2015-05-26 2016-12-01 三菱電機株式会社 Pressure-contact semiconductor device
US9603283B1 (en) * 2015-10-09 2017-03-21 Raytheon Company Electronic module with free-formed self-supported vertical interconnects
JP6108026B1 (en) 2016-12-16 2017-04-05 富士電機株式会社 Pressure contact type semiconductor module
JP6877251B2 (en) * 2017-06-09 2021-05-26 三菱電機株式会社 Semiconductor devices for electric power
CN109786349B (en) * 2018-01-11 2020-11-03 苏州能讯高能半导体有限公司 Exhaust type device and device welding structure
JPWO2022210616A1 (en) * 2021-03-31 2022-10-06

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2974583B2 (en) * 1994-05-31 1999-11-10 株式会社東芝 Semiconductor device and manufacturing method thereof
JPH1197463A (en) * 1997-09-22 1999-04-09 Hitachi Ltd Pressure joint semiconductor device
JP2006005292A (en) * 2004-06-21 2006-01-05 Nissan Motor Co Ltd Pressure contact type semiconductor device

Also Published As

Publication number Publication date
JP2009267246A (en) 2009-11-12

Similar Documents

Publication Publication Date Title
JP5203032B2 (en) Pressure contact type semiconductor device
JP4569473B2 (en) Resin-encapsulated power semiconductor module
US8872332B2 (en) Power module with directly attached thermally conductive structures
US9379083B2 (en) Semiconductor device and method for manufacturing semiconductor device
US9041196B2 (en) Semiconductor module arrangement and method for producing and operating a semiconductor module arrangement
JP4586087B2 (en) Power semiconductor module
US9129931B2 (en) Power semiconductor module and power unit device
JPWO2018179981A1 (en) Semiconductor device
JP2006261168A (en) Semiconductor device
US7473990B2 (en) Semiconductor device featuring electrode terminals forming superior heat-radiation system
US8278747B2 (en) Semiconductor apparatus having a two-side heat radiation structure
CN108496247B (en) Semiconductor device with a plurality of semiconductor chips
JP6150866B2 (en) Power semiconductor device
US10658343B2 (en) Semiconductor module including pressure contact adjustment screws
CN111354710B (en) Semiconductor device and method for manufacturing the same
JP6010942B2 (en) Semiconductor device and manufacturing method thereof
JP2008300627A (en) Semiconductor device
US9532459B2 (en) Electronic module and method of manufacturing the same
JP4535004B2 (en) Double-sided cooling type semiconductor device
US20130043579A1 (en) Power semiconductor arrangement, power semiconductor module with multiple power semiconductor arrangements, and module assembly comprising multiple power semiconductor modules
JP5682511B2 (en) Semiconductor module
CN115579346B (en) Connection structure, packaging structure and manufacturing process of power module
JP4952555B2 (en) Manufacturing method of semiconductor device
JP5817696B2 (en) Semiconductor device
JP2008226920A (en) Connection structure of power module

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101126

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111115

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121016

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130115

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130213

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160222

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees