JP5201143B2 - 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 - Google Patents

読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 Download PDF

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Publication number
JP5201143B2
JP5201143B2 JP2009523029A JP2009523029A JP5201143B2 JP 5201143 B2 JP5201143 B2 JP 5201143B2 JP 2009523029 A JP2009523029 A JP 2009523029A JP 2009523029 A JP2009523029 A JP 2009523029A JP 5201143 B2 JP5201143 B2 JP 5201143B2
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Japan
Prior art keywords
bus
mode
array
lines
bit line
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JP2009523029A
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Japanese (ja)
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JP2009545837A5 (https=
JP2009545837A (ja
Inventor
ロイ・イー ショイアーライン，
ルカ・ジー ファソリ，
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SanDisk 3D LLC
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SanDisk 3D LLC
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Publication date
Priority claimed from US11/461,352 external-priority patent/US7486587B2/en
Priority claimed from US11/461,369 external-priority patent/US7499366B2/en
Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
Publication of JP2009545837A publication Critical patent/JP2009545837A/ja
Publication of JP2009545837A5 publication Critical patent/JP2009545837A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
JP2009523029A 2006-07-31 2007-07-31 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 Active JP5201143B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,352 US7486587B2 (en) 2006-07-31 2006-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array
US11/461,352 2006-07-31
US11/461,369 2006-07-31
US11/461,369 US7499366B2 (en) 2006-07-31 2006-07-31 Method for using dual data-dependent busses for coupling read/write circuits to a memory array
PCT/US2007/074901 WO2008016948A2 (en) 2006-07-31 2007-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array

Publications (3)

Publication Number Publication Date
JP2009545837A JP2009545837A (ja) 2009-12-24
JP2009545837A5 JP2009545837A5 (https=) 2010-09-16
JP5201143B2 true JP5201143B2 (ja) 2013-06-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009523029A Active JP5201143B2 (ja) 2006-07-31 2007-07-31 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置

Country Status (6)

Country Link
EP (1) EP2062263B1 (https=)
JP (1) JP5201143B2 (https=)
KR (1) KR101465557B1 (https=)
AT (1) ATE556411T1 (https=)
TW (1) TWI345790B (https=)
WO (1) WO2008016948A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8279704B2 (en) 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US8958230B2 (en) 2012-08-31 2015-02-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
GB2545264B (en) * 2015-12-11 2020-01-15 Advanced Risc Mach Ltd A storage array
US11763875B2 (en) 2021-05-26 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Second word line combined with Y-MUX signal in high voltage memory program

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229845B1 (en) * 1999-02-25 2001-05-08 Qlogic Corporation Bus driver with data dependent drive strength control logic
US6856572B2 (en) 2000-04-28 2005-02-15 Matrix Semiconductor, Inc. Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device
JP4322645B2 (ja) * 2003-11-28 2009-09-02 株式会社日立製作所 半導体集積回路装置
KR101128246B1 (ko) * 2004-05-03 2012-04-12 유니티 세미컨덕터 코포레이션 비-휘발성 프로그램 가능한 메모리
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
US7054219B1 (en) * 2005-03-31 2006-05-30 Matrix Semiconductor, Inc. Transistor layout configuration for tight-pitched memory array lines

Also Published As

Publication number Publication date
TWI345790B (en) 2011-07-21
EP2062263A4 (en) 2009-08-12
WO2008016948A3 (en) 2009-01-08
TW200823921A (en) 2008-06-01
EP2062263B1 (en) 2012-05-02
EP2062263A2 (en) 2009-05-27
KR101465557B1 (ko) 2014-11-26
KR20090057373A (ko) 2009-06-05
ATE556411T1 (de) 2012-05-15
JP2009545837A (ja) 2009-12-24
WO2008016948A2 (en) 2008-02-07

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