JP5201143B2 - 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 - Google Patents
読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 Download PDFInfo
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- JP5201143B2 JP5201143B2 JP2009523029A JP2009523029A JP5201143B2 JP 5201143 B2 JP5201143 B2 JP 5201143B2 JP 2009523029 A JP2009523029 A JP 2009523029A JP 2009523029 A JP2009523029 A JP 2009523029A JP 5201143 B2 JP5201143 B2 JP 5201143B2
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- Prior art keywords
- bus
- mode
- array
- lines
- bit line
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000008878 coupling Effects 0.000 title claims description 40
- 238000010168 coupling process Methods 0.000 title claims description 40
- 238000005859 coupling reaction Methods 0.000 title claims description 40
- 230000001419 dependent effect Effects 0.000 title claims description 37
- 230000009977 dual effect Effects 0.000 title description 18
- 230000002441 reversible effect Effects 0.000 claims description 79
- 239000000758 substrate Substances 0.000 claims description 17
- 230000004044 response Effects 0.000 claims description 4
- 238000003491 array Methods 0.000 abstract description 8
- 101100421141 Homo sapiens SELENON gene Proteins 0.000 description 40
- 102100023781 Selenoprotein N Human genes 0.000 description 40
- 101000739577 Homo sapiens Selenocysteine-specific elongation factor Proteins 0.000 description 29
- 102100037498 Selenocysteine-specific elongation factor Human genes 0.000 description 29
- 238000010586 diagram Methods 0.000 description 23
- 238000007667 floating Methods 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 230000002829 reductive effect Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000000670 limiting effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003542 behavioural effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000005387 chalcogenide glass Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910000480 nickel oxide Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/461,352 | 2006-07-31 | ||
| US11/461,369 US7499366B2 (en) | 2006-07-31 | 2006-07-31 | Method for using dual data-dependent busses for coupling read/write circuits to a memory array |
| US11/461,369 | 2006-07-31 | ||
| US11/461,352 US7486587B2 (en) | 2006-07-31 | 2006-07-31 | Dual data-dependent busses for coupling read/write circuits to a memory array |
| PCT/US2007/074901 WO2008016948A2 (en) | 2006-07-31 | 2007-07-31 | Dual data-dependent busses for coupling read/write circuits to a memory array |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009545837A JP2009545837A (ja) | 2009-12-24 |
| JP2009545837A5 JP2009545837A5 (enExample) | 2010-09-16 |
| JP5201143B2 true JP5201143B2 (ja) | 2013-06-05 |
Family
ID=38997822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009523029A Active JP5201143B2 (ja) | 2006-07-31 | 2007-07-31 | 読出／書込回路をメモリアレイに結合させるためのデュアルデータ依存型バスのための方法および装置 |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP2062263B1 (enExample) |
| JP (1) | JP5201143B2 (enExample) |
| KR (1) | KR101465557B1 (enExample) |
| AT (1) | ATE556411T1 (enExample) |
| TW (1) | TWI345790B (enExample) |
| WO (1) | WO2008016948A2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8279704B2 (en) * | 2006-07-31 | 2012-10-02 | Sandisk 3D Llc | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same |
| US8958230B2 (en) | 2012-08-31 | 2015-02-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| GB2545264B (en) * | 2015-12-11 | 2020-01-15 | Advanced Risc Mach Ltd | A storage array |
| US11763875B2 (en) | 2021-05-26 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Second word line combined with Y-MUX signal in high voltage memory program |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229845B1 (en) * | 1999-02-25 | 2001-05-08 | Qlogic Corporation | Bus driver with data dependent drive strength control logic |
| US6856572B2 (en) | 2000-04-28 | 2005-02-15 | Matrix Semiconductor, Inc. | Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device |
| JP4322645B2 (ja) * | 2003-11-28 | 2009-09-02 | 株式会社日立製作所 | 半導体集積回路装置 |
| JP2007536680A (ja) * | 2004-05-03 | 2007-12-13 | ユニティ・セミコンダクター・コーポレーション | 不揮発性プログラマブルメモリ |
| US7286439B2 (en) * | 2004-12-30 | 2007-10-23 | Sandisk 3D Llc | Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders |
| US7054219B1 (en) | 2005-03-31 | 2006-05-30 | Matrix Semiconductor, Inc. | Transistor layout configuration for tight-pitched memory array lines |
-
2007
- 2007-07-31 AT AT07840621T patent/ATE556411T1/de active
- 2007-07-31 EP EP07840621A patent/EP2062263B1/en active Active
- 2007-07-31 TW TW096128071A patent/TWI345790B/zh not_active IP Right Cessation
- 2007-07-31 WO PCT/US2007/074901 patent/WO2008016948A2/en not_active Ceased
- 2007-07-31 KR KR1020097004226A patent/KR101465557B1/ko not_active Expired - Fee Related
- 2007-07-31 JP JP2009523029A patent/JP5201143B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR20090057373A (ko) | 2009-06-05 |
| EP2062263A2 (en) | 2009-05-27 |
| TW200823921A (en) | 2008-06-01 |
| KR101465557B1 (ko) | 2014-11-26 |
| TWI345790B (en) | 2011-07-21 |
| WO2008016948A2 (en) | 2008-02-07 |
| WO2008016948A3 (en) | 2009-01-08 |
| JP2009545837A (ja) | 2009-12-24 |
| ATE556411T1 (de) | 2012-05-15 |
| EP2062263B1 (en) | 2012-05-02 |
| EP2062263A4 (en) | 2009-08-12 |
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