KR101465557B1 - 메모리 어레이에 판독/기입 회로를 결합하기 위한 듀얼 데이터 종속 버스 - Google Patents

메모리 어레이에 판독/기입 회로를 결합하기 위한 듀얼 데이터 종속 버스 Download PDF

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Publication number
KR101465557B1
KR101465557B1 KR1020097004226A KR20097004226A KR101465557B1 KR 101465557 B1 KR101465557 B1 KR 101465557B1 KR 1020097004226 A KR1020097004226 A KR 1020097004226A KR 20097004226 A KR20097004226 A KR 20097004226A KR 101465557 B1 KR101465557 B1 KR 101465557B1
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South Korea
Prior art keywords
mode
bit line
bus
voltage
lines
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Expired - Fee Related
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KR1020097004226A
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English (en)
Korean (ko)
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KR20090057373A (ko
Inventor
로이 이. 쉐얼라인
루카 쥐. 파솔리
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쌘디스크 3디 엘엘씨
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Priority claimed from US11/461,369 external-priority patent/US7499366B2/en
Priority claimed from US11/461,352 external-priority patent/US7486587B2/en
Application filed by 쌘디스크 3디 엘엘씨 filed Critical 쌘디스크 3디 엘엘씨
Publication of KR20090057373A publication Critical patent/KR20090057373A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
KR1020097004226A 2006-07-31 2007-07-31 메모리 어레이에 판독/기입 회로를 결합하기 위한 듀얼 데이터 종속 버스 Expired - Fee Related KR101465557B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/461,352 2006-07-31
US11/461,369 US7499366B2 (en) 2006-07-31 2006-07-31 Method for using dual data-dependent busses for coupling read/write circuits to a memory array
US11/461,369 2006-07-31
US11/461,352 US7486587B2 (en) 2006-07-31 2006-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array
PCT/US2007/074901 WO2008016948A2 (en) 2006-07-31 2007-07-31 Dual data-dependent busses for coupling read/write circuits to a memory array

Publications (2)

Publication Number Publication Date
KR20090057373A KR20090057373A (ko) 2009-06-05
KR101465557B1 true KR101465557B1 (ko) 2014-11-26

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KR1020097004226A Expired - Fee Related KR101465557B1 (ko) 2006-07-31 2007-07-31 메모리 어레이에 판독/기입 회로를 결합하기 위한 듀얼 데이터 종속 버스

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EP (1) EP2062263B1 (enExample)
JP (1) JP5201143B2 (enExample)
KR (1) KR101465557B1 (enExample)
AT (1) ATE556411T1 (enExample)
TW (1) TWI345790B (enExample)
WO (1) WO2008016948A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8279704B2 (en) * 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
US8958230B2 (en) 2012-08-31 2015-02-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
GB2545264B (en) * 2015-12-11 2020-01-15 Advanced Risc Mach Ltd A storage array
US11763875B2 (en) 2021-05-26 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Second word line combined with Y-MUX signal in high voltage memory program

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030128581A1 (en) 2000-04-28 2003-07-10 Scheuerlein Roy E. Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229845B1 (en) * 1999-02-25 2001-05-08 Qlogic Corporation Bus driver with data dependent drive strength control logic
JP4322645B2 (ja) * 2003-11-28 2009-09-02 株式会社日立製作所 半導体集積回路装置
JP2007536680A (ja) * 2004-05-03 2007-12-13 ユニティ・セミコンダクター・コーポレーション 不揮発性プログラマブルメモリ
US7286439B2 (en) * 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
US7054219B1 (en) 2005-03-31 2006-05-30 Matrix Semiconductor, Inc. Transistor layout configuration for tight-pitched memory array lines

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030128581A1 (en) 2000-04-28 2003-07-10 Scheuerlein Roy E. Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

Also Published As

Publication number Publication date
KR20090057373A (ko) 2009-06-05
EP2062263A2 (en) 2009-05-27
TW200823921A (en) 2008-06-01
TWI345790B (en) 2011-07-21
WO2008016948A2 (en) 2008-02-07
WO2008016948A3 (en) 2009-01-08
JP2009545837A (ja) 2009-12-24
ATE556411T1 (de) 2012-05-15
EP2062263B1 (en) 2012-05-02
JP5201143B2 (ja) 2013-06-05
EP2062263A4 (en) 2009-08-12

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