JP5195282B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- JP5195282B2 JP5195282B2 JP2008276257A JP2008276257A JP5195282B2 JP 5195282 B2 JP5195282 B2 JP 5195282B2 JP 2008276257 A JP2008276257 A JP 2008276257A JP 2008276257 A JP2008276257 A JP 2008276257A JP 5195282 B2 JP5195282 B2 JP 5195282B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- insulating substrate
- metal base
- semiconductor device
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
この発明は、半導体装置およびその製造方法に関し、特にパワー半導体素子を搭載した樹脂封止型半導体装置とその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a resin-encapsulated semiconductor device on which a power semiconductor element is mounted and a manufacturing method thereof.
インバータ装置、無停電電源装置、工作機械および産業用ロボット等には、半導体装置（汎用モジュール）が多用されている。
この半導体装置としては、絶縁基板上に所定の厚みを有した金属ベース板を固着し、この金属ベース板上に半導体素子を固着し、それを樹脂ケースに収納したパッケージ型タイプのものが開示されている（例えば、特許文献１参照）。
Semiconductor devices (general-purpose modules) are frequently used in inverter devices, uninterruptible power supply devices, machine tools, industrial robots, and the like.
As this semiconductor device, a package type device is disclosed in which a metal base plate having a predetermined thickness is fixed on an insulating substrate, a semiconductor element is fixed on the metal base plate, and the semiconductor element is housed in a resin case. (For example, refer to Patent Document 1).
ここで、半導体素子は、例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やフリーホイールダイオード等である。この金属ベース板上にはＩＧＢＴとダイオードなど複数個の半導体素子が搭載される場合が多い。
また、近年のＩＧＢＴにおいては、高パワー化がさらに進み、動作時において、ＩＧＢＴの主電極側に大電流を流すことが多く、その場合、大電流によって半導体素子から相当量の熱が発生する。
Here, the semiconductor element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a free wheel diode. In many cases, a plurality of semiconductor elements such as IGBTs and diodes are mounted on the metal base plate.
Further, in recent IGBTs, higher power has further progressed, and during operation, a large current is often passed to the main electrode side of the IGBT. In this case, a considerable amount of heat is generated from the semiconductor element due to the large current.
この発熱により、金属ベース板が熱膨張し半導体素子を搭載した絶縁基板が変形して、半導体装置の信頼性を低下させる場合が生じる。
近年、このような課題を解決した上に、さらに優れた動作特性を有し、且つ高い生産性を有する半導体装置が製作されている。例えば、絶縁基板とこの絶縁基板に対向させたプリント基板とがアンダーフィル材の封止により一体になった構造をなし、絶縁基板上には複数の半導体素子が実装され、全体が樹脂ケースでパッケージングされた半導体装置などであり、汎用ＩＧＢＴモジュールとして機能する。
Due to this heat generation, the metal base plate is thermally expanded, and the insulating substrate on which the semiconductor element is mounted is deformed, which may reduce the reliability of the semiconductor device.
In recent years, in addition to solving such problems, a semiconductor device having further excellent operation characteristics and high productivity has been manufactured. For example, a structure in which an insulating substrate and a printed circuit board opposed to the insulating substrate are integrated by sealing with an underfill material, a plurality of semiconductor elements are mounted on the insulating substrate, and the whole is packaged in a resin case. A semiconductor device that functions as a general-purpose IGBT module.
この絶縁基板は、例えば、セラミックス基板などの絶縁板と、絶縁板の裏面（下面）に直接接合により固着された金属箔と、絶縁板の上面に同じく直接接合により固着された複数の金属箔と、さらに同じく直接接合で固着された金属ベース板と、を備え、高い生産性を有している。
また、放熱の問題に対しては、必要な箇所の放熱効果を向上させるとともに、高価な熱伝導性樹脂の使用量を抑えるため、部分的に熱伝導性樹脂が充填された熱伝導性樹脂部と、熱伝導性樹脂部を除く部分に第２樹脂が充填された樹脂封止部と、を備える半導体装置が開示されている（例えば、特許文献２参照）。
The insulating substrate includes, for example, an insulating plate such as a ceramic substrate, a metal foil fixed to the back surface (lower surface) of the insulating plate by direct bonding, and a plurality of metal foils fixed to the upper surface of the insulating plate by direct bonding. And a metal base plate fixed by direct bonding, and has high productivity.
In addition, for the problem of heat dissipation, the heat conductive resin part partially filled with heat conductive resin is used in order to improve the heat dissipation effect at the necessary places and to suppress the use of expensive heat conductive resin. And a resin sealing portion in which a portion excluding the heat conductive resin portion is filled with a second resin is disclosed (for example, see Patent Document 2).
これは、複数の絶縁基板または半導体素子の間を接続する接続線（ボンディングワイヤ）を覆うと共に、絶縁基板と制御基板との間にわたって部分的に熱伝導性樹脂が充填された半導体装置である。
ＤＣＢ（ダイレクト・カッパー・ボンディング）法などにより金属板を固着した絶縁基板（セラミックス基板）は、小型高実装化が可能である点や、製造工程の短縮化を図ることができる点などの利点がある。しかし、半導体素子等からの発熱に伴い、絶縁基板と金属板との熱膨張率の差に起因するバイメタル効果による熱応力が発生し、絶縁基板を反らせたり、クラックを生じさせたり、あるいは金属板剥離を発生させたりする。
This is a semiconductor device that covers connection wires (bonding wires) that connect a plurality of insulating substrates or semiconductor elements and is partially filled with a heat conductive resin between the insulating substrate and the control substrate.
An insulating substrate (ceramic substrate) to which a metal plate is fixed by a DCB (direct copper bonding) method has advantages such as being able to be miniaturized and mounted, and shortening the manufacturing process. is there. However, due to heat generation from semiconductor elements, etc., thermal stress due to the bimetallic effect due to the difference in thermal expansion coefficient between the insulating substrate and the metal plate is generated, causing the insulating substrate to warp, crack, or metal plate It causes peeling.
このような課題に対して、絶縁基板であるセラミックス基板に固着された複数の金属板のうち、少なくとも１つの金属板において、接合面と反対の金属板の表面側の外周部に複数の孔を形成して外周部での熱応力を緩和したセラミックス基板が開示されている（特許文献３参照）
放熱性を向上させるために、絶縁基板の裏側に一枚の金属ベース板を銅箔を介して固着することが行なわれているが、その場合、金属ベース板の肉厚が厚い場合にはバイメタル効果により絶縁基板が反ったり、割れたりする不具合を生じる。
それを防止するために、特許文献３の図１（ｂ）に示されるように、絶縁基板の裏側の金属ベース板を分割することが行なわれている。しかし、つぎのようなデメリットが生じる。半導体素子で発生した熱は、絶縁基板の裏面の金属ベース板を介して冷却体に伝達されるが、裏面の金属ベース板が一枚の金属板であれば熱は絶縁基板内を４５°の角度で広がって行き、熱抵抗は小さくなる。ところが、金属ベース板が分割されていると、この効果が発揮できず、冷却性が悪くなる。
In order to improve heat dissipation, a single metal base plate is fixed to the back side of the insulating substrate via a copper foil. In this case, if the metal base plate is thick, it is bimetallic. Due to the effect, the insulating substrate warps or breaks.
In order to prevent this, the metal base plate on the back side of the insulating substrate is divided as shown in FIG. However, the following disadvantages occur. The heat generated in the semiconductor element is transferred to the cooling body via the metal base plate on the back surface of the insulating substrate. However, if the metal base plate on the back surface is a single metal plate, the heat is 45 ° in the insulating substrate. It spreads at an angle and the thermal resistance becomes smaller. However, if the metal base plate is divided, this effect cannot be exhibited and the cooling performance is deteriorated.
特に、絶縁基板の裏面に複数の金属ベース板が固着された場合においては、裏面の金属ベース板の数が増えるほど、個々の金属ベース板の面積は小さくなる。半導体素子は裏面の金属板と対向する上側の金属ベース板上に実装されているため、裏面の金属ベース板の面積が小さくなれば、十分な放熱性が得られなくなり、大きな電流を流す半導体素子を上側の金属ベース板上に搭載できなくなる。 In particular, when a plurality of metal base plates are fixed to the back surface of the insulating substrate, the area of each metal base plate decreases as the number of metal base plates on the back surface increases. Since the semiconductor element is mounted on the upper metal base plate facing the metal plate on the back side, if the area of the metal base plate on the back side is reduced, sufficient heat dissipation cannot be obtained, and a semiconductor element that flows a large current Cannot be mounted on the upper metal base plate.
一方、放熱性を向上させるために、分割された裏面の複数の金属ベース板間の隙間に樹脂を充填してこの樹脂を利用して放熱性を向上させることが考えられる。
裏面に複数の金属ベース板が固着された絶縁基板を用いた半導体装置においては、裏面の金属ベース板間の隙間の幅の寸法が小さい場合、金型内において、単一の樹脂を用いて樹脂ケース内を一度に封止する際には、流路の狭い前記の裏面に形成された金属ベース板間の隙間に樹脂が充填されにくく、樹脂の未充填箇所又はボイドが発生する。樹脂にボイドが発生すると当然その箇所での放熱性が阻害されてしまう。
On the other hand, in order to improve heat dissipation, it is conceivable to fill a gap between a plurality of metal base plates on the back surface and to improve heat dissipation using this resin.
In a semiconductor device using an insulating substrate with a plurality of metal base plates fixed on the back surface, if the width dimension of the gap between the metal base plates on the back surface is small, a single resin is used in the mold. When the inside of the case is sealed at a time, the resin is difficult to be filled in the gap between the metal base plates formed on the back surface having a narrow flow path, and a resin unfilled portion or a void is generated. If voids are generated in the resin, the heat dissipation at that point is naturally inhibited.
尚、前記の特許文献１〜３においては、高熱伝導樹脂を絶縁基板の裏側の金属ベース板の隙間に充填することは記載されていない。
この発明の目的は、前記の課題を解決して、半導体素子で発生した熱を絶縁基板を介して効果的に放熱できる半導体装置およびその製造方法を提供することにある。
In Patent Documents 1 to 3, there is no description of filling the gap between the metal base plates on the back side of the insulating substrate with the high thermal conductive resin.
An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of effectively dissipating heat generated in a semiconductor element through an insulating substrate and a method for manufacturing the same.
前記の目的を達成するために、絶縁基板の両主面に固着された複数の導電体を備え、前記絶縁基板の第１主面の第１導電体上に半導体素子を固着し、前記半導体素子の周囲を囲むケースの内側を封止材により封止した半導体装置であって、前記絶縁基板の第２主面に固着され、前記第１導電体に対向して配置された複数の第２導電体と、該第２導電体同士の隙間に該第２導電体の側壁と接するように充填された第１樹脂と、前記ケースの内側に充填された前記封止材である第２樹脂とを有し、前記第１樹脂の熱伝導率が前記第２樹脂の熱伝導率より大きい構成とする。 In order to achieve the above object, a plurality of conductors fixed to both main surfaces of an insulating substrate are provided, a semiconductor element is fixed on the first conductor of the first main surface of the insulating substrate, and the semiconductor element A semiconductor device in which the inside of a case surrounding the periphery of the semiconductor device is sealed with a sealing material, and is fixed to the second main surface of the insulating substrate and is arranged to face the first conductor. A first resin filled to contact the side wall of the second conductor in a gap between the second conductor and the second resin that is the sealing material filled inside the case And the thermal conductivity of the first resin is greater than the thermal conductivity of the second resin.
また、前記第１導電体および前記第２導電体が、それぞれ金属箔を介して前記絶縁基板に固着されるとよい。
また、前記第２導電体が、前記第２主面に垂直投影された第１導電体の投影領域の少なくとも全領域に配置されるとよい。
また、前記第２導電体同士の隙間が、１ｍｍ以上であるとよい。
The first conductor and the second conductor may be fixed to the insulating substrate via metal foils.
The second conductor may be disposed in at least the entire region of the projection region of the first conductor that is vertically projected onto the second main surface.
Moreover, the clearance gap between said 2nd conductors is good in it being 1 mm or more.
また、前記ケースが樹脂ケースであり、前記導電体が金属ベース板であり、前記第１樹脂が高熱伝導樹脂であり、前記金属箔が前記絶縁基板に形成された導電パターンであるとよい。
また、絶縁基板の両主面に固着された複数の金属ベース板を備え、前記絶縁基板の第１主面の第１金属ベース板上に半導体素子を固着し、前記半導体素子の周囲を囲むケースの内側を封止材により封止した半導体装置の製造方法であって、前記絶縁基板の第１主面に複数の前記第１金属ベース板と、前記絶縁基板の第２主面に複数の第２金属ベース板とをそれぞれ金属箔を介して固着する工程と、前記絶縁基板下の第２主面に固着された複数の前記第２金属ベース板間の隙間に第２樹脂より熱伝導率が大きい高熱伝導樹脂である第１樹脂を充填した後、半硬化させる工程と、前記ケース内部に前記第２樹脂を充填した後、該第２樹脂と前記の半硬化させた第１樹脂とを同時に硬化させる工程とを有する製造方法とする。
The case may be a resin case, the conductor may be a metal base plate, the first resin may be a high thermal conductive resin, and the metal foil may be a conductive pattern formed on the insulating substrate.
A case in which a plurality of metal base plates fixed to both main surfaces of the insulating substrate are provided, a semiconductor element is fixed on the first metal base plate of the first main surface of the insulating substrate, and the periphery of the semiconductor element is surrounded And a plurality of first metal base plates on a first main surface of the insulating substrate, and a plurality of first metal base plates on a second main surface of the insulating substrate. A step of fixing the two metal base plates to each other via a metal foil, and a gap between the plurality of second metal base plates fixed to the second main surface under the insulating substrate, the thermal conductivity of the second resin. After filling the first resin, which is a large high thermal conductive resin, semi-curing, and after filling the case with the second resin, the second resin and the semi-cured first resin are simultaneously And a step of curing.
また、前記高熱伝導樹脂が金属粒子入り樹脂であり、前記第２樹脂がエポキシ樹脂であるとよい。 The high thermal conductive resin may be a resin containing metal particles, and the second resin may be an epoxy resin.
この発明によれば、絶縁基板の裏面に固着した金属ベース板間の隙間に高熱伝導樹脂を充填することにより、高熱伝導樹脂の占める面積も放熱に寄与することになり、半導体素子から発生した熱をより効率よく放熱することができる。
また、絶縁基板の裏面に固着された複数の金属ベース板間の隙間に予め高熱伝導樹脂を充填し、半硬化させた後、樹脂ケース内部を第２樹脂で充填し、高熱伝導樹脂と第２樹脂を同時に硬化させることより、高熱伝導樹脂の未充填やボイド発生を防ぐことができる。
According to this invention, by filling the gap between the metal base plates fixed to the back surface of the insulating substrate with the high thermal conductive resin, the area occupied by the high thermal conductive resin also contributes to heat dissipation, and the heat generated from the semiconductor element. Can be radiated more efficiently.
Further, after filling the gap between the plurality of metal base plates fixed to the back surface of the insulating substrate with a high heat conductive resin in advance and semi-curing, the inside of the resin case is filled with the second resin, and the high heat conductive resin By simultaneously curing the resins, it is possible to prevent unfilling of the high thermal conductive resin and generation of voids.
実施の形態を以下の実施例で説明する。 Embodiments will be described in the following examples.
図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部断面図、同図（ｂ）は同図（ａ）のＡ部拡大図である。セラミックス基板である絶縁基板１の両面には金属箔２を介して金属ベース板３が固着している。図２は、図１に示す半導体装置の裏面の要部平面図である。これは、絶縁基板１と、この絶縁基板１の裏面に配置される第２金属ベース板３ｂと、第２金属ベース板３ｂ同士の間の隙間１４をこの第２金属ベース板３ｂの側壁に接するように埋められる高熱伝導樹脂４と、樹脂ケース１０内を充填する第２樹脂５および樹脂ケース１０の裏面の平面図である。 FIGS. 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a sectional view of an essential part, and FIG. 1B is an enlarged view of a portion A of FIG. Metal base plates 3 are fixed to both surfaces of an insulating substrate 1 which is a ceramic substrate via a metal foil 2. FIG. 2 is a plan view of the main part of the back surface of the semiconductor device shown in FIG. This is because the insulating substrate 1, the second metal base plate 3b disposed on the back surface of the insulating substrate 1, and the gap 14 between the second metal base plates 3b are in contact with the side walls of the second metal base plate 3b. FIG. 4 is a plan view of the back surface of the high thermal conductive resin 4 filled as described above, the second resin 5 filling the resin case 10 and the resin case 10.
図１に示す半導体装置は、複数の第１、第２金属箔２ａ、２ｂを介して複数の第１、第２金属ベース板３ａ、３ｂが表面および裏面にそれぞれ固着された絶縁基板１と、前記第１金属ベース板３ａ上にはんだ８により固着された複数の半導体素子７とで構成される。
さらに、前記絶縁基板１に対向して平行に配置された制御基板であるプリント基板６と、前記半導体素子７上にはんだ８により固着された複数の金属ピン９と、周囲を囲う樹脂ケース１０と、前記第１金属箔２ａに接続された複数の外部導出端子１１と、複数の第２金属ベース板３ｂ同士の間の隙間１４に充填された高熱伝導樹脂４と、樹脂ケース１０の内部を充填した封止材である第２樹脂５とで構成される。尚、図１および図２に記した符号１２は半導体装置を取り付けるための取り付け用貫通孔である。
The semiconductor device shown in FIG. 1 includes an insulating substrate 1 in which a plurality of first and second metal base plates 3a and 3b are respectively fixed to a front surface and a back surface via a plurality of first and second metal foils 2a and 2b. The plurality of semiconductor elements 7 are fixed to the first metal base plate 3a by solder 8 on the first metal base plate 3a.
Furthermore, a printed circuit board 6 which is a control board disposed in parallel to face the insulating substrate 1, a plurality of metal pins 9 fixed by solder 8 on the semiconductor element 7, and a resin case 10 surrounding the periphery A plurality of external lead-out terminals 11 connected to the first metal foil 2a, a high thermal conductive resin 4 filled in a gap 14 between the plurality of second metal base plates 3b, and the inside of the resin case 10 are filled. It is comprised with the 2nd resin 5 which is a sealing material. Reference numeral 12 shown in FIGS. 1 and 2 is an attachment through hole for attaching the semiconductor device.
本発明の半導体装置においては、第２金属ベース板３ｂは第１金属ベース板３ａと同じ大きさで、第１金属ベース板３ａの直下に配置されている。この第２金属ベース板３ｂを第１金属ベース板３ａより大きくすれば熱抵抗が小さくなり放熱性が向上するのでよい。
しかし、第２金属ベース板３ｂが大きすぎるとバイメタル効果で絶縁基板１が曲がり、割れやクラックが発生して好ましくない。さらに、第２金属ベース板３ｂ同士の隙間１４が狭くなりすぎて隙間１４を充填する高熱伝導樹脂４内にボイドが発生するため好ましくない。
In the semiconductor device of the present invention, the second metal base plate 3b is the same size as the first metal base plate 3a and is disposed immediately below the first metal base plate 3a. If the second metal base plate 3b is made larger than the first metal base plate 3a, the thermal resistance may be reduced and the heat dissipation may be improved.
However, if the second metal base plate 3b is too large, the insulating substrate 1 is bent due to the bimetal effect, and cracks or cracks are generated, which is not preferable. Furthermore, since the gap 14 between the second metal base plates 3b becomes too narrow and voids are generated in the high thermal conductive resin 4 filling the gap 14, it is not preferable.
そのため、隙間１４の大きさ（第２金属ベース板３ｂ同士の間の間隔）は、その間隔を１ｍｍ以上とするとよい。それは、高熱伝導樹脂４を一旦半硬化させ、その後硬化させた場合も間隔が１ｍｍ未満になるとボイドの発生が見られるからである。
高熱伝導樹脂４としては、放熱性を良くするために、例えば、第２樹脂５として用いるエポキシ樹脂（熱伝導率＝０．７Ｗ／ｍ・Ｋ程度）よりも大きな熱伝導率の樹脂を用いる。この高熱伝導樹脂４としては、例えば金属粒子が混入された樹脂（フィラー入り樹脂）などがあり、第２樹脂５に比べて絶縁性が低くコスト高である。そのため第２樹脂５を高熱伝導樹脂４に換えることは絶縁性とコスト性の点で好ましくない。
Therefore, the size of the gap 14 (interval between the second metal base plates 3b) is preferably 1 mm or more. This is because even when the high thermal conductive resin 4 is once semi-cured and then cured, voids are observed when the interval is less than 1 mm.
As the high thermal conductive resin 4, for example, a resin having a thermal conductivity larger than that of the epoxy resin (thermal conductivity = about 0.7 W / m · K) used as the second resin 5 is used in order to improve heat dissipation. As the high thermal conductive resin 4, for example, there is a resin mixed with metal particles (filler-containing resin) or the like, which has a lower insulating property and higher cost than the second resin 5. Therefore, replacing the second resin 5 with the high thermal conductive resin 4 is not preferable in terms of insulation and cost.
前記のことから本発明のポイントはつぎのようになる。高熱伝導樹脂４の熱伝導率を第２樹脂５の熱伝導率より大きくする。また、第２金属ベース板３ｂの大きさを第１金属ベース板３ａの大きさ以上にして、第２金属ベース板３ｂを第１金属ベース板３ａの直下に配置するようにする。つまり、第１金属ベース板３ａの絶縁基板１の裏面への垂直投影領域に第２金属ベース板３ｂを配置し、第２金属ベース板３ｂの大きさをその投影領域（第１金属ベース板３ａの大きさ）以上の大きさにする。また、第２金属ベース板３ｂ同士の隙間１４はボイド発生を防止するために１ｍｍ以上とする。 From the above, the points of the present invention are as follows. The thermal conductivity of the high thermal conductive resin 4 is made larger than the thermal conductivity of the second resin 5. Further, the size of the second metal base plate 3b is set to be equal to or larger than the size of the first metal base plate 3a, and the second metal base plate 3b is disposed immediately below the first metal base plate 3a. That is, the second metal base plate 3b is disposed in a vertical projection region on the back surface of the insulating substrate 1 of the first metal base plate 3a, and the size of the second metal base plate 3b is set to the projection region (first metal base plate 3a). )) Or larger. Further, the gap 14 between the second metal base plates 3b is set to 1 mm or more in order to prevent generation of voids.
図３〜図６は、図１に示す半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。ここで半導体素子としてはＩＧＢＴを例に挙げる。
図３において、絶縁基板１の表側に第１金属箔２ａを固着し、裏側に第２金属箔２ｂを固着し、第１金属箔２ａには第１金属ベース板３ａと外部導出端子１１を固着し、第２金属箔２ｂには第２金属ベース板３ｂを固着する。第１金属ベース板３ａにはんだ８を介して半導体素子７を固着し、半導体素子７の図示しないゲート電極とエミッタ電極に金属ピン９をはんだ８を介して固着する。絶縁基板１と平行に半導体素子７から離して制御基板であるプリント基板６を金属ピン９と外部導出端子１１に固着する。外部導出端子１１はコレクタ端子となる。
3 to 6 are cross-sectional views of a manufacturing process of the semiconductor device shown in FIG. Here, an example of the semiconductor element is an IGBT.
In FIG. 3, the first metal foil 2a is fixed to the front side of the insulating substrate 1, the second metal foil 2b is fixed to the back side, and the first metal base plate 3a and the external lead terminal 11 are fixed to the first metal foil 2a. The second metal base plate 3b is fixed to the second metal foil 2b. The semiconductor element 7 is fixed to the first metal base plate 3 a via the solder 8, and the metal pin 9 is fixed to the gate electrode and the emitter electrode (not shown) of the semiconductor element 7 via the solder 8. A printed circuit board 6 that is a control board is fixed to the metal pins 9 and the external lead-out terminals 11 apart from the semiconductor element 7 in parallel with the insulating substrate 1. The external lead-out terminal 11 becomes a collector terminal.
つぎに、図４において、絶縁基板１の裏側を上に向けて、高熱伝導樹脂４を充填する充填領域（６個の第２金属ベース板３ｂを一括して囲んだ領域）の周囲を図示しないシリコーンパテなどで囲う。これは高熱伝導樹脂４が充填領域の外に漏れでないようにするためである。真空装置内で高熱伝導樹脂４を真空脱泡し、絶縁基板１の裏面の充填領域に脱泡した高熱伝導樹脂４を充填し、真空装置内を大気圧に開放し、硬化炉内にて高熱伝導樹脂４を半硬化させる。この段階では高熱伝導樹脂４の厚さは、部分的に第２金属ベース板３ｂの厚さよりも厚くなり第２金属ベース板上の一部を覆っている。続いて、硬化炉から取り出しシリコーンパテを外し、絶縁基板１の裏面の金属ベース板３ｂと半硬化した高熱伝導樹脂４の面が平坦となるように裏面の研磨を行う。この研磨は、第２金属ベース板３ｂが完全に露出するまで行なわれる。 Next, in FIG. 4, the periphery of the filling region (the region in which the six second metal base plates 3 b are collectively enclosed) filled with the high thermal conductive resin 4 with the back side of the insulating substrate 1 facing upward is not illustrated. Surround with silicone putty. This is to prevent the high thermal conductive resin 4 from leaking out of the filling region. The high thermal conductive resin 4 is degassed in a vacuum apparatus, the degassed high thermal conductive resin 4 is filled in the filling area on the back surface of the insulating substrate 1, the vacuum apparatus is opened to atmospheric pressure, and high heat is generated in a curing furnace. The conductive resin 4 is semi-cured. At this stage, the thickness of the high thermal conductive resin 4 is partially thicker than the thickness of the second metal base plate 3b and covers a part of the second metal base plate. Subsequently, the silicone putty is removed from the curing furnace, and the back surface is polished so that the metal base plate 3b on the back surface of the insulating substrate 1 and the surface of the semi-cured high thermal conductive resin 4 become flat. This polishing is performed until the second metal base plate 3b is completely exposed.
つぎに、図５において、第２金属ベース板３ｂと高熱伝導樹脂４を平坦化したものを第２樹脂封止用の金型１３に設置し、上部から樹脂ケース１０を被せる。
つぎに、図６において、樹脂ケース１０で覆われた金型１３と充填前の第２樹脂５を真空装置内に入れ、第２樹脂５を真空脱泡する。なお、樹脂温度と金型温度は、第２樹脂５が流動性を保持できる時間に関係するため、使用する第２樹脂５によって温度設定値を変更する必要がある。例えば第２樹脂５として、２液型熱硬化性樹脂であるエポキシ樹脂を使用する場合、金型温度、樹脂温度を８０℃に設定すると、第２樹脂５は、封止に必要な流動性を主剤と硬化剤の混合開始から約２０分間保持することができる。
Next, in FIG. 5, a flattened second metal base plate 3b and high thermal conductive resin 4 are placed in a second resin sealing mold 13 and covered with a resin case 10 from above.
Next, in FIG. 6, the mold 13 covered with the resin case 10 and the second resin 5 before filling are placed in a vacuum apparatus, and the second resin 5 is vacuum degassed. In addition, since the resin temperature and the mold temperature are related to the time during which the second resin 5 can maintain fluidity, it is necessary to change the temperature set value depending on the second resin 5 to be used. For example, when an epoxy resin that is a two-component thermosetting resin is used as the second resin 5, if the mold temperature and the resin temperature are set to 80 ° C., the second resin 5 has the fluidity necessary for sealing. It can be held for about 20 minutes from the start of mixing of the main agent and curing agent.
第２樹脂５を真空脱泡したのち、真空中にて前記樹脂ケース１０に設けられた図示しない穴より樹脂ケース１０内部に第２樹脂５を充填する。充填後、真空装置内を大気圧に開放し、硬化炉内にて高熱伝導樹脂４と第２樹脂５を同時に硬化させる。上述のエポキシ樹脂の場合、１００℃で１時間硬化させた後、１８０℃で２時間でさらに硬化させる。このとき高熱伝導樹脂４も同時に硬化させる。 After degassing the second resin 5, the second resin 5 is filled into the resin case 10 through a hole (not shown) provided in the resin case 10 in a vacuum. After filling, the inside of the vacuum apparatus is opened to atmospheric pressure, and the high thermal conductive resin 4 and the second resin 5 are simultaneously cured in a curing furnace. In the case of the above-mentioned epoxy resin, after being cured at 100 ° C. for 1 hour, it is further cured at 180 ° C. for 2 hours. At this time, the high thermal conductive resin 4 is also cured simultaneously.
本発明の半導体装置によれば、前記絶縁基板１の裏面に固着された複数の第２金属ベース板３ｂ間の隙間１４に、高熱伝導樹脂４が充填されている。これによって、前記第２金属ベース板３ｂに加え、第２金属ベース板３ｂに接する前記高熱伝導樹脂４も半導体素子より生じた熱の放熱に寄与することになり、より効率よく放熱することができる。
また、本発明の樹脂封止方法によれば、樹脂を封止する際、前記絶縁基板１の裏面に固着された複数の第２金属ベース板３ｂ間の隙間１４において、予め高熱伝導樹脂４を充填し、半硬化させた後、樹脂ケース１０内の前記高熱伝導樹脂４が充填されていない箇所に第２樹脂５を充填し、硬化させる。このとき、高熱伝導樹脂４も同時に硬化させる。これによって、金型１３内において、半導体装置全体を単一の第２樹脂５で樹脂封止する場合に生じ易い樹脂の未充填やボイドの発生を防ぐことができる。
According to the semiconductor device of the present invention, the high thermal conductive resin 4 is filled in the gaps 14 between the plurality of second metal base plates 3 b fixed to the back surface of the insulating substrate 1. As a result, in addition to the second metal base plate 3b, the high thermal conductive resin 4 in contact with the second metal base plate 3b also contributes to the heat dissipation of the heat generated from the semiconductor element, and can be radiated more efficiently. .
Further, according to the resin sealing method of the present invention, when the resin is sealed, the high thermal conductive resin 4 is preliminarily disposed in the gaps 14 between the plurality of second metal base plates 3b fixed to the back surface of the insulating substrate 1. After the filling and semi-curing, the second resin 5 is filled in the portion of the resin case 10 where the high thermal conductive resin 4 is not filled and cured. At this time, the high thermal conductive resin 4 is also cured simultaneously. Thereby, in the mold 13, it is possible to prevent unfilling of resin and generation of voids that are likely to occur when the entire semiconductor device is sealed with the single second resin 5.
１ 絶縁基板
２ 金属箔
２ａ 第１金属箔
２ｂ 第２金属箔
３ 金属ベース板
３ａ 第１金属ベース板
３ｂ 第２金属ベース板
４ 高熱伝導樹脂
５ 第２樹脂
６ プリント基板
７ 半導体素子
８ はんだ
９ 金属ピン
１０ 樹脂ケース
１１ 外部導出端子
１２ 取り付け用貫通孔
１３ 樹脂封止用金型
１４ 隙間
DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 2 Metal foil 2a 1st metal foil 2b 2nd metal foil 3 Metal base board 3a 1st metal base board 3b 2nd metal base board 4 High heat conductive resin 5 2nd resin 6 Printed circuit board 7 Semiconductor element 8 Solder 9 Metal Pin 10 Resin case 11 External lead-out terminal 12 Through hole for mounting 13 Mold for resin sealing 14 Gap
Claims (9)
前記絶縁基板の第２主面に固着され、前記第１導電体に対向して配置された複数の第２導電体と、該第２導電体同士の隙間に該第２導電体の側壁と接するように充填された第１樹脂と、前記ケースの内側に充填された前記封止材である第２樹脂とを有し、前記第１樹脂の熱伝導率が前記第２樹脂の熱伝導率より大きいことを特徴とする半導体装置。 A plurality of conductors fixed to both main surfaces of the insulating substrate; a semiconductor element is fixed on the first conductor of the first main surface of the insulating substrate; and the inside of the case surrounding the semiconductor element is sealed. A semiconductor device sealed with a stop material,
A plurality of second conductors fixed to the second main surface of the insulating substrate and arranged to face the first conductor, and a side wall of the second conductor in contact with a gap between the second conductors The first resin filled in this way and the second resin that is the sealing material filled inside the case, and the thermal conductivity of the first resin is higher than the thermal conductivity of the second resin. A semiconductor device characterized by being large.
前記絶縁基板の第１主面に複数の前記第１金属ベース板と、前記絶縁基板の第２主面に複数の第２金属ベース板とをそれぞれ金属箔を介して固着する工程と、
前記絶縁基板下の第２主面に固着された複数の前記第２金属ベース板間の隙間に第２樹脂より熱伝導率が大きい高熱伝導樹脂である第１樹脂を充填した後、半硬化させる工程と、
前記ケース内部に前記第２樹脂を充填した後、該第２樹脂と前記の半硬化させた第１樹脂とを同時に硬化させる工程と、を有することを特徴とする半導体装置の製造方法。 A plurality of metal base plates fixed to both main surfaces of the insulating substrate, a semiconductor element fixed on the first metal base plate of the first main surface of the insulating substrate, and an inner side of the case surrounding the semiconductor element A method for manufacturing a semiconductor device in which is sealed with a sealing material,
Fixing the plurality of first metal base plates to the first main surface of the insulating substrate and the plurality of second metal base plates to the second main surface of the insulating substrate via metal foils, respectively;
The gap between the plurality of second metal base plates fixed to the second main surface under the insulating substrate is filled with the first resin, which is a high thermal conductive resin having a higher thermal conductivity than the second resin, and then semi-cured. Process,
And a step of simultaneously curing the second resin and the semi-cured first resin after filling the case with the second resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008276257A JP5195282B2 (en) | 2008-10-28 | 2008-10-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008276257A JP5195282B2 (en) | 2008-10-28 | 2008-10-28 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010108955A JP2010108955A (en) | 2010-05-13 |
| JP5195282B2 true JP5195282B2 (en) | 2013-05-08 |
Family
ID=42298139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008276257A Expired - Fee Related JP5195282B2 (en) | 2008-10-28 | 2008-10-28 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5195282B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5644440B2 (en) * | 2010-12-03 | 2014-12-24 | 富士電機株式会社 | Power semiconductor module |
| JP5807348B2 (en) * | 2011-03-10 | 2015-11-10 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP5994254B2 (en) * | 2012-01-11 | 2016-09-21 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP5928485B2 (en) * | 2012-02-09 | 2016-06-15 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3148008B2 (en) * | 1992-07-31 | 2001-03-19 | 富士通株式会社 | Method of connecting substrate and chip using conductive adhesive |
| JP2973792B2 (en) * | 1993-09-21 | 1999-11-08 | 富士電機株式会社 | Resin-sealed semiconductor device |
| JP3333409B2 (en) * | 1996-11-26 | 2002-10-15 | 株式会社日立製作所 | Semiconductor module |
| JP3361276B2 (en) * | 1998-07-08 | 2003-01-07 | 株式会社三社電機製作所 | Power semiconductor module |
| JP2000340721A (en) * | 1999-05-26 | 2000-12-08 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit |
| JP2001118987A (en) * | 1999-10-20 | 2001-04-27 | Nissan Motor Co Ltd | Power semiconductor module |
| JP2002043510A (en) * | 2000-07-24 | 2002-02-08 | Mitsubishi Electric Corp | Semiconductor power module and its manufacturing method |
| JP3669980B2 (en) * | 2002-09-04 | 2005-07-13 | 電気化学工業株式会社 | MODULE STRUCTURE MANUFACTURING METHOD, CIRCUIT BOARD FIXING METHOD, AND CIRCUIT BOARD |
| JP2005142323A (en) * | 2003-11-06 | 2005-06-02 | Mitsubishi Electric Corp | Semiconductor module |
| JP5028085B2 (en) * | 2006-12-27 | 2012-09-19 | アイシン・エィ・ダブリュ株式会社 | Electronic circuit device and manufacturing method thereof |
-
2008
- 2008-10-28 JP JP2008276257A patent/JP5195282B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010108955A (en) | 2010-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5807348B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9613888B2 (en) | Semiconductor device and semiconductor module | |
| US7902653B2 (en) | Semiconductor module | |
| WO2017175612A1 (en) | Power module, power semiconductor device, and power module manufacturing method | |
| US9117795B2 (en) | Semiconductor device | |
| US20100134979A1 (en) | Power semiconductor apparatus | |
| JP2010251408A (en) | Semiconductor device and method of manufacturing the same, and electronic device | |
| KR101321277B1 (en) | Power module package and method for manufacturing the same | |
| US10163752B2 (en) | Semiconductor device | |
| JP6350364B2 (en) | Connection structure | |
| CN106847781A (en) | Power module package and its manufacture method | |
| JP2016181536A (en) | Power semiconductor device | |
| JP5195282B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20150108685A (en) | Power Semi-Conductor package and Method of Manufacturing for the same | |
| JP6360035B2 (en) | Semiconductor device | |
| JP6314433B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4647673B2 (en) | Heat dissipation type multi-hole semiconductor package | |
| JP6472568B2 (en) | Manufacturing method of semiconductor device | |
| EP2608257B1 (en) | Semiconductor device and method for manufacturing same | |
| JP6769556B2 (en) | Semiconductor devices and semiconductor modules | |
| KR101239117B1 (en) | Power semiconductor package and method for fabricating the same | |
| JP2004039700A (en) | Semiconductor power module | |
| JP2020072095A (en) | Power unit, method of manufacturing the same, electric device having power unit, and heat sink | |
| JP2015076488A (en) | Semiconductor device and manufacturing method of the same | |
| US20240088064A1 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20110422 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110812 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120927 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121002 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121203 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130108 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130121 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160215 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5195282 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |