JP5155221B2 - Memory control device - Google Patents

Description

  The present invention relates to a memory control device. In particular, the present invention relates to a memory control device that controls the timing of a refresh operation of a DRAM that requires refresh.

In recent years, there has been an increasing demand for processing an enormous amount of data such as images as needed. Therefore, it is necessary to transfer data to be processed to DRAM at high speed.
Here, the DRAM needs to perform a refresh operation periodically. If the data transfer and the refresh timing overlap, the refresh is prioritized and the data transfer is suspended.
However, such suspension of data transfer lowers the data transfer efficiency, and as a result, lowers the processing speed of the entire processing system. Therefore, there is an increasing need to control the memory operation so as to reduce the overlap between the refresh operation and the data transfer and improve the data transfer efficiency to the DRAM.

Patent Document 1 discloses a memory control device that improves data transfer efficiency to DRAM.
FIG. 9 is a diagram showing the configuration of the memory control device disclosed in Patent Document 1. In FIG.
A real-time processing unit (hereinafter referred to as “RPU”) 5 that processes an image includes a single pixel processing unit 51, a pixel interpolation unit 52, and an image compression unit 53 as image processing function units.
The single pixel processing unit 51 processes an image in units of pixels. For example, shading correction is performed. The pixel interpolation unit 52 performs color interpolation processing for interpolating the value of the color component that is missing from each pixel of the image based on the information of the surrounding pixels. The image compression unit 53 compresses the image to reduce the amount of image data.

  The RPU 5 is connected to the bus 20 via a memory interface unit (hereinafter “MIU”) 6. A DRAM 4 is also connected to the bus 20. Then, image data is transferred between the RPU 5 and the DRAM 4 via the MIU 6 serving as a memory control device.

The MIU 6 includes an arbitrator 61, a control signal transmission unit 62, and a refresh control unit 63.
Here, the RPU 5 outputs a data transfer request to the DRAM 4 to the arbitrator 61.
In addition, the refresh control unit 63 sends a refresh request signal for requesting refresh of the DRAM 4 to the arbitrator 61. The arbitrator 61 arbitrates between the data transfer request from the RPU 5 related to the DRAM 4 and the refresh request transmitted from the refresh control unit 63.
The arbitration will be described later with reference to the flowchart of FIG.

  The control signal transmission unit 62 generates a control signal (RAS, CAS, WE, etc.) for the DRAM 4 and transmits it to the control unit 41 of the DRAM 4. The control unit 41 controls the operation of the DRAM 4 based on the control signal input in this way.

The refresh control unit 63 includes a pulse generation unit 64 that generates a reference pulse at a predetermined generation cycle, and transmits two types of refresh request signals using the reference pulse as a reference signal.
The first refresh request signal (first request signal) functions as a request signal having a relatively low degree of urgency.
The second refresh request signal (second request signal) functions as a request signal having a relatively high degree of urgency.
In other words, the first request signal indicates the timing at which the refresh may be performed, and the second request signal indicates the timing at which the refresh must be performed.
The second request signal is not necessarily transmitted, and is transmitted only when refresh is not executed based on the first request signal.

FIG. 10 is a timing chart showing the relationship between the generation timing of the reference pulse and the transmission timing of two types of refresh request signals.
The generation timing of the reference pulse corresponds to the refresh cycle.
The reference pulse is generated at a predetermined generation cycle Ta. A first refresh request signal (first request signal) is transmitted at a timing when a predetermined period Tb (<Ta) has elapsed since the generation of a certain reference pulse. Further, the second refresh request signal (second request signal) is transmitted at the same timing as the generation of the next reference pulse. That is, in the prior art, refresh to the DRAM 4 is instructed in any one of the period Td from the generation timing T1 of the first request signal to the timing T2 of generation of the second request signal.

  Note that these periods Ta and Tb are stored in advance in a register of the refresh control unit 63 or the like.

The single pixel processing unit 51, the pixel interpolation unit 52, and the image compression unit 53 of the RPU 5 include data transfer units 7a to 7e, respectively.
The data transfer units 7a to 7e include FIFOs 8a to 8e serving as buffer memories used for data transfer, and transmit a transfer request signal for requesting data transfer to the arbitrator 61 based on the amount of data stored in the FIFOs 8a to 8e. .

FIG. 11 is a diagram illustrating an operation flow performed by the arbitrator 61 and the control signal transmission unit 62.
Here, the arbitrator 61 determines request signals in the order of the second request signal, the transfer request signal, and the first request signal, and determines a request signal to be executed with this order as a priority.
First, when the second request signal is input to the arbitrator 61 (S1: YES), refresh is executed regardless of the presence or absence of the transfer request signal (S4). That is, a refresh instruction signal is transmitted from the control signal transmission unit 62 to the DRAM 4 in order to refresh the DRAM 4 (step S4). If the second request signal is not input (S1: NO), the presence / absence of a transfer request signal is determined (S2). If there is a transfer request (S2: YES), the data transfer related to the transfer request signal is performed as a control signal. Instructed by the transmission unit 62 (S7).
If neither the second request signal nor the transfer request signal is input (S1: NO, S2: NO), if the first request signal is input (S3: YES), refresh is executed (S4).

In the prior art, refresh is instructed in any period Td (= Ta−Tb) from the time point T1 of the first request signal generation timing to the time point T2 of the second request signal generation timing.
In other words, refresh is not instructed at the generation timing of the second request signal (reference pulse generation timing) with a high level of urgency of refresh, and refresh can be instructed before the generation timing of the second request signal. As described above, a period (hereinafter referred to as “margin period”) Td having a certain width is provided.
As a result, the execution of refresh is adjusted within the grace period Td according to the degree of congestion of the bus 20 used for data transfer.
By performing refresh while the degree of congestion of the bus 20 is relatively low, it is possible to prevent a decrease in data transfer efficiency associated with the refresh, and as a result, it is possible to improve data transfer efficiency.

JP 2007-257774 A

In the above prior art, from the relationship of the priority of signal processing in the arbitrator 61, even if the first request signal is input, if the transfer request signal is input, the presence / absence of the transfer request signal is preferentially determined. Then, processing based on the transfer request signal is executed.
That is, data transfer is executed, and refresh by the first request signal is not executed.

Here, the second request signal may be input to the arbitrator 61 after the refresh operation by the first request signal is skipped due to the presence of the data transfer request. That is, since the refresh operation by the first request signal is skipped, the second refresh request signal (second request signal) is transmitted at the same timing as the generation of the next reference pulse.
When the second request signal is input to the arbitrator 61, the DRAM 4 is in a state of high refresh urgency. Then, refresh is executed regardless of the transmission request signal transmission state.

Then, after the refresh by the first request signal is skipped due to the presence of the data transfer request signal, the number of data transfer requests may increase further during the margin period Td. The second request signal will compete where there are many requests.
If refresh is executed in this state, the overlap between the refresh and the data transfer increases, causing a problem that the efficiency of the data transfer is significantly reduced.

In recent years, in fields where it is necessary to process an enormous amount of data such as images as needed, it is required to transfer data at high speed to a DRAM that stores data to be processed.
In a system that performs image processing, the number of data transfer requests to the DRAM is not always constant, and the number of data transfer requests increases during the period of fetching data to be processed from the DRAM. The number of data transfer requests tends to decrease.
However, in the conventional memory control device, there is a risk that the overlap between refresh and data transfer will increase and the efficiency of data transfer will remarkably decrease, and it will not be possible to meet the demand for high-speed data transfer. There's a problem.

  A memory control device according to the present invention receives a data transfer request from a refresh control unit that generates a memory refresh request and a plurality of modules that perform data transfer between the memory and the refresh request from the refresh control unit. And an arbitrator that arbitrates between the data transfer request and the refresh request and gives an operation request to the memory, wherein the refresh control unit performs a refresh request at a cycle in which the memory needs to be refreshed. It is predicted that the number of future data transfer requests will increase based on the pulse generation circuit for generating the second request signal and the count value of the data transfer request input via the arbitrator and its fluctuation tendency Generate a first request signal that is a refresh request Comprises a dynamic prediction circuit, wherein the arbitrator, the second request signal, said first request signal, and performs arbitration of the demand signal priority by the data transfer request signal.

  The memory control method of the present invention is a memory control method for arbitrating between a data transfer request and a refresh request for a memory, and generates a second request signal that is a refresh request at a cycle in which the memory needs to be refreshed. A first request signal that is a refresh request is generated when it is predicted that the number of future data transfer requests will increase based on the count value of the transfer request and its fluctuation tendency, the second request signal, the first request signal The request signal is arbitrated in the priority order of the request signal and the data transfer request signal.

In a refresh control circuit for a memory such as DRAM that requires refreshing, the number of data transfer requests in a certain period and its change are predicted to increase the number of data transfer requests in the future, and if the number of data transfer requests is expected to increase, A refresh request is generated and refresh is executed.
By performing refresh before the number of data transfer requests increases and reducing the overlap between refresh and data transfer, it is possible to prevent a decrease in data transfer efficiency associated with refresh and improve data transfer efficiency.

The figure which shows the structure of 1st Embodiment 3 is a flowchart showing an operation procedure of the first embodiment. The figure for demonstrating the operation example of 1st Embodiment. The figure for demonstrating the operation example of 1st Embodiment. The figure for demonstrating the effect of 1st Embodiment. The figure which shows the structure of 2nd Embodiment. 9 is a flowchart showing an operation procedure of the second embodiment. The figure for demonstrating the operation example of 2nd Embodiment. The figure which shows the structure of the conventional memory control apparatus. 9 is a timing chart showing signal generation timing in a conventional memory control device. The flowchart which shows the operation | movement procedure in the conventional memory control apparatus.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be illustrated and described with reference to reference numerals attached to respective elements in the drawings.
(First embodiment)
FIG. 1 is a diagram showing a configuration of a first embodiment according to a DRAM control device (memory control device) of the present invention.
Arbitrator 103 receives data transfer request signal 1 from CPU core 101, data transfer request signal 2 from peripheral macro 102, and refresh request signal from refresh control unit 106A.
Arbitrator 103 outputs a refresh request to control signal transmission unit 104 when a refresh request signal is input.
Further, the arbitrator 103 outputs a data transfer request to the control signal transmitting unit 104 when the refresh request signal is not input and the data transfer request signals 1 and 2 are input.
Further, when the data transfer request signal 1 from the CPU core 101 and the data transfer request signal 2 from the peripheral macro 102 are input to the arbitrator 103, the data transfer request signal 1 and the data transfer request signal 2 are directly used as data. The transfer request signal 3 is output to the refresh control unit 106A.

The data transfer request signal 3 is input from the arbitrator 103 to the refresh control unit 106A. Then, the refresh control unit 106A predicts the number of data transfer requests in the future based on the number of data transfer requests in a certain period and the change thereof.
When the number of data transfer requests is expected to increase, the refresh control unit 106A outputs a refresh request signal to the arbitrator 103.

  The control signal transmission unit 104 receives the request signal from the arbitrator 103 and outputs a control signal to the DRAM 105.

The refresh control unit 106A includes the following circuit.
The refresh request circuit 133 receives the second request signal and the first request signal and makes a refresh request to the arbitrator 103.
Here, the second request signal is a signal generated by the pulse generation circuit 131 and generated in the refresh cycle of the DRAM 105.
The pulse generation circuit 131 has a counter inside, and generates a second request signal that is a refresh request to the refresh request circuit 133 at a period in which the DRAM 105 needs to be refreshed.
On the other hand, the first request signal is a signal generated as a refresh request from the fluctuation prediction circuit 132 when the number of data transfer requests is expected to increase.
However, the refresh request circuit 133 ignores the second and subsequent refresh requests when it receives a plurality of refresh requests from the pulse generation circuit 131 and the fluctuation prediction circuit 132 during a certain period.

  A configuration and operation for the fluctuation prediction circuit 132 to predict an increase in the number of data transfer requests in the future from the number of data transfer requests in a certain period and changes thereof will be described.

The data transfer request signal 3 from the arbitrator 103 is input to the transfer request count circuit 121.
The transfer request count circuit 121 is set with a sampling period which is a period obtained by equally dividing a refresh cycle required by the DRAM 105 into a plurality of arbitrary values. The transfer request count circuit 121 counts the number of data transfer requests within the sampling period, and outputs the result to the transfer request count storage circuit 122 and the first variation calculation circuit 123A for each sampling period.

The transfer request count storage circuit 122 stores the transfer request count counted by the transfer request count circuit 121.
Further, when the latest transfer request count is sequentially input to the transfer request count storage circuit 122, the transfer request count storage circuit 122 is in the previous sampling period with respect to the input latest transfer request count. The number of transfer requests is output to first fluctuation calculation circuit 123A and absolute value determination circuit 126.

The first fluctuation calculation circuit 123A receives the latest transfer request count counted by the transfer request count circuit 121 and the transfer request count in the previous sampling period given from the transfer request count storage circuit 122. Has been. Then, the first fluctuation calculating circuit 123A calculates a fluctuation value of the data transfer request count by subtracting the latest transfer request count from the transfer request count in the immediately preceding sampling period.
The first fluctuation calculation circuit 123A outputs the fluctuation value of the number of data transfer requests calculated in this way to the second fluctuation calculation circuit 124B and the fluctuation prediction circuit 132 as the latest fluctuation value.

The second fluctuation calculation circuit 124B stores the latest fluctuation value given from the first fluctuation calculation circuit 123A.
Further, the second fluctuation calculation circuit 124B outputs the fluctuation value of the number of data transfer requests in the immediately preceding sampling period to the fluctuation prediction circuit 132.

A determination reference value that can be arbitrarily set is set in the determination reference register circuit 125A, and the determination reference register circuit 125A outputs the determination reference value to the absolute value determination circuit 126.
To the absolute value determination circuit 126, the determination reference value from the determination reference register circuit A125 and the transfer request count in the previous sampling period given from the transfer request count storage circuit 122 are input. The absolute value determination circuit 126 determines the size of the determination reference value and the number of transfer requests, and outputs the result of the size determination to the fluctuation prediction circuit 132.
When the transfer request count is less than or equal to the determination reference value, the determination result 1 is output. When the transfer request count exceeds the determination reference value, the determination result 0 is output.

The fluctuation prediction circuit 132 is given from the latest fluctuation value given from the first fluctuation calculation circuit 123A, the fluctuation value in the previous sampling period given from the second fluctuation calculation circuit 124B, and the absolute value determination circuit 126. The magnitude determination result is input.
Then, the fluctuation prediction circuit 132 predicts a change in the number of data transfer requests, and outputs a first request signal that is a refresh request to the refresh request circuit 133 when the number of data transfer requests is expected to increase. .

The condition for outputting the first request signal in the fluctuation prediction circuit 132 is when all of the following three conditions are satisfied.
(1) The latest fluctuation value given from the first fluctuation calculation circuit 123A is 1 or more.
(2) The fluctuation value in the immediately preceding sampling period given from the second fluctuation calculation circuit 124B is 0 or less.
(3) The number of data transfer requests in the previous sampling period is less than or equal to the criterion value.
When all of these three conditions are satisfied, the fluctuation prediction circuit 132 outputs a first request signal that is a refresh request to the refresh request circuit 133.

Here, in the case of (1) above, the number of data transfer requests has increased.
In the case of (2) above, the number of data transfer requests in the previous sampling period has not changed or has decreased.
In the case of (3), the number of data transfer requests in the previous sampling period is equal to or less than a certain number.
When these three conditions are satisfied, it can be determined that the number of data transfer requests is shifting from a state where the number of data transfer requests is small to an increasing phase.
Therefore, the fluctuation prediction circuit 132 predicts that the number of future data transfer requests will increase, and outputs a first request signal that is a refresh request.

  If any one of the above three conditions is not satisfied, the fluctuation prediction circuit 132 does not output the first request signal.

  Here, the arbitrator 103, the refresh control unit 106A, and the control signal transmission unit 104 constitute a memory control device.

Next, the operation of the first embodiment will be described with reference to FIG.
FIG. 2 is a flowchart showing an operation procedure of the DRAM control method according to the first embodiment.
First, the pulse generation circuit 131 generates the second request signal at a period in which the DRAM 105 needs to be refreshed. When the second request signal is generated (S101: YES), the second request signal is generated by the refresh request circuit. Is output to 133.
The refresh request circuit 133 receives the second request signal and outputs a refresh request signal to the arbitrator 103.
Upon receiving the refresh request signal, the arbitrator 103 outputs a refresh request to the control signal transmission unit 104 regardless of the presence or absence of the data transfer request signals 1 and 2.
Then, refresh is instructed to the DRAM 105 by the control signal from the control signal transmission unit 104 (S106), and the DRAM 105 is refreshed.

When the second request signal is not generated from the pulse generation circuit 131 (S101: NO), the fluctuation prediction circuit 132 is supplied from the first fluctuation calculation circuit 123, the second fluctuation calculation circuit 124, and the absolute value determination circuit 126. The generation conditions of the first request signal are determined in order based on the obtained data.
That is, in S102, the magnitude of the fluctuation value of the latest data transfer request count obtained by the first fluctuation calculation circuit 123 is checked.
If the fluctuation value of the latest data transfer request count is 1 or more (S102: YES), then, the fluctuation value of the previous data transfer request count given from the second fluctuation calculation circuit 124 is seen.
If the fluctuation value of the previous data transfer request count is 0 or less (S103: NO), then the magnitude judgment result given from the absolute value judgment circuit is seen.

If the absolute value determination circuit determines that the number of data transfer requests in the previous sampling period is less than or equal to the determination reference value (S104: YES), all three conditions for generating the first request signal are satisfied. Will be.
Therefore, in this case, it is predicted that the number of future data transfer requests will increase, and the fluctuation prediction circuit 132 generates the first request signal (S105).

The first request signal is output from the fluctuation prediction circuit to the refresh request circuit 133.
The refresh request circuit 133 receives the first request signal and outputs a refresh request signal to the arbitrator 103.
Upon receiving the refresh request signal, the arbitrator 103 outputs a refresh request to the control signal transmission unit 104 regardless of the presence or absence of the data transfer request signals 1 and 2. Then, refresh is instructed to the DRAM 105 by the control signal from the control signal transmission unit 104 (S106), and the DRAM 105 is refreshed.

When the second request signal is not generated (S101: NO), and when none of the conditions of S102 to S104 is satisfied, the second request signal and the first request signal are input to the refresh request circuit 133. Will not be.
In this case, the refresh request signal is not output from the refresh request circuit 133 to the arbitrator 103.
If there is no refresh request signal, the arbitrator 103 determines whether there are data transfer request signals 1 and 2 from the CPU core 101 or the peripheral macro 102 (S107). If there is a data transfer request (S107: YES), the data transfer request is output to the control signal transmission unit 104, and data transfer is instructed to the DRAM 105 (S108).

3 and 4 are diagrams for explaining an operation example of the first embodiment.
Here, taking a system that performs image processing as an example, the relationship between the fluctuation in the number of data transfer requests and the generation of the first request signal is shown as a specific example.
3 and 4, the vertical axis represents the number of data transfer requests, and the horizontal axis represents time.
Here, the sampling period is a period obtained by dividing the period Ta that requires refreshing of the DRAM 105 into 20 parts.
Further, it is assumed that “5” is set as the determination reference value in the determination reference register circuit 125A.

In FIG. 3, the output of the transfer request count circuit 121 changes to 4, 3, 2, 3, 2,... After the reference T0.
The latest fluctuation value, which is the output of the first fluctuation calculation circuit 123A, is obtained by subtracting the latest transfer request count from the transfer request count in the previous sampling period. That is, the latest fluctuation value changes as −3 · −1 · −1 · 1... After the reference T0.

  The output of the second fluctuation calculation circuit 124B is the fluctuation value in the previous sampling period, and is the same as the latest fluctuation value output from the first fluctuation calculation circuit 123A, delayed by one. That is, it changes to −3 · −3 · −1 · −1... After the reference T0.

Also, the magnitude determination result that is the output of the absolute value determination circuit 126 is obtained by comparing the number of data transfer requests in the previous sampling period with the determination reference value (= 5).
In this example, it becomes 0 · 1 · 1 · 1 ··· after the reference T0.

Therefore, the first timing when the latest fluctuation value is 1 or more, the fluctuation value of the previous sampling period is 0 or less, and the number of data transfer requests in the previous sampling period is less than or equal to the criterion value is shown in FIG. Indicated by Ts1 inside.
At timing Ts1, the fluctuation prediction circuit 132 predicts that the number of future data transfer requests will increase, generates a first request signal, and outputs the first request signal to the refresh request circuit 133. Then, the DRAM 105 is refreshed.

FIG. 4 is a diagram showing an example different from FIG.
Also in FIG. 4, the same processing as in FIG. 3 is executed. Then, the first timing when the latest fluctuation value is 1 or more, the fluctuation value of the previous sampling period is 0 or less, and the number of data transfer requests in the previous sampling period is less than the judgment reference value is shown in FIG. Indicated by Ts2 inside.
Therefore, at timing Ts2, the fluctuation prediction circuit 132 predicts that the number of future data transfer requests will increase, generates a first request signal, and outputs the first request signal to the refresh request circuit 133. Then, the DRAM 105 is refreshed.

Thus, in the present embodiment, a future change in the number of data transfer requests is predicted based on the number of data transfer requests and the change thereof. When the number of data transfer requests is expected to increase, a first request signal is transmitted to refresh the DRAM 105.
In other words, if data transfer requests are expected to increase in the future, the DRAM 105 starts refreshing by the first request signal without waiting for the timing (second request signal) at which the DRAM 105 is absolutely required to be refreshed. .
In this way, by executing refresh before the number of data transfer requests increases, it is possible to avoid a situation where absolutely necessary refresh operations overlap when the number of data transfer requests actually increases.
Thereby, the overlap between the refresh operation and the data transfer request can be reduced, and as a result, the data transfer efficiency can be improved by preventing the data transfer efficiency from being lowered due to the refresh.

(Example 1)
Next, Example 1 that demonstrates the effect of the present invention will be described.
FIG. 5 is a diagram for explaining the effect of the first embodiment.
As an example of the case where the refresh is performed, the prior art and the first embodiment are compared under the following conditions.

DRAM operating speed: 100 MHz (10 ns / cycle)
Refresh cycle: 4 ms
Number of refreshes: 8192 times Distributed refresh times: 1024 times Distributed refresh cycle: 3.91us
Number of judgments during distributed refresh: 16 times Sampling period: 244.1ns
Refresh operation time: 100 ns

FIG. 5 shows the probability that the data transfer and the refresh operation will collide when a data transfer request occurs under the above-mentioned use conditions using the fluctuation in the number of data transfer requests assumed in the system that performs image processing.
Since each sampling period is 244.1 ns, the maximum number of accesses in one sampling period is 24.41 (244.1 ns / 10 ns).
Since the refresh operation time of 100 ns is 10 times of 10 ns for one cycle time, the maximum number of collisions during 24.41 times of access is 10.
In FIG. 5, the expected value of the number of collisions in the first sampling period S1 in which seven times of access has occurred is 10 × (7 / 24.41) = 2.87 times.
According to the first embodiment, since the first request signal is generated at the timing Ts1, the expected number of collisions is 1.23, which is about 8 times the maximum compared to the conventional example and 4 times the average collision probability. Reduction is possible.
Therefore, according to the first embodiment, it is possible to reduce the overlap between refresh and data transfer compared to the prior art, to prevent a decrease in data transfer efficiency associated with refresh, and to improve data transfer efficiency.
Therefore, the effect of the first embodiment has been demonstrated.

(Second embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 6 is a diagram illustrating the configuration of the second embodiment.
In FIG. 6, the transfer request count storage circuit 122 receives the latest transfer request count from the transfer request count count circuit 121 in order, and the transfer request count storage circuit 122 sets the latest transfer request count to be inputted. On the other hand, the number of transfer requests in the previous sampling period is output to the first fluctuation calculation circuit 123A.
Compared to the first embodiment, the second embodiment does not include an absolute value determination circuit.

  A determination reference value that can be arbitrarily set is set in the determination reference register circuit 125A, and the determination reference register circuit 125A outputs the determination reference value to the fluctuation prediction circuit 232.

The first fluctuation calculation circuit 123A calculates the fluctuation value of the data transfer request count by subtracting the latest transfer request count from the transfer request count in the previous sampling period, and calculates the data transfer request count thus calculated. The fluctuation value is output as the latest fluctuation value to the third fluctuation calculation circuit 224C, the tendency determination circuit 226, and the fluctuation prediction circuit 232.
The third fluctuation calculation circuit 124B converts the fluctuation value of the number of data transfer requests input from the first fluctuation calculation circuit 123A into an absolute value.
A value obtained by converting the fluctuation value of the number of data transfer requests into an absolute value is output to the tendency determination circuit 226.

The trend determination circuit 226 receives the latest fluctuation value from the first fluctuation calculation circuit 123A and the absolute value of the fluctuation value given from the third fluctuation calculation circuit 224C. Then, the trend determination circuit 226 monitors the fluctuation value of the number of data transfer requests and the absolute value of the fluctuation value.
Here, based on the fluctuation value of the data transfer request count and the absolute value of the fluctuation value, the fluctuation value of the data transfer request count is −1 or less, the data transfer request count is decreasing, and the fluctuation value When it is detected that the absolute value of has once increased and then decreased, the tendency determination circuit 226 outputs a high level as a tendency determination result to the fluctuation prediction circuit 232.

The fluctuation prediction circuit 232 is input with the judgment reference value set in the judgment reference register circuit 225B, the latest fluctuation value given from the first fluctuation calculation circuit 123A, and the tendency judgment result given from the trend judgment circuit 226. Has been.
The fluctuation prediction circuit 232 predicts a change in the number of data transfer requests, and outputs a first request signal that is a refresh request to the refresh request circuit 133 when the number of data transfer requests is expected to increase. .

The condition for the fluctuation prediction circuit 232 to output the first request signal is when all of the following three conditions are satisfied.
(1) The trend determination result from the trend determination circuit 226 is at a high level.
(2) The latest fluctuation value from the first fluctuation calculation circuit 123A is 0 or less.
(3) The latest fluctuation value from the first fluctuation calculation circuit 123A is equal to or greater than the determination reference value set in the determination reference register circuit 225B.
When these three conditions are satisfied, the fluctuation prediction circuit 232 outputs a first request signal that is a refresh request to the refresh request circuit 133.

Here, in the case of (1), the number of data transfer requests tends to decrease, and since the degree of decrease is decreasing, the data transfer requests are approaching the least.
In the case of (2) above, the number of data transfer requests has not changed or has decreased.
In the case of (3) above, since the degree of decrease in the number of data transfer requests is less than a certain value (judgment reference value), a gradually decreasing curved surface is entered from the phase of greatly decreasing, approaching the phase of the least data transfer requests. Will be.
Therefore, when these conditions are satisfied, the number of data transfer requests is close to the smallest state, and can be predicted to increase in the future.
Therefore, the fluctuation prediction circuit 232 outputs a first request signal that is a refresh request.

  If any one of the above three conditions is not satisfied, the fluctuation prediction circuit 232 does not output the first request signal.

The operation of the second embodiment will be described with reference to FIG.
FIG. 7 is a flowchart showing the procedure of the DRAM control method according to the second embodiment.
When the second request signal is output from the pulse generation circuit 131 (S101: YES), the arbitrator 103 outputs a refresh request to the control signal transmission unit 104 regardless of the presence or absence of the data transfer request signals 1 and 2 (S106). The DRAM 105 is refreshed.
In a state where the second request signal is not generated from the pulse generation circuit 131 (S101: NO), first, it is checked whether or not a condition for outputting a high level is satisfied in the determination by the tendency determination circuit 226.
That is, in S202, the magnitude of the fluctuation value of the latest data transfer request number obtained by the first fluctuation calculation circuit 123 is checked.
When the number of data transfer requests is decreasing, that is, when the number of data transfer requests is −1 or less (S202: YES), the absolute value of the fluctuation value of the number of data transfer requests obtained by the third fluctuation calculation circuit is subsequently determined. Look at the value.
When the absolute value has increased once and then decreased (S203: YES), the tendency determination circuit 226 outputs a high level to the fluctuation prediction circuit 232 as a tendency determination result.

Subsequently, after receiving the high level, the fluctuation prediction circuit 232 further determines whether the condition for generating the first request signal is satisfied.
That is, by looking at the latest fluctuation value of the number of data transfer requests obtained by the first fluctuation calculation circuit 123, if the fluctuation value is equal to or less than 0 (S205: YES), the fluctuation value is then determined as a determination reference register circuit. Contrast with the criterion value set in 225B. If the variation value is equal to or greater than the determination reference value (S206: YES), the condition for generating the first request signal is satisfied.
Therefore, in this case, the number of data transfer requests is close to the state where it is the smallest, and it is predicted that the number of data transfer requests will increase in the future, and the fluctuation prediction circuit 232 generates the first request signal (S207).

The first request signal is output from the fluctuation prediction circuit 232 to the refresh request circuit 133.
The refresh request circuit 133 receives the first request signal and outputs a refresh request signal to the arbitrator 103.
Upon receiving the refresh request signal, the arbitrator 103 outputs a refresh request to the control signal transmission unit 104 regardless of the presence or absence of the data transfer request signals 1 and 2. Then, refresh is instructed to the DRAM 105 by the control signal from the control signal transmission unit 104 (S106), and the DRAM 105 is refreshed.

When the second request signal is not generated (S101: NO), and when none of the conditions of S202 to S206 is satisfied, the second request signal and the first request signal are input to the refresh request circuit 133. Will not be.
In this case, the refresh request signal is not output from the refresh request circuit 133 to the arbitrator 103.
If there is no refresh request signal, the arbitrator 103 determines whether there are data transfer request signals 1 and 2 from the CPU core 101 or the peripheral macro 102 (S107). If there is a data transfer request (S107: YES), the data transfer request is output to the control signal transmission unit 104, and data transfer is instructed to the DRAM 105 (S108).

FIG. 8 is a diagram for explaining an operation example of the second embodiment.
Here, taking a system that performs image processing as an example, the relationship between the fluctuation in the number of data transfer requests and the generation of the first request signal is shown as a specific example.
3 and 4, the vertical axis represents the number of data transfer requests, and the horizontal axis represents time.
The sampling period is a period obtained by dividing the period Ta, which requires refreshing the DRAM 105, into 20 parts.
Further, it is assumed that “−1” is set as the determination reference value in the determination reference register circuit 125A.

8, the output of the transfer request count circuit 121 changes to 9, 13, 16,..., 18, 16, 13, 9, 6, 4, 3, 2,.
The latest fluctuation value, which is the output of the first fluctuation calculation circuit 123A, is obtained by subtracting the latest transfer request count from the transfer request count in the previous sampling period.
In other words, the latest fluctuation value changes from the standard T0 onward as 3, 4, 3, ... -1, -2, -3, -4, -3, -2, -1, -1 ... .

The output of the third fluctuation calculation circuit 224C is obtained by converting the output value from the first fluctuation calculation circuit 123A into an absolute value.
That is, after the reference T0, it changes to 3, 4, 3,... 1, 2, 3, 4, 3, 3, 2, 1, 1,.

The trend determination circuit 226 determines whether the condition for outputting a high level is satisfied based on the fluctuation value given from the first fluctuation calculation circuit 123A and the absolute value of the fluctuation value given from the third fluctuation calculation circuit 224C. Determine.
That is, when it is detected that the number of data transfer requests is decreasing and the absolute value of the fluctuation value is once increased and then changed to a decreasing state, the tendency determination circuit 226 outputs a high level.
In this example, the tendency determination result changes as 0 · 0 · 0 ... 0 · 0 · 0 · 0 · 1 · 1 · 1 · 1 ··· after the reference T0.

Therefore, the first timing when the tendency determination result is in the high level state, the fluctuation value is 0 or less, and the fluctuation value is equal to or greater than the determination reference value (= −1) set in the determination reference register circuit 225B is shown in FIG. Indicated by Ts3 inside.
At timing Ts3, the fluctuation prediction circuit 232 is in a state close to a state where the number of data transfer requests is the smallest, and predicts that the number of data transfer requests will increase in the future, generates a first request signal, and generates a refresh request circuit. Output to 133. Then, the DRAM 105 is refreshed.

In the first embodiment, the DRAM 105 is refreshed by predicting that the number of future data transfer requests will increase at the timing when the latest number of data transfer requests has increased.
On the other hand, in the second embodiment, the DRAM 105 can be refreshed by predicting that the number of future data transfer requests will increase at the timing before the number of data transfer requests increases.

(Modification 1)
In the first embodiment, the absolute value determination circuit 126 is provided, and the absolute value determination circuit 126 receives the determination reference value (for example, five times) set in the determination reference register circuit 125A and the data transfer request in the previous sampling period. In comparison with the number of times, when the number of times of data transfer is less than or equal to the judgment reference value, the judgment result 1 is output.
The fluctuation prediction circuit 132 sets that the determination result “1” is satisfied as one of the conditions for generating the first request signal.
Here, as a first modification, the determination reference register circuit 125A is changed to a configuration in which a plurality of values can be set, and the determination to be output to the absolute value determination circuit 126 depending on whether it is in the first half or the second half in the refresh cycle of the DRAM 105 The reference value may be changed.
As a result, the condition for generating the first request signal can be changed according to the time until the refresh of the DRAM 105 is always necessary.
By changing the conditions for generating the first request signal in this way, the DRAM can be refreshed at a more optimal timing.
Such a change in the determination reference value can also be applied to the determination reference value set in the determination reference register circuit 225B in the second embodiment.

(Modification 2)
In the first embodiment and the second embodiment, a memory circuit for storing one or both of the maximum value and the minimum value of the number of data transfer requests in the refresh cycle is added, and the number of data transfer requests stored in the memory circuit The upper limit of the latest number of data transfer requests may be determined as one of the conditions for generating the first request signal based on the number of times information.
With this configuration, the change in the number of data transfer requests can be seen over a wide time range, and the conditions for generating the first request signal can be automatically changed according to the overall trend.

For example, the maximum or minimum value of the number of data transfer requests stored in the storage circuit is used as the upper limit of the latest number of data transfer requests as it is, and the conditions described in the first embodiment or the second embodiment in a state where this is satisfied The first request signal may be generated when the above is satisfied.
Alternatively, the reference value may be automatically generated by adding or subtracting a predetermined value to the maximum value or the minimum value of the number of data transfer requests stored in the storage circuit.

  Further, the maximum value and minimum value of the number of data transfer requests in the previous refresh cycle may be stored, the maximum value and minimum value of the data transfer request number in the previous refresh cycle may be stored, and A value obtained by averaging the maximum value and the minimum value of the number of data transfer requests in a plurality of refresh cycles may be stored.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention.

101 ... CPU core, 102 ... peripheral macro, 103 ... arbitrator, 104 ... control signal transmission unit, 105 ... DRAM, 106A ... refresh control unit, 121 ... transfer request count circuit, 122 ... transfer request count storage circuit, 123A ... 1 fluctuation calculation circuit 124B second fluctuation calculation circuit 125A determination criterion register circuit 126 absolute value determination circuit 131 pulse generation circuit 132 fluctuation prediction circuit 133 refresh request circuit 206 refresh control unit , 224C, a third fluctuation calculation circuit, 225, a judgment reference register circuit, 226, a tendency judgment circuit, and 232, a fluctuation prediction circuit.

Claims (1)

A refresh controller for generating a memory refresh request;
Receives data transfer requests from a plurality of modules that transfer data to and from the memory, receives a refresh request from the refresh control unit, and operates the memory by arbitrating the data transfer request and the refresh request In a memory control device comprising an arbitrator for giving a request,
The refresh control unit
A pulse generation circuit for generating a second request signal that is a refresh request at a cycle in which the memory needs to be refreshed;
A first request signal that is a refresh request is generated when it is predicted that the number of future data transfer requests will increase based on the count value of the data transfer request input via the arbitrator and its fluctuation tendency A fluctuation prediction circuit,
The arbitrator arbitrates request signals in the priority order of the second request signal, the first request signal, and the data transfer request.

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