KR20140095399A - Adaptive service controller, system on chip and method of controlling the same - Google Patents

Abstract

The system-on-chip includes at least one slave intelligent element, a plurality of master intelligent elements, an interconnect device, and a plurality of service controllers. The master intelligent elements each generate requests for requesting service to the slave intelligent element. The interconnection device is connected to the slave intelligent element and the master intelligent elements through respective channels, and performs intervention of the requests. The service controllers adaptively control the request flows of the master intelligent elements according to changes in the operating environment of the system-on-chip.

Description

Adaptive service controller, system-on-chip and system-on-chip control method

The present invention relates to a semiconductor integrated circuit, and more particularly, to an adaptive service controller, a system-on-chip, and a system-on-chip control method for improving service quality of a plurality of master intelligent devices.

A system on chip (SOC) refers to a single chip on which various semiconductor components are integrated or a system integrated on the chip. In recent years, demand for application specific integrated circuits (ASICs) and application specific standard products (ASSPs) has gradually been shifting to system-on-chips. In addition, the trend of thinning and high performance of electronic devices has become a factor to promote the system-on-chip industry.

As system-on-chip integration increases, more components are integrated on a single chip, but the operating speed of the system-on-chip is not increasing enough. Due to the limited operating speeds, it is difficult to meet the service requirement levels of various master intelligent devices.

An object of the present invention is to provide a service controller capable of adaptively controlling a request flow according to a change in an operating environment and a system on chip including the service controller.

It is an object of the present invention to provide a control method of a system-on-chip that can adaptively control a request flow in accordance with a change in an operating environment.

To achieve the above object, a system-on-chip according to embodiments of the present invention includes at least one slave intelligent element, a plurality of master intelligent elements each for generating a request for requesting service to the slave intelligent element, And an interconnection device connected to the slave intelligent device and the master intelligent devices through channels of the master intelligent device and adapted to perform an arbitration operation of the requests, And a plurality of service controllers for controlling flows.

The system-on-chip may further include a global controller for generating a global control signal indicative of a change in the operating environment based on the at least one status signal. The service controllers may control respective request flows based on the global control signal.

The slave intelligent device includes a memory controller, and the master intelligent devices may include a modem and a display controller. Wherein the status signal includes a first status signal activated when the operating temperature of the memory controller is greater than a reference temperature, a second status signal activated when the modem fails to receive service from the slave intelligent device over a reference time, And a third state signal which is activated when the storage rate of data stored in the data buffer of the controller is smaller than a reference rate.

Wherein each of the service controllers comprises: a monitor for detecting a service demand level of the corresponding master intelligent device in real time and outputting a credit value indicating the service demand level; And a control block for generating a local control signal for controlling the monitor based on a change in the operating environment and generating priority information for a request from the corresponding master intelligent element based on the credit value .

The local control signal may include an overflow value, a unit increase value, and a unit decrease value that are determined according to a change in the operating environment. The monitor includes a first counter for generating a first event signal that is activated at a period corresponding to the overflow value, a second counter for generating a second event signal to the corresponding master intelligent element based on the channel signal between the corresponding master intelligent element and the interconnection device A service detector for generating a second event signal that is activated each time a service is provided; and a service detector for incrementing the credit value by the unit increment value each time the first event signal is activated, And a second counter for decreasing the credit value by the unit decrease value.

The control block may control the request flow of the corresponding master intelligent device by changing at least one of the overflow value, the unit increase value, and the unit decrease value based on a change in the operating environment.

Wherein the control block is configured to facilitate the request flow of the corresponding master intelligent device by decreasing the overflow value, increasing the unit increment value, or decreasing the unit decrement value, increasing the overflow value, The request flow of the corresponding master intelligent device can be suppressed by decreasing the unit decrease value or increasing the unit decrease value.

The local control signal may further include a still value provided when the operating environment changes. The second counter may decrease the credit value by the still value.

At least one of the service controllers may further include a limiter for blocking a request flow between the corresponding master intelligent device and the interconnection device in response to a restriction signal from the control block.

The control block may control the request flow of the corresponding master intelligent device by activating the restriction signal when the credit value is smaller than the approval value and changing the approval value based on the change in the operating environment.

Wherein the limiter comprises: a synchronizer for generating a synchronization limit signal in response to the limit signal; a first logic gate for outputting a mask enable signal by logically computing the synchronization limit signal and the valid signal from the corresponding master intelligent element, And a second logic gate for outputting a mask ready signal by logically computing the synchronization restriction signal and the ready signal from the interconnecting device.

The control block sets a plurality of operation modes by dividing the range of the credit value and sets the values of the local control signal differently according to the operation modes to control the request flow of the corresponding master intelligent element . The operating modes include:

A default mode in which the credit value is higher than the upper boundary value, the credit value is lower than the upper boundary value and larger than the lower boundary value, and a dehumidification mode in which the credit value is smaller than the lower threshold value.

Wherein the control block is operable to determine whether the default master mode is enabled or disabled based on the operating modes so that a greater bandwidth is allowed in the promotion mode than in the default mode for the corresponding master intelligent device and a greater bandwidth is allowed in the default mode than in the de- The values of the local control signal can be set.

Wherein the slave intelligent element includes a request queue for storing a plurality of requests transmitted from the master intelligent elements via the interconnecting device and a service queue for the stored requests based on respective priorities of the stored requests. And a scheduler for determining the order.

The master intelligent elements include at least one real-time intelligent element, and the service controller corresponding to the real-time intelligent element can generate an urgent signal indicating that urgent service is required.

The scheduler of the slave intelligent device may increase the priority of the requests generated from the real time intelligent device among the requests stored in the request queue in response to the emergency signal.

The system-on-chip may further include a transmission line connected point-to-point between the slave intelligent device and the service controller corresponding to the real-time intelligent device. The emergency signal can be transmitted directly to the slave intelligent element from the service controller corresponding to the real-time intelligent element through the transmission line.

Wherein the master intelligent elements comprise at least one best effort intelligent element and the slave intelligent element generates an external limiting signal based on a change in the operating environment and wherein the service controller corresponding to the best effort intelligent element And interrupt the request flow between the best effort port intelligent device and the interconnection device in response to the external limiting signal.

The slave intelligent device can activate the external limiting signal when more requests than the reference number are stored in the request queue and the service is waiting.

The master intelligent devices may further include at least one real-time intelligent device, and the slave intelligent device may activate the external limiting signal in response to an urgent signal indicating that urgent service is required for the real-time intelligent device.

The real-time intelligent device includes a display controller, and the best effort intelligent device may include a processor.

The system-on-chip may further include a transmission line that is point-to-point connected between the service controller and the slave intelligent element corresponding to the best effort intelligent element. The external limiting signal may be transmitted from the slave intelligent element through the transmission line directly to the service controller corresponding to the best effort port intelligent element.

In order to achieve the above object, according to embodiments of the present invention, a plurality of master intelligent elements, each of which generates at least one slave intelligent element and requests to request a service for the slave intelligent element, A control method of a chip is provided. The method comprising the steps of: generating at least one status signal indicative of a status of at least one of the slave intelligent element and the master intelligent elements; generating a global control signal indicative of a change in the operating environment of the system- And controlling the request flows of the master intelligent elements adaptively based on the global control signal.

According to embodiments of the present invention, there is provided a service controller for controlling a request flow of a master intelligent device that generates a request for requesting a service to a slave intelligent device.

The service controller generates a local control signal for controlling the monitor on the basis of a change in the operating environment, a monitor for detecting a service requirement level of the master intelligent device in real time and outputting a credit value indicating the service demand level, And a control block for generating priority information on a request from the master intelligent element based on the credit value.

The method of controlling a system-on-chip and a system-on-chip according to embodiments of the present invention can improve quality of service (QOS) by controlling request flows of master intelligent devices adaptively according to a change of an operating environment have.

The system-on-chip and the system-on-chip control method according to embodiments of the present invention can independently set control conditions of request flows for each master intelligent device using a plurality of service controllers assigned to each master intelligent device A complicated scenario according to a change in the operating environment can be easily implemented.

1 is a block diagram illustrating a system according to embodiments of the present invention.
2 is a flowchart illustrating a method of controlling a system according to embodiments of the present invention.
3 is a block diagram illustrating a service controller in accordance with embodiments of the present invention.
4 is a diagram for explaining an example of a method of detecting a service requirement level of a master intelligent device.
5 is a block diagram illustrating an embodiment of a monitor included in the service controller of FIG.
6 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining an example of the operation of the monitor of FIG. 5;
8 is a diagram illustrating an example of a transaction performed by a system according to embodiments of the present invention.
Fig. 9 is a block diagram showing a limiter included in the service controller of Fig. 3; Fig.
10 is a circuit diagram showing an example of a limiter included in the service controller of FIG.
11 is a timing chart showing the operation of the limiter in Fig.
12 is a circuit diagram showing another example of the limiter included in the service controller of Fig.
13 is a timing chart showing the operation of the limiter in Fig.
FIG. 14 is a diagram illustrating a method of controlling a system-on-chip according to an embodiment of the present invention.
15 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
FIG. 16 is a view for explaining an example of the operation of the monitor of FIG. 5 according to the method of FIG.
17 is a block diagram illustrating a system in accordance with embodiments of the present invention.
18 is a block diagram illustrating an example of a service controller included in the system of FIG.
19 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
20 is a diagram illustrating a method of generating an emergency signal according to an embodiment of the present invention.
Figure 21 is a block diagram illustrating an example of a service controller included in the system of Figure 17;
22 is a diagram showing an example of a slave intelligent element included in the system of Fig.
23 is a diagram showing a structure of a request stored in the slave intelligent element of Fig. 22 and an example of an emergency signal.
24 is a block diagram showing an example of application of a system-on-chip according to embodiments of the present invention to an electronic device.
25 is a block diagram showing an example of an interface used in the electronic apparatus of Fig.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having", etc., are used to specify that there are described features, numbers, steps, operations, elements, parts or combinations thereof, and that one or more other features, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a system according to embodiments of the present invention. The system described below may include a system on chip (SOC) in which various semiconductor components are integrated on a single chip.

Referring to FIG. 1, a system 1000 includes slave intelligent devices SLV1 and SLV2 301 and 302, master intelligent devices MST1, MST2, and MST3 101, 102 and 103, service controllers QC1, QC2 and QC3 501 and 502 and 503 and an interconnect device 10. Depending on the embodiment, the system 1000 may further include a global controller 30.

The master intelligent elements 101, 102 and 103 and the slave intelligent elements 301 and 302 may each be referred to as a device and may be referred to as an IP core or an IP block. Depending on the embodiment, each of the master intelligent elements 101, 102, 103 and the slave intelligent elements 301, 302 may be part of a logic unit, cell or chip.

A plurality of master intelligent elements 101, 102, and 103 each generate requests to request service for at least one slave intelligent element 301, 302. At least one intelligent element 301, 302 may be used as a common resource of a plurality of master intelligent elements 101, 102, 103.

The interconnection device 10 is connected to the slave intelligent elements 301, 302 and the master intelligent elements 101, 102, 103 through respective channels. A single channel may be implemented between one intelligent element and the interconnecting device 10, or a plurality of channels may be implemented. For example, when the slave intelligent elements 301 and 302 include a memory controller, a read channel and a write channel can be implemented between one intelligent element and the interconnect device 10, respectively. The interconnection device 10 performs an arbitration operation of requests from the master intelligent elements 101, 102, The interconnection device 10 may include at least one arbiter for the arbitration operation.

The plurality of service controllers 501, 502, and 503 adaptively control the request flows of the master intelligent elements 101, 102, and 103 in accordance with a change in the operating environment of the system 1000.

The change in the operating environment may be provided using one or more status signals ST1, ST2, ST3. For example, the second slave intelligent element 302 may be a memory controller, the second master intelligent element 102 may be a modem, and the third master intelligent element 103 may be a display controller.

The memory controller 302 may generate a first status signal ST1 that is activated when the operating temperature is greater than the reference temperature. The memory controller 302 may include a temperature sensor for detecting the operating temperature. In general, the memory controller 302 is designed to reduce the operating speed in order to ensure reliability of operation when the operating temperature rises above a certain level. When the operation speed of the memory controller 302 is reduced, there is a need for a scenario capable of ensuring the bandwidth of the real-time intelligent device while totally suppressing the request flows of the master intelligent devices using the memory controller 302 as a shared resource do.

The modem 102 may generate a second status signal ST2 that is activated when the slave intelligent device 102 fails to receive a service over the reference time. In general, when the modem 102 fails to receive a service within a predetermined time due to the restriction of the communication protocol with the external device, the already issued request is invalidated. A scenario is required in which the request flow of the other master intelligent device is suppressed so that the modem 102 can be guaranteed a certain latency when the service for the modem 102 is seriously delayed due to a change in the operating environment.

The display controller 103 may generate a third status signal ST3 that is activated when the storage rate of data stored in the internal data buffer is smaller than the reference rate. The display controller 103 corresponds to a real-time intelligent device that regularly requests display data. If the display data can not be serviced in time, the user will directly perceive it as less than product performance. In this case, a scenario is required in which the request flow of other master intelligent elements is suppressed so that the display controller 103 can guarantee a certain bandwidth.

The above-described scenarios can be variously determined according to the operation characteristics of the system 1000, the user's selection, and the like. Examples of scenarios based on conversion of the operating environment according to embodiments of the present invention will be described below with reference to Fig.

1, the system 1000 includes a global (global) control signal (GCON) that generates a global control signal (GCON) indicating a change in the operating environment based on one or more status signals (ST1, ST2, ST3) And may further include a controller 30. In this case, the service controllers 501, 502, 503 can control respective request flows based on the global control signal GCON.

In another embodiment, the global controller 30 may be omitted and the status signals STl, ST2, ST3 may be provided directly to the service controllers 501, 502, 503. In this case, the service controllers 501, 502, 503 can control respective request flows based on respective status signals ST1, ST2, ST3 or a combination thereof.

The number of master intelligent elements and slave intelligent elements shown in Fig. 1 can be variously changed. Depending on the operating characteristics of the master intelligent device, the service controllers may have different configurations, and some service controllers may be omitted.

2 is a flowchart showing a system control method according to embodiments of the present invention.

2 shows a control method of a system in which a plurality of master intelligent elements each generating at least one slave intelligent element and requests for servicing the slave intelligent element are connected to the interconnecting device.

1 and 2, at least one of the slave intelligent elements 301 and 302 and the master intelligent elements 101, 102, and 103 includes one or more status signals ST1, ST2, and ST3 indicating their status, (Step S100). The global controller 30 generates a global control signal GCON indicating a change in the operating environment of the system 1000 based on the status signals ST1, ST2, and ST3 (step S300). The service controllers 501, 502 and 503 adaptively control the request flows of the master intelligent elements 101, 102 and 103 based on the global control signal GCON (step S500).

Various embodiments of the system of Fig. 1 and the control method of the system of Fig. 2 will be described below with reference to Figs. 3 to 23. Fig. Only the components necessary for the description of the embodiments in Figs. 3 to 23 can be shown and the redundant description can be omitted.

3 is a block diagram illustrating a service controller in accordance with embodiments of the present invention.

In Fig. 3, one service controller 500a corresponding to one master intelligent device 100 is shown. The plurality of service controllers 501, 502, and 503 of FIG. 1 may have the configurations shown in FIG. 3, respectively. As shown in FIG. 3, the service controller 500a may be coupled to a channel between the corresponding master intelligent device 100 and the interconnection device 10. In another embodiment, the service controller 500a may be included within the master intelligent device 100 as part of the master intelligent device 100. [

Referring to FIG. 3, the service controller 500a may be implemented including a limiter 510, a monitor 520, and a control block 530. FIG.

The monitor 520 detects a service requirement level of the corresponding master intelligent device 100 in real time and outputs a credit value (CRD) indicating the service demand level.

The service requirement level may be detected as a bandwidth, an outstand- ing count value, and / or an average latency. The bandwidth represents the amount of data that is transmitted or serviced at a given time. As will be described later, the credit value (CRD) corresponds to the bandwidth. The out-standing count value is the number of requests already issued but not yet completed from the master intelligent device. The latency represents a time interval from when the master intelligent device requests the slave intelligent device to the service to when the requested service is completed. The monitor of FIG. 3 may be implemented to provide at least one of a credit value (CRD) as well as a bandwidth, an outstand count value, and an average latency.

The control block 530 generates a local control signal LCON for controlling the monitor 520 based on a change in the operating environment of the system. The change in the operating environment may be provided as a global control signal GCON as described with reference to Fig. 1, or may be provided as status signals ST1, ST2, ST3. The control block 530 may also generate priority information PRT for the request from the corresponding master intelligent device 100 based on the credit value CRD. The priority information PRT may be provided to the interconnection device 10 and used as a basis for the arbitration operation. At least a portion of the control block 530 may be implemented with a special function register having a configuration to perform a predetermined process sequence in response to stored values and input values.

The limiter 510 blocks the request flow between the corresponding master intelligent device 100 and the interconnect device 10 in response to the limit signal LMT from the control block 530. [ The limiter 510 may be omitted depending on the operation characteristics of the corresponding master intelligent device 100. [

4 is a diagram for explaining an example of a method of detecting a service requirement level of a master intelligent device.

According to the operation characteristics of the master intelligent device, the service requirement level of the master intelligent device can be expressed by a bandwidth. The bandwidth represents the amount of data that is transmitted or serviced at a given time. For example, a master intelligent device such as a display controller receives data from a slave intelligent device such as a memory controller connected through an interconnection device, stores the data in a data buffer, performs a unique function while consuming the stored data .

In Fig. 4, the data occupation state of the line buffer included in the master intelligent element is shown with shading. The occupied state of the data can be represented by a line buffer pointer (LBP). When data from the slave intelligent element is serviced (DATA IN), the line buffer pointer LBP increases in the FULL direction and the master intelligent element consumes the data (DATA OUT), the line buffer pointer LBP becomes empty ) Direction.

As the line buffer pointer (LBP) increases, a lower priority is given and a higher priority can be given as the line buffer pointer (LBP) decreases. That is, the higher the priority, the higher the bandwidth is required. A relation between the line buffer pointer (LBP) and the priority can be set according to the overall scenario of the system. For example, an area between a pool (FULL) and an empty area (EMPTY), which is a range of the line buffer pointer (LBP), can be divided into a plurality of areas, and the driving order can be sequentially designated for each area.

5 is a block diagram illustrating an embodiment of a monitor included in the service controller of FIG.

5, the monitor 520a may be implemented including a first counter (CNT1) 521, a second counter (CNT2) 523, and a service detector (SDET)

The first counter 521 generates a first event signal CEV which is activated in a cycle corresponding to the overflow value OV. For example, the first counter 521 counts the cycle of the clock signal CLK, and the first event signal CEV is a pulse signal that is activated whenever the counted value reaches the overflow value OV . The clock signal CLK may be the operating clock signal of the corresponding master intelligent device 100.

The service detector 525 is operable each time a service is provided to the corresponding master intelligent device 100 based on the channel signal CHN between the corresponding master intelligent device 100 and the interconnect device 10, And generates an event signal SEV.

The second counter 523 increases the credit value CRD by the unit increment value INC every time the first event signal CEV is activated and increments the unit decrease value CRD every time the second event signal SEV is activated. (CRD) as much as the credit value (DEC). The second counter 523 may decrease the credit value CRD by the still value STL provided from the control block 530. [ The control block 530 may provide a still value (STL) only when a change in the operating environment occurs to temporarily reduce the credit value (CRD).

Thus, the current bandwidth requirement level of the corresponding master intelligent device 100 can be expressed as a credit value (CRD). As the credit value (CRD) increases, a relatively large bandwidth is required, and as the credit value (CRD) decreases, a relatively small bandwidth is required.

The overflow value OV, the unit increment value INC, the unit decrement value DEC and the still value STL may be included in the local control signal LCON from the control block 530. The overflow value OV, the unit increment value INC, the unit decrease value DEC, and the still value STL may be determined according to the overall scenario of the system. The control block 530 may change the overflow value OV, the unit increment value INC, the unit decrease value DEC, and the still value STL according to the change of the operating environment. For example, the overflow value OV, the unit increment value INC, the unit decrease value DEC, and the still value STL are provided in the initialization process of the system 1000 according to the change of the operating environment, 530). The user can determine the values for each master intelligent element in consideration of the operating characteristics of the master intelligent elements 101, 102, A complicated scenario of the system 1000 can be easily and efficiently implemented through the distributed control method for each master intelligent device.

FIG. 6 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention, and FIG. 7 is a view for explaining an example of the operation of the monitor of FIG.

6 and 7, each time the first event signal CEV is activated, the credit value CRD increases in the direction of the maximum value MAX and the credit value CRD) decreases in the minimum value (MIN) direction. The activation period of the first event signal CEV corresponds to the target bandwidth and the average activation period of the second event signal SEV corresponds to the currently-served real-time bandwidth. As shown in FIG. 7, if the real time bandwidth is smaller than the target bandwidth, the credit value (CRD) gradually increases, and if the real time bandwidth is larger than the target bandwidth, the credit value (CRD) gradually decreases.

The control block 530 shown in FIG. 3 may give a higher priority as the credit value (CRD) is larger and a lower priority as the credit value (CRD) is smaller. In general, the interconnection device 10 is designed to promote a request flow as a master intelligent device having a high priority and demote a request flow as a master intelligent device having a low priority.

The control block 530 may control the corresponding master intelligent element (e. G., The processor) by changing at least one of an overflow value OV, a unit increment value INC and a unit decrement value DEC based on a change in the operating environment of the system 1000. [ 100 can be controlled. For example, the control block 530 may control the request flow of the corresponding master intelligent device 100 by decreasing the overflow value OV, increasing the unit increment value INC, or decreasing the unit decrement value DEC Can promote. The control block 530 also demotes the request flow of the corresponding master intelligent device 100 by increasing the overflow value OV or decreasing the unit increment value INC or increasing the unit decrement value DEC, can do.

3, at least one service controller 500a is connected between the corresponding master intelligent device 100 and the interconnect device 10 in response to a limit signal LMT from the control block 530 And a limiter 510 for blocking the request flow of the request. Embodiments of limiter 510 are described below with reference to Figures 9-13.

If the service controller 500a includes the limiter 510, the control block 530 may generate a limit signal LMT that is activated when the credit value CRD is less than the grant value GRN. The control block 530 may control the request flow of the corresponding master intelligent device 100 by changing the grant value GRN based on a change in the operating environment of the system. The request flow of the corresponding master intelligent device 100 is further suppressed as the approval value GRN is set larger and the request flow of the corresponding master intelligent device 100 is further promoted as the approval value GRN is set smaller .

8 is a diagram illustrating an example of a transaction performed by a system according to embodiments of the present invention.

FIG. 8 shows an example of a read transaction according to the AXI (Advanced Extensible Interface) protocol for convenience of explanation. The AXI protocol adopts a handshake mechanism using valid signals (ARVALID, RVALID) and ready signals (ARREADY, RREADY).

According to the handshake method, one side of the master interface and the slave interface activates the valid signal at the time of signal transmission and activates the ready signal at the other side when ready to receive. Sampling of the transmission signal is performed in synchronization with the rising edge of the global clock signal ACLK in both the master interface and the slave interface. Therefore, valid signal transmission is performed only when the valid signal and the corresponding ready signal are all activated at the rising edge of the global clock signal ACLK.

As shown in Fig. 8, the master intelligent device 100 corresponding to the master interface activates the request valid signal ARVALID at the time of signal transmission and the interconnection device 10 corresponding to the slave interface is ready to receive Activates the request ready signal (ARREADY). Similarly, the interconnection device 10 activates the service enable signal RVALID at the time of signal transmission and the master intelligent device 100 activates the service ready signal RREADY when ready to receive.

In FIG. 8, the time points indicating the rising edges of the global clock signal ACLK are indicated by T0 to T13. The master interface, for example, the master intelligent element 100 sends a read request signal ARADDR to the slave interface, for example, the interconnect device 10, along with a read valid signal (" ARVALID). At the time T2, both the valid signal ARVALID and the ready signal RREADY are activated and the transfer of the read request signal ARADDR is actually performed. However, from the viewpoint of the master interface, it is possible to determine the time T1 as the service request time regardless of whether the ready signal RREADY of the slave interface is activated, that is, regardless of whether the actual signal transmission is successful or not.

The data D (A0), D (A1), D (A2), and D (A3) are transmitted from the interconnection device 10 to the master intelligent device 100 by the burst transfer method as a response to the read request do. The interconnecting device 10 activates the RLAST signal corresponding to the service completion signal together with the transmission of the last data D (A3), and the time T13 is determined as the service completion time.

3 receives the request signal between the master intelligent device 100 and the interconnection device 10 among the channel signals CHN between the master intelligent device 100 and the interconnection device 10. In this case, (RVALID, RREADY, RLAST) on the basis of the service request time (ARVALID, ARREADY), that is, the time of issuance of the request, and the service signals (RVALID, RREADY, RLAST).

The latency (LAT) indicates a time interval from when the master intelligent device requests service to the slave intelligent device to when the requested service is completed. For example, the latency (LAT) is expressed by the number of cycles of the clock signal .

Fig. 9 is a block diagram showing a limiter included in the service controller of Fig. 3; Fig.

9, the limiter 510 may include a synchronizer (SYNC) 512 and a mask unit (MASK) 515.

Synchronizer 512 generates a synchronized limit signal (SMSK) based on the limit signal (LMT) from control block (530). The masking unit 515 blocks the request from the corresponding master intelligent device 100 in response to the synchronization limit signal SMSK.

The synchronizer 512 controls the transition point of the limit signal LMT in order to prevent the error of the handshake signal transmission between the master intelligent device 100 and the interconnection device 10.

10 is a circuit diagram showing an example of a limiter included in the service controller of FIG.

Referring to FIG. 10, the limiter 510a may include a flip-flop (FF) 512a and a masking unit 515a corresponding to a synchronizer.

The flip-flop 512a generates the synchronization limit signal SMSK based on the limit signal LMT from the control block 530 and the inverse global clock signal ACLKb. The flip-flop 512a samples the limit signal LMT in response to the rising edge of the inverted global clock signal ACLKb to generate a synchronization limit signal SMSK. The rising edge of the inverted global clock signal ACLKb corresponds to the falling edge of the global clock signal ACLK and consequently the transition point of the synchronization limiting signal SMSK is synchronized to the falling edge of the global clock signal ACLK.

The mask section 515a blocks the request from the corresponding master intelligent element 10 in response to the synchronization limiting signal SMSK. The mask portion 515a may include a first logic gate 516 and a second logic gate 517. [ The first logic gate 516 outputs a masked valid signal MVALID by logically operating the synchronization limit signal SMSK and the valid signal VALID from the corresponding master intelligent device 100. The second logic gate 517 outputs a masked ready signal MREADY by logically operating the synchronization limit signal SMSK and the ready signal READY from the interconnecting device 10.

For example, when the synchronization limiting signal SMSK is inactivated to the logic low level, the masking unit 515a outputs the mask enable signal MVALID having the same logic level as the valid signal VALID and the ready signal READY, And the mask ready signal MREADY. When the synchronization limiting signal SMSK is activated to the logic high level, the masking unit 515a outputs the mask enable signal disabled in the logic low level regardless of the logic level of the valid signal VALID and the ready signal READY MVALID) and a mask ready signal MREADY.

11 is a timing chart showing the operation of the limiter in Fig.

As described with reference to Fig. 8, the master intelligent device 100 activates the valid signal VALID when transmitting the request signal and the interconnection device 10 corresponding to the slave is ready to receive ). The interconnection apparatus 10 receives the mask valid signal MVALID and the master intelligent element 100 receives the mask ready signal MREADY by the mask unit 515a of Fig. In other words, when the valid signal VALID and the mask ready signal MREADY are all activated at the rising edge of the global clock signal ACLK, the master intelligent device 100 determines that a valid signal transfer has been made, The controller 10 determines that effective signal transmission has been performed when both the mask valid signal MVALID and the ready signal READY have been activated at the rising edge of the global clock signal ACLK.

It may be determined that only one of the master intelligent device 100 and the interconnection device 10 has performed valid signal transmission although an actually effective signal transmission has not been performed due to the inconsistency of the judgment criteria.

In order to prevent such an error, the limiter 510a of FIG. 10 synchronizes the start and end points of the masked interval (tMSK) with the falling edge of the global clock signal ACLK. Synchronizes the transition point of the synchronization limiting signal SMSK with the falling edge of the global clock signal ACLK irrespective of the transition point of the limiting signal LMT. Thus, the starting and ending points of the masking can be clearly separated from the sampling point of the master intelligent element 100 and the interconnection device 10, that is, the rising edge of the global clock signal ACLK.

Since the mask valid signal MVALID and the mask ready signal MREADY have the same logic level as the valid signal VALID and the ready signal READY at the sampling times SP1 and SP3 not belonging to the mask interval, A handshake is performed, and a valid signal transmission is performed at sampling points (SP1, SP3). On the other hand, at the sampling point SP2 belonging to the mask section, the master intelligent element 100 and the interconnection device 10 are respectively inactivated mask ready signal It is determined that effective signal transmission has not been performed based on the mask valid signal MREADY and the mask valid signal MVALID.

12 is a circuit diagram showing another example of the limiter included in the service controller of Fig.

Referring to FIG. 12, the limiter 510b may include a synchronizer 512b and a masking unit 515b.

The synchronizer 512b generates a synchronization limit signal SMSKb based on the limit signal LMT, the global clock signal ACLK, the valid signal VALID and the mask ready signal MREADY from the control block 530 do. Contrary to the embodiment of FIG. 10, the synchronization limit signal SMSKb may correspond to an activation level at a logic low level. The operation of the synchronizer 512b will be described later with reference to FIG.

The mask section 515b blocks the request from the corresponding master intelligent element 100 in response to the synchronization limit signal SMSKb. The mask portion 515b may include a first logic gate 518 and a second logic gate 519. [ The first logic gate 518 outputs a masked valid signal MVALID by logically operating the synchronization limit signal SMSKb and the valid signal VALID from the corresponding master intelligent device 100. The second logic gate 519 outputs a masked ready signal MREADY by logically operating the synchronization limit signal SMSKb and the ready signal READY from the interconnecting device 10.

For example, when the synchronization limiting signal SMSKb is deactivated to the logic high level, the masking unit 515b outputs the mask enable signal MVALID having the same logic level as the valid signal VALID and the ready signal READY, And the mask ready signal MREADY. When the synchronization limiting signal SMSKb is activated to the logic low level, the masking unit 515b outputs the mask enable signal (deactivated to the logic low level) regardless of the logic level of the valid signal VALID and the ready signal READY MVALID) and a mask ready signal MREADY.

13 is a timing chart showing the operation of the limiter in Fig.

As described with reference to Fig. 8, the master intelligent device 100 activates the valid signal VALID when transmitting the request signal and the interconnection device 10 corresponding to the slave is ready to receive ). The interconnecting device 10 receives the mask valid signal MVALID and the master intelligent device 100 receives the mask ready signal MREADY by the mask unit 515b of Fig. In other words, when the valid signal VALID and the mask ready signal MREADY are all activated at the rising edge of the global clock signal ACLK, the master intelligent device 100 determines that a valid signal transfer has been made, The controller 10 determines that effective signal transmission has been performed when both the mask valid signal MVALID and the ready signal READY have been activated at the rising edge of the global clock signal ACLK.

It may be determined that only one of the master intelligent device 100 and the interconnection device 10 has performed valid signal transmission although an actually effective signal transmission has not been performed due to the inconsistency of the judgment criteria.

In order to prevent such an error, the synchronizer 512b of FIG. 12 performs a function of synchronizing the start time of the masked interval (tMSK) immediately after one valid transmission is performed. That is, activates the synchronization limiting signal SMSKb to a logic low level immediately after the sampling point in time SP1 at which the limiting signal LMT is activated and valid transmission is made. Meanwhile, the synchronizer 512b synchronizes the end timing of the mask interval tMSK with the deactivation timing of the limit signal LMT.

Since the mask valid signal MVALID and the mask ready signal MREADY have the same logic level as the valid signal VALID and the ready signal READY at sampling points SP1 and SP5 not belonging to the mask section, A shake is performed, and a valid signal transmission is made at sampling points (SP1, SP5). On the other hand, the master intelligent device 100 and the interconnection device 10 are deactivated in spite of the validation signal VALID and the ready signal READY being activated at the sampling points SP2, SP3 and SP4 belonging to the mask section, It is determined that effective signal transmission has not been performed based on the mask ready signal MREADY and mask valid signal MVALID.

FIG. 14 is a diagram illustrating a method of controlling a system-on-chip according to an embodiment of the present invention.

Fig. 14 illustrates scenarios for controlling the request flow of the system for the illustrative cases. The system includes at least a processor, a modem and a display controller as master intelligence elements, and the master intelligence elements can issue requests to the memory controller corresponding to the slave intelligent elements of the common resource, each requesting a service .

The master intelligent device can be divided into hard real time IP, soft real time IP and best effort IP depending on the type of the master intelligent device.

A hard real-time intelligent device is an intelligent device that underruns a data buffer if the data of a certain bandwidth is constantly used and the required bandwidth is not guaranteed, such as a display intelligent device. Such an intelligent device can sufficiently control the request flow while sufficiently filling the data buffer and generating a request as much as it consumes data.

On the other hand, in order to reduce the manufacturing cost of the system, an external modem chip may share a system-on-chip memory. Such an external modem chip has a characteristic that an error occurs if the average latency requirement is not satisfied. In the case of the modem chip, since the request enters the system-on-chip only when communication occurs, and the types of modem chips vary, it is difficult to grasp the bandwidth demand level of the modem chip.

A soft real-time intelligent device has a frame rate (for example, 30, 60 per sec) such as a video codec (CODEC) and has a plurality of frame buffers with a slightly different bandwidth requirement depending on the characteristics of the frame It is an intelligent device that must be guaranteed the average decode / encode time. Such an intelligent device has a characteristic of going to the next frame of decode / encode as fast as possible without controlling the request flow, but has a characteristic that it can not receive a lot of requests at once because of dependency between data. Therefore, while the operating speed satisfies the frame rate while the constant bandwidth and / or latency is guaranteed, the decay / encode time rapidly increases and the operating speed decreases when the latency exceeds the threshold.

A best-effort intelligent device is an intelligent device that constantly generates a request if it does not control the request flow, such as a 2D, 3D graphics engine (two-dimensional and / or three dimensional graphics engine) or a DMAC (direct memory access controller). These intelligent devices must be flow controlled. It is desirable that the high priority intelligent elements are not as urgent as possible and that the slave intelligent elements such as the memory controller can serve as much as they can afford without limiting the request flow. However, if an emergency situation occurs in a high-priority intelligent device, the priority of the best-effort intelligent device must be limited to a level that allows the slave intelligent device to have a margin, so that a high priority intelligent device can escape from the emergency situation.

On the other hand, a latency oriented IP such as a CPU does not have the required bandwidth, but the bandwidth requirement varies greatly depending on the situation, but the performance is directly affected by the average latency. Because these intelligent devices are difficult to quantify bandwidth requirements, they should receive system priority service according to average latency.

The first case (CASE1) of FIG. 14 shows a default case in which the system operates in the normal state. The processor corresponds to a typical best-effort intelligent device and the display controller corresponds to a typical real-time intelligent device. The overflow value OV, the approval value GRN, and the unit reduction value DEC described above can be suitably set according to the operation characteristics of the master intelligent elements. The above-mentioned unit increment value INC can be set to a value of 1 for all cases and all master intelligent elements. The unit increment value INC may be set to a different value depending on the scenario and the operation characteristics of the master intelligent device according to the embodiment. The overflow value OV may correspond to the number of cycles of the operation clock, for example, the cycle period of the operation clock may be 1 ns (nano second). In the first case (CASE1) of FIG. 1, the display controller may operate at 640 MB / sec and the processor may operate at 2560 MB / sec.

The second case CASE2 may correspond to the case where the third state signal ST3 described with reference to Fig. 1 is activated. That is, in the second case (CASE2), the storage rate of data stored in the data buffer of the display controller becomes smaller than the reference rate, so that urgent service to the display controller is required. In this case, it is possible to set the overflow value of the processor to be larger than the default case, thereby suppressing the request flow of the processor and setting the overflow value of the display controller to be smaller than the default case, thereby promoting the request flow of the display controller. In addition, when the operating environment changes from the first case (CASE1) to the second case (CASE2), the request flow of the processor can be quickly suppressed by reducing the credit value of the processor once (STEAL). In the second case (CASE 2), the display controller may operate at 1280 MB / sec and the processor may operate at 1920 MB / sec.

The third case CASE3 may correspond to the case where the first state signal ST1 described with reference to Fig. 1 is activated. That is, the third case CASE3 may be a case where the operating temperature of the memory controller is larger than the reference temperature, so that the operating speed of the memory controller is reduced. In this case, the overflow value of the processor corresponding to the best effort intelligent element is set to be larger than that of the default case to suppress the request flow of the processor, and the overflow value of the display controller corresponding to the real time intelligent element is set smaller than the default case The bandwidth of the display controller can be maintained. On the other hand, the unit decrease value DEC is set larger for all master intelligent elements than the default case, and the request flow can be suppressed as a whole. In addition, when the operating environment changes from the first case (CASE1) to the third case (CASE3), the request flow of the processor can be quickly suppressed by reducing the credit value of the processor once. In the third case (CASE 3), the display controller may operate at 640 MB / sec and the processor may operate at 960 MB / sec.

The fourth case CASE4 may correspond to the case where the first state signal ST1 and the third state signal ST3 described with reference to FIG. 1 are activated together. That is, in the fourth case (CASE4), the storage rate of the data stored in the data buffer of the display controller becomes smaller than the reference rate, urgent service to the display controller is required and the operation temperature of the memory controller becomes larger than the reference temperature, The speed may be reduced. In this case, the overflow value of the processor corresponding to the best effort intelligent element is set to be larger than that of the default case to suppress the request flow of the processor, and the overflow value of the display controller corresponding to the real time intelligent element is set smaller than the default case The bandwidth of the display controller can be maintained. On the other hand, for the processor and the modem, the unit decrease value DEC can be set larger than the default case, thereby suppressing the request flow and ensuring the bandwidth of the display controller. Further, when the operating environment changes from the first case (CASE1), the second case (CASE2), or the third case (CASE3) to the fourth case (CASE4), by reducing the credit value of the processor once, The flow can be quickly suppressed. In the fourth case (CASE 4), the display controller may operate at 1280 MB / sec and the processor may operate at 320 MB / sec.

The fifth case CASE5 may correspond to the case where the second state signal ST2 described with reference to FIG. 1 is activated. That is, the fifth case (CASE5) may be the case where the modem does not receive service from the memory controller for a reference time or more. In this case, the overflow value of the processor corresponding to the best effort intelligent device can be set to infinity to block the request flow of the processor. Setting the overflow value of the processor to infinity may be to activate the limit signal LMT regardless of the above-mentioned credit value (CRD). The request flow between the processor and the interconnection device can be blocked by activating the limit signal LMT in response to the global control signal GCON indicating the fifth case CASE5. In addition, when the operating environment changes from the first case (CASE1) to the fifth case (CASE5), the credit value of the processor can be reduced at once.

As described above, the system on chip and the system on chip control method according to the embodiments of the present invention can improve the service quality by adaptively controlling the request flows of the master intelligent elements according to the change of the operating environment. Further, since the control conditions of the request flows can be independently set for each master intelligent element by using a plurality of service controllers assigned to the respective master intelligent elements, complex scenarios according to the change of the operating environment can be easily implemented.

FIG. 15 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention. FIG. 16 is a view for explaining an example of the operation of the monitor of FIG. 5 according to the method of FIG. to be.

As described above, every time the first event signal CEV is activated, the credit value CRD increases in the direction of the maximum value MAX and the credit value CRD becomes equal to the credit value CRD every time the second event signal SEV is activated And decreases in the minimum value (MIN) direction. The control block 530 may assign a higher priority to a credit value (CRD), and a lower priority value to a credit value (CRD).

15 and 16, the control block 530 sets a plurality of operation modes by dividing a range of a credit value (CRD) and sets the values of the local control signal LCON (OV, INC , And DEC can be set to be different from each other to control the request flow of the corresponding master intelligent device.

For example, the operating modes may include a captured mode, a default mode, and a demo mode. The promotion mode corresponds to the case where the credit value (CRD) is larger than the upper boundary value (UPBN), and the default mode corresponds to the case where the credit value (CRD) is smaller than the upper boundary value (UPBN) , And the deemed mode corresponds to a case in which the credit value (CRD) is smaller than the lower boundary value (LWBN).

The control block 530 controls the values of the local control signal LCON so that a greater bandwidth is allowed in the promotion mode than in the default mode and a larger bandwidth is allowed in the default mode than the de- OV, INC, DEC) can be set. For example, the control block 530 sets the overflow value OV2 in the default mode to be smaller than the overflow value OV1 in the deformation mode, and sets the overflow value OV3 in the promotion mode to the default mode Can be set to be smaller than the overflow value (OV2). The control block 530 sets the unit increment value INC in the default mode to be larger than the unit increment value INC in the deformation mode and sets the unit increment value INC in the promotion mode to the unit in the default mode Can be set to be larger than the increment value INC. FIG. 16 shows a case where the unit decrease value DEC is constant regardless of the operation mode, but the unit decrease value DEC can be set differently according to the operation mode. That is, by decreasing the unit decrease value DEC, the request flow can be promoted and the request flow can be suppressed by increasing the unit decrease value DEC.

17 is a block diagram illustrating a system in accordance with embodiments of the present invention. The system 1000a shown in FIG. 17 is similar to the system 1000 shown in FIG. 1, so redundant description may be omitted.

Referring to FIG. 17, a system 1000a includes slave intelligent devices SLV1 and SLV2 301 and 302, master intelligent devices MST1, MST2 and MST3 101, 102 and 103, service controllers QC1, QC2 and QC3 501 and 502 and 503 and an interconnect device 10. According to an embodiment, the system 1000a may further include a global controller 30. [

A plurality of master intelligent elements 101, 102, and 103 each generate requests to request service for at least one slave intelligent element 301, 302. The interconnection device 10 is connected to the slave intelligent elements 301, 302 and the master intelligent elements 101, 102, 103 through respective channels. The interconnection device 10 performs an arbitration operation of requests from the master intelligent elements 101, 102, The interconnection device 10 may include at least one arbiter for the arbitration operation. The plurality of service controllers 501, 502, and 503 adaptively control the request flows of the master intelligent elements 101, 102, and 103 in accordance with a change in the operating environment of the system 1000.

The master intelligence elements 101, 102, and 103 may include at least one real-time intelligent element. For example, the third master intelligent device 103 may be a real-time intelligent device such as a display controller. Also, the second slave intelligent device 102 may be a memory controller that provides services to the master intelligent devices 101, 102, and 103 in common. In this case, the service controller 503 corresponding to the real-time intelligent device 103 may generate an urgent signal UGNT indicating that urgent service is required.

The system 1000a may further include a transmission line TL2 connected point-to-point between the slave intelligent element 302 and the service controller 503 corresponding to the real-time intelligent element 103 have. The emergency signal UGNT may be transmitted directly from the service controller 503 corresponding to the real-time intelligent element 103 to the slave intelligent element 302 via the transmission line TL2. The emergency signal UGNT may also be provided to the interconnection device 10 and the interconnection device 10 may adjust the priority in the intervention operation based on the emergency signal UGNT.

The master intelligence elements 101, 102, and 103 may include at least one best effort intelligent element. For example, the first master intelligent device 101 may be a best effort intelligent device such as a processor. In this case, the slave intelligent element 302 generates an external limiting signal ELMT based on a change in the operating environment of the system, and the service controller 501 corresponding to the best effort intelligent element 101 generates an external limiting signal It is possible to block the request flow between the best effort intelligent element 101 and the interconnecting device 10 in response to the request signal ELMT.

The system 1000a may further include a transmission line TL1 that is point-to-point connected between the slave intelligent element 302 and the service controller 501 corresponding to the best effort intelligent element 101. [ The external limiting signal ELMT may be transmitted directly from the slave intelligent element 302 to the service controller 501 corresponding to the best effort intelligent element 101 via the transmission line TL1.

18 is a block diagram illustrating an example of a service controller included in the system of FIG.

The service controller 503 shown in Fig. 18 may be a service controller for controlling a request flow of a real-time intelligent device 103 such as a display controller. The service controller 503 of FIG. 18 is similar to the service controller 500a of FIG. 3 except for the operation of the control block, so redundant description may be omitted.

The control block 540 generates a local control signal LCON for controlling the monitor 520 based on a change in the operating environment of the system. The change in the operating environment may be provided as a global control signal GCON as described with reference to Fig. 1, or may be provided as status signals ST1, ST2, ST3. The control block 540 may also generate priority information PRT for the request from the corresponding master intelligent device 103 based on the credit value CRD. The priority information PRT may be provided to the interconnection device 10 and used as a basis for the arbitration operation.

The control block 540 may generate an urgent signal UGNT indicating that urgent service is required for the real-time intelligent device 103 in addition to the priority information PRT. As described above, the emergency signal UGNT is provided to the slave intelligent element 302 in real time so as to be used for facilitating the service for the request of the real-time intelligent element 103 or suppressing the request flow of the other master intelligent element .

At least a portion of the control block 540 may be implemented as a special function register having a configuration to perform a predetermined process sequence in response to stored values and input values.

19 is a diagram for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention.

Referring to FIG. 19, the control block 540 shown in FIG. 18 sets a plurality of operation modes by dividing a range of a credit value (CRD), and sets the values of the local control signal LCON (OV, INC, DEC) can be set differently to control the request flow of the corresponding master intelligent device.

For example, the operation modes may include an emergency mode, a captured motion mode, a default mode, and a deemed mode. The emergency mode corresponds to a case in which the credit value (CRD) is larger than the emergency level (UGL), and the promotion mode corresponds to a case in which the credit value (CRD) is larger than the upper boundary value (UPBN). The urgency level UGL may be set to be equal to or higher than the upper boundary value UPBN. The default mode corresponds to a case where the credit value (CRD) is smaller than the upper boundary value (UPBN) and larger than the lower boundary value (LWBN), and the deemed mode corresponds to the case where the credit value (CRD) .

The control block 540 controls the values of the local control signal LCON so that a larger bandwidth is allowed in the promotion mode than in the default mode and a larger bandwidth is allowed in the default mode than the de- OV, INC, DEC) can be set.

The control block 540 may also activate the emergency signal UGNT if the credit value CRD is greater than the emergency level UGL. When a very urgent service is required for the real-time intelligent device 103 in this way, the urgent signal UGNT is activated, the service for the request of the real-time intelligent device 103 is promoted by using the emergency signal UGNT It is possible to suppress the request flow of other master intelligent elements.

20 is a diagram illustrating a method of generating an emergency signal according to an embodiment of the present invention.

Referring to FIG. 20, an emergency signal UGNT may be generated in a hysteresis scheme by setting different activation and inactivation conditions of the emergency signal UGNT. The control block 540 of FIG. 18 activates the emergency signal UGNT at a time t1 when the credit value CRD becomes larger than the rising emergency level UGLR and the credit value CRD is smaller than the falling emergency level UGLF The emergency signal UGNT can be deactivated at the time point t3 when the signal is lost. The falling emergency level (UGLF) may be set to be less than the rising emergency level (UGLR).

In this case, at the time t2 when the credit value CRD becomes smaller than the rising urgency level UGLR, the activation state of the urgent signal UGNT is maintained and the credit value CRD is decreased to the lower urgency level UGLF At time t3, the emergency signal UGNT is deactivated. By generating the emergency signal (UGNT) by the hysteresis method, it is possible to prevent the frequent change of the operation mode and to control the real time intelligent element to reliably relieve the emergency state.

Figure 21 is a block diagram illustrating an example of a service controller included in the system of Figure 17;

The service controller 501 shown in Fig. 21 may be a service controller for controlling the request flow of the best-effort intelligent device 101 such as a processor. The service controller 503 of FIG. 21 is similar to the service controller 500a of FIG. 3 except for the operating condition of the limiter 510, so redundant description may be omitted.

The limiter 510 of FIG. 21 may be enabled in response to an external limit signal ELMT as well as a limit signal LMT from the control block 530. For this purpose, the service controller 501 may further include an OR gate 550. The OR gate 550 performs an OR operation on the limit signal LMT and the external limit signal ELMT and the limiter 510 can be enabled in response to the output signal of the OR gate 550. [

The limiting signal LMT is activated when the corresponding best port intelligent device 101 is sufficiently serviced and the external limiting signal ELMT is activated when the other master intelligent and / . As a result, the service controller 501 corresponding to the best effort intelligent device 101 can block the request flow of the best effort intelligent device 101 in accordance with the change of the internal state and the external state.

22 is a diagram showing an example of a slave intelligent element included in the system of Fig.

22, the slave intelligent device 302 may include a request queue 310 and a scheduler 320 to control the request flow of the system 1000a of FIG.

The request queue 310 stores a plurality of requests transmitted from the master devices 101, 102, and 103 via the interconnection device 10. When a protocol supporting multiple outstanding transactions or multiple outstanding requests is employed, the slave intelligent device may include at least one request queue 310. [ The request queue 310 stores a plurality of requests that have been issued but not yet completed from the master intelligence elements.

The scheduler 320 may determine the service order for the stored requests based on the priorities of the respective requests stored in the request queue 310. [ The requests are sequentially transmitted to the internal circuit 340 according to the determined service order.

The scheduler 320 generates a request from the real-time intelligent element 103 among the requests stored in the request queue 310 in response to the emergency signal UGNT provided from the service controller 503 corresponding to the real- It is possible to increase the priority of the requests. By increasing the priority, the service for the real-time intelligent device 103 can be promoted, and the emergency state of the real-time intelligent device 103 can be resolved.

The scheduler 320 can activate the queue signal QF when more requests than the reference number are stored in the request queue 310 and are waiting for the service. The OR gate 330 can generate an external limiting signal ELMT by performing an OR operation on the urgent signal UGNT and the poult signal QF. As described above, the emergency signal UGNT may indicate that urgent service is required for the real-time intelligent device, and the external limiting signal ELMT may be used to block the request flow of the best-effort intelligent device.

In this manner, the request flow of the real-time intelligent device can be promoted and the request flow of the best effort intelligent device can be suppressed in accordance with the change of the operating environment by using the emergency signal UGNT and the external limiting signal ELMT.

23 is a diagram showing a structure of a request stored in the slave intelligent element of Fig. 22 and an example of an emergency signal.

23, the requests REQ stored in the request queue 310 include a master identifier (MID) indicating a master intelligent element that generates a request (REQ), a request identifier (AxID) for distinguishing a plurality of requests, The address-command ADD-COM indicating the contents of the request REQ and the priority order AxQ of the request REQ.

The emergency signal UGNT may include a flag value FLG indicating an emergency state of the master intelligent device and a master identifier MID indicating a master intelligent device that generates the emergency signal UGNT. According to the embodiment, the emergency signal UGNT includes only the flag value FLG, and the master identifier MID indicating the master intelligent device that generated the emergency signal UGNT may be provided as a separate signal.

The scheduler 320 of FIG. 22 compares the emergency signal UGNT with the master identifier MID of the requests stored in the request queue 310 when the flag FLG indicates an emergency state, The priority of the issued request can be increased. The service for the priority-increased request can be facilitated and the emergency state of the master intelligent device can be resolved.

24 is a block diagram showing an example of application of a system-on-chip according to embodiments of the present invention to an electronic device.

24, the electronic device 2000 includes a system-on-a-chip 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and an image sensor 1060 can do. 24, the electronic device 2000 may further include ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other electronic devices .

The system on chip 1010 is an application processor system on chip (AP SOC) according to the embodiments of the present invention described with reference to Figs. 1 to 23, and includes an interconnect device INT and a plurality of intelligent devices Function blocks). For example, the intelligent devices include a memory controller (MC), a central processing unit, a display controller (DIS), a file system block (FSYS) a graphics processing unit (GPU), an image signal processor (ISP), a multi-format codec block (MFC), and the like. The memory controller MC corresponds to one of the slave intelligent elements and the plurality of intelligent elements among other intelligent elements correspond to master intelligent elements that use the memory controller MC as a common resource. Although not shown in FIG. 23, as described above, the system-on-chip 1010 includes service controllers that adaptively control request flows of the master intelligent elements according to changes in the operating environment of the system-on-chip.

The system on chip 1010 is coupled to a memory device 1020, a storage device 1030, an input / output device 1040, and an image sensor (not shown) via an address bus, a control bus, and a data bus 2060). Depending on the embodiment, the system on chip 1010 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1020 can store data and program codes necessary for the operation of the electronic device 2000. For example, the memory device 1020 can be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM have. Storage device 1030 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The input / output device 1040 may include input means such as a keyboard, a keypad, a mouse and the like, and output means such as a printer, a display, and the like. Power supply 1050 can supply the operating voltage required for operation of electronic device 2000.

The image sensor 1060 can communicate with the system on chip 1010 via the buses or other communication links. The image sensor 1060 may be integrated on a single chip together with the system-on-chip 1010, or integrated on different chips.

At least some of the components of the electronic device 2000 shown in Fig. 24 may be implemented in various types of packages. For example, at least some of the configurations may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carriers (PLCC), Plastic Dual In- (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline (SSP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package ), And the like.

On the other hand, the electronic device 2000 should be interpreted as all devices and systems including at least one system-on-a-chip. For example, the electronic device 2000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and the like.

25 is a block diagram showing an example of an interface used in the electronic apparatus of Fig.

25, the electronic device 1100 may be implemented as a data processing device capable of using or supporting a MIPI interface and may include a system on chip (AP SOC) 1110 in the form of an application processor chip, an image sensor 1140, And a display 1150 and the like.

The CSI host 1112 of the system on chip 1110 can perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). In one embodiment, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the system on chip 1110 can perform serial communication with the DSI device 1151 of the display 1150 through a display serial interface (DSI).

In one embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). Further, the electronic device 1100 may further include a radio frequency (RF) chip 1160 capable of performing communication with the system-on-chip 1110. The PHY 1113 of the electronic device 1100 and the PHY 1161 of the RF chip 1160 can perform data transmission and reception according to a Mobile Industry Processor Interface (MIPI) DigRF. In addition, the system-on-chip 1110 may further include a DigRF MASTER 1114 that controls data transmission / reception according to the MIPI DigRF of the PHY 1161. [

The electronic device 1100 includes a GPS (Global Positioning System) 1120, a storage 1170, a microphone 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190 . The electronic device 1100 may use an Ultra Wide Band (UWB) 1210, a Wireless Local Area Network (WLAN) 1220 and a Worldwide Interoperability for Microwave Access (WIMAX) So that communication can be performed. The structure and the interface of the electronic device 1100 shown in Fig. 25 are not limited thereto.

The system and system control method according to embodiments of the present invention are useful for any device and system including a plurality of master intelligent elements and at least one slave element commonly accessed by the master intelligent elements . Particularly, the present invention can be effectively applied to a system-on-chip in which various semiconductor components are integrated on a single chip. The present invention can be applied to a digital camera, a mobile phone, a PDA, a PMP ), Smart phones, and the like.

While the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

100, 101, 102, 103: Master intelligent element
10: interconnection device
301, 302: Slave intelligent element
500, 501, 502: Service controller
PRT: Priority information
UGNT: Emergency signal
LMT: Limit signal
ELMT: external limit signal

Claims (20)

At least one slave intelligent element;
A plurality of master intelligent elements each for generating requests for requesting service to the slave intelligent elements;
An interconnection device connected to the slave intelligent device and the master intelligent devices through respective channels and performing an arbitration operation of the requests; And
And a plurality of service controllers for adaptively controlling request flows of the master intelligent elements according to a change in the operating environment of the system-on-chip. The method according to claim 1,
Further comprising a global controller for generating a global control signal indicative of a change in said operating environment based on at least one status signal,
Wherein the service controllers control respective request flows based on the global control signal. 3. The method of claim 2,
Wherein the slave intelligent element includes a memory controller,
Wherein the master intelligent elements comprise a modem and a display controller,
The status signal may include:
A first state signal activated when an operating temperature of the memory controller is greater than a reference temperature;
A second status signal activated when the modem fails to receive a service from the slave intelligent device over a reference time; And
And a third state signal that is activated when the storage rate of data stored in the data buffer of the display controller is less than a reference rate. 2. The method of claim 1, wherein each of the service controllers comprises:
A monitor for detecting a service demand level of the corresponding master intelligent device in real time and outputting a credit value indicating the service demand level; And
And a control block for generating a local control signal for controlling the monitor based on a change in the operating environment and generating priority information for a request from the corresponding master intelligent element based on the credit value Features a system-on-chip. 5. The method of claim 4,
Wherein the local control signal includes an overflow value, a unit increase value, and a unit decrease value that are determined according to a change in the operating environment,
The monitor includes:
A first counter generating a first event signal activated at a period corresponding to the overflow value;
A service detector for generating a second event signal that is activated each time a service is provided to the corresponding master intelligent device based on a channel signal between the corresponding master intelligent device and the interconnect device; And
And a second counter that increases the credit value by the unit increase value every time the first event signal is activated and decreases the credit value by the unit decrease value every time the second event signal is activated Features a system-on-chip. 6. The apparatus of claim 5,
Wherein the request flow control unit controls the request flow of the corresponding master intelligent device by changing at least one of the overflow value, the unit increase value, and the unit decrease value based on a change in the operating environment. 6. The method of claim 5,
Wherein the local control signal further includes a still value provided when the operating environment changes,
And the second counter decrements the credit value by the still value. 5. The method of claim 4, wherein at least one of the service controllers comprises:
Further comprising a limiter for blocking a request flow between the corresponding master intelligent device and the interconnect device in response to a limit signal from the control block. 9. The apparatus of claim 8,
And activates the restriction signal when the credit value is smaller than the approval value and controls the request flow of the corresponding master intelligent device by changing the approval value based on a change in the operating environment. 9. The apparatus of claim 8,
A synchronizer for generating a synchronization limit signal in response to the limit signal;
A first logic gate for logically operating the synchronization limit signal and the valid signal from the corresponding master intelligent element to output a mask valid signal; And
And a second logic gate for outputting a mask ready signal by logically computing the synchronization restriction signal and the ready signal from the interconnecting device. 5. The apparatus of claim 4,
And sets a plurality of operation modes by dividing the range of the credit value and sets the values of the local control signal differently according to the operation modes to control the request flow of the corresponding master intelligent element On chip. The slave intelligent device according to claim 1,
A request queue storing a plurality of requests transmitted from the master intelligent elements via the interconnection device; And
And a scheduler for determining a service order for the stored requests based on priorities of each of the stored requests. 13. The method of claim 12,
Wherein the master intelligent elements comprise at least one real-time intelligent element,
Wherein the service controller corresponding to the real-time intelligent element generates an urgent signal indicating that urgent service is required. 14. The method of claim 13,
Wherein the scheduler of the slave intelligent device increases the priority of the requests generated from the real-time intelligent device among the requests stored in the request queue in response to the emergency signal. 13. The method of claim 12,
Wherein the master intelligent elements comprise at least one best effort intelligent element,
Wherein the slave intelligent element generates an external limiting signal based on a change in the operating environment,
Wherein the service controller corresponding to the best effort intelligent device blocks the request flow between the best effort port intelligent device and the interconnection device in response to the external limiting signal. 16. The method of claim 15,
Wherein the slave intelligent element activates the external limiting signal when requests larger than a reference number are stored in the request queue and are waiting for a service. 16. The method of claim 15,
Wherein the master intelligent elements further comprise at least one real-time intelligent element,
Wherein the slave intelligent element activates the external limiting signal in response to an urgent signal indicating that urgent service is required for the real-time intelligent element. 18. The method of claim 17,
Wherein the real-time intelligent device includes a display controller,
Wherein the best effort intelligent device comprises a processor. A method for controlling a system-on-chip, wherein a plurality of master intelligent elements each generating at least one slave intelligent element and requests for servicing the slave intelligent element are connected to the interconnecting device,
Generating at least one status signal indicative of a state of at least one of the slave intelligent element and the master intelligent elements;
Generating a global control signal indicating a change in the operating environment of the system-on-chip based on the status signal; And
And controlling the request flows of the master intelligent elements adaptively based on the global control signal. 1. A service controller for controlling a request flow of a master intelligent device for generating a request for requesting a service to a slave intelligent device,
A monitor for detecting a service requirement level of the master intelligent device in real time and outputting a credit value indicating the service demand level; And
And a control block for generating a local control signal for controlling the monitor based on a change in the operating environment and generating priority information for a request from the master intelligent element based on the credit value.

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