KR102021795B1 - Adaptive service controller, system on chip and method of controlling the same - Google Patents

Abstract

The system on chip includes at least one slave intelligent element, a plurality of master intelligent elements, an interconnect device and a plurality of service controllers. The master intelligent elements each generate requests for requesting service from the slave intelligent elements. An interconnect device is connected to the slave intelligent device and the master intelligent devices via respective channels, and performs an arbitration operation of the requests. Service controllers adaptively control the request flows of the master intelligent elements as the operating environment of the system on chip is changed.

Description

Adaptive service controller, system on chip and method of controlling the same}

The present invention relates to a semiconductor integrated circuit, and more particularly, to an adaptive service controller, a system on chip, and a system on chip control method for improving a quality of service of a plurality of master intelligent elements.

A system on chip (SOC) refers to a chip or a system integrated on the chip, in which various semiconductor components are integrated into one. The recent market trend is that the demand for existing application specific integrated circuits (ASICs) and application specific standard products (ASSPs) is gradually shifting to system-on-chip. In addition, the trend toward thinner, shorter and higher functionality of electronic devices is also driving the system-on-chip industry.

As the degree of integration of system-on-chip increases, more components are integrated on one chip, but the operating speed of the system-on-chip is not sufficiently increased. Limited operating speeds make it difficult to meet the service requirements of various master intelligent devices.

One object of the present invention for solving the above problems is to provide a service controller and a system on chip including the same that can adaptively control the request flow according to changes in the operating environment.

One object of the present invention is to provide a method for controlling a system on a chip capable of adaptively controlling a request flow according to a change in an operating environment.

In order to achieve the above object, the system on a chip according to an embodiment of the present invention is at least one slave intelligent device, a plurality of master intelligent devices, each of which generates requests for requesting service to the slave intelligent device, each An interconnection device connected to the slave intelligent element and the master intelligent elements via channels of the interconnection device, performing an arbitration operation of the requests, and adaptively requesting the master intelligent elements according to a change in an operating environment of a system on chip. A plurality of service controllers to control the flows.

The system on chip may further include a global controller generating a global control signal indicating a change in the operating environment based on at least one status signal. The service controllers can control respective request flows based on the global control signal.

The slave intelligent device may include a memory controller, and the master intelligent devices may include a modem and a display controller. The status signal may include a first status signal that is activated when an operating temperature of the memory controller is greater than a reference temperature, a second status signal that is activated when the modem has not received service from the slave intelligent device for a reference time, and the display. It may include at least one of the third state signal that is activated when the storage rate of the data stored in the data buffer of the controller is less than the reference rate.

Each of the service controllers may include: a monitor configured to detect a service demand level of the corresponding master intelligent element in real time and output a credit value indicating the service demand level; And a control block for generating a local control signal for controlling the monitor based on the change in the operating environment, and generating priority information for a request from the corresponding master intelligent element based on the credit value. Can be.

The local control signal may include an overflow value, a unit increase value, and a unit decrease value determined according to a change in the operating environment. The monitor is configured to provide a first counter to generate a first event signal that is activated at a period corresponding to the overflow value, and to the corresponding master intelligent element based on a channel signal between the corresponding master intelligent element and the interconnect device. A service detector for generating a second event signal that is activated each time a service is provided, and incrementing the credit value by the unit increment value each time the first event signal is activated, and when the second event signal is activated Each counter may include a second counter for decreasing the credit value by the unit decrease value.

The control block may control the request flow of the corresponding master intelligent element by changing at least one of the overflow value, the unit increase value, and the unit decrease value based on a change in the operating environment.

The control block facilitates the request flow of the corresponding master intelligent element by decreasing the overflow value, increasing the unit increasing value, or decreasing the unit decreasing value, increasing the overflow value, or increasing the unit increasing value. Reducing or increasing the unit reduction value can suppress the request flow of the corresponding master intelligent element.

The local control signal may further include a still value provided when the operating environment changes. The second counter may decrease the credit value by the still value.

At least one of the service controllers may further include a limiter that blocks a request flow between the corresponding master intelligent element and the interconnect device in response to a limit signal from the control block.

The control block may control the request flow of the corresponding master intelligent element by activating the limit signal when the credit value is less than the grant value and changing the grant value based on a change in the operating environment.

The limiter may include a synchronizer for generating a sync limit signal in response to the limit signal, and a first logic gate configured to logically operate a valid signal from the sync limit signal and the corresponding master intelligent element to output a mask valid signal. And a second logic gate configured to logically operate the sync limit signal and the ready signal from the interconnect device to output a mask ready signal.

The control block may control a request flow of the corresponding master intelligent element by dividing the credit value range to set a plurality of operation modes and differently setting values of the local control signal according to the operation modes. Can be. The operating modes,

And a promotion mode in which the credit value is larger than an upper boundary value, a default mode in which the credit value is smaller than the upper boundary value and larger than a lower boundary value, and a demotion mode in which the credit value is smaller than the lower boundary value.

The control block is based on the operating modes such that a larger bandwidth is allowed in the promotion mode than the default mode for the corresponding master intelligent element and a larger bandwidth is allowed in the default mode than the demotion mode. The values of the local control signal can be set.

The slave intelligent element may include a request queue for storing a plurality of requests delivered from the master intelligent elements via the interconnect device, and a service for the stored requests based on respective priorities of the stored requests. It may include a scheduler for determining the order.

The master intelligent elements include at least one real-time intelligent element, and the service controller corresponding to the real-time intelligent element may generate an emergency signal indicating that an urgent service is required.

The scheduler of the slave intelligent device may increase the priority of requests generated from the real-time intelligent device among the requests stored in the request queue in response to the emergency signal.

The system on chip may further include a transmission line connected point-to-point between the service controller corresponding to the real-time intelligent device and the slave intelligent device. The emergency signal may be transmitted directly from the service controller corresponding to the real-time intelligent device to the slave intelligent device via the transmission line.

The master intelligent elements include at least one best effort intelligent element, the slave intelligent element generates an external limit signal based on a change in the operating environment, and the service controller corresponding to the best effort intelligent element The request flow between the best effort intelligent element and the interconnect device may be blocked in response to the external limit signal.

The slave intelligent device may activate the external limit signal when more requests than the reference number are stored in the request queue and are waiting for service.

The master intelligent devices may further include at least one real-time intelligent device, and the slave intelligent device may activate the external limit signal in response to an emergency signal indicating that an urgent service is required for the real-time intelligent device.

The real-time intelligent device may include a display controller, and the best effort intelligent device may include a processor.

The system on chip may further include a transmission line connected point-to-point between the service controller corresponding to the best effort intelligent element and the slave intelligent element. The external limit signal may be transmitted directly from the slave intelligent element to the service controller corresponding to the best effort intelligent element via the transmission line.

In order to achieve the above object, in accordance with embodiments of the present invention, at least one slave intelligent device and a plurality of master intelligent devices each generating requests for requesting service from the slave intelligent device are connected to an interconnect device. A method of controlling a chip is provided. The method includes generating at least one state signal indicative of a state of at least one of the slave intelligent element and the master intelligent element, a global control signal indicative of a change in the operating environment of the system on chip based on the state signal. And generating adaptive control of the request flows of the master intelligent elements based on the global control signal.

In order to achieve the above object, according to embodiments of the present invention, a service controller is provided for controlling a request flow of a master intelligent device that generates a request for requesting a service from a slave intelligent device.

The service controller detects the service demand level of the master intelligent element in real time and outputs a credit value indicating the service demand level, and generates a local control signal for controlling the monitor based on a change in operating environment. And a control block for generating priority information on a request from the master intelligent element based on the credit value.

The system-on-chip and method for controlling the system-on-chip according to embodiments of the present invention can improve the quality of service (QOS) by adaptively controlling the request flows of the master intelligent elements according to the change of the operating environment. have.

In the control method of the system on chip and the system on chip according to the embodiments of the present invention, the control conditions of the request flows may be independently set for each master intelligent element using a plurality of service controllers assigned to the respective master intelligent elements. Complex scenarios according to changes in the operating environment can be easily implemented.

1 is a block diagram illustrating a system in accordance with embodiments of the present invention.
2 is a flowchart illustrating a control method of a system according to embodiments of the present disclosure.
3 is a block diagram illustrating a service controller according to embodiments of the present invention.
4 is a view for explaining an example of a method for detecting a service request level of a master intelligent element.
FIG. 5 is a block diagram illustrating an embodiment of a monitor included in the service controller of FIG. 3.
6 is a diagram illustrating a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
7 is a view for explaining an example of the operation of the monitor of FIG.
8 is a diagram illustrating an example of a transaction performed by a system according to embodiments of the present invention.
9 is a block diagram illustrating a limiter included in the service controller of FIG. 3.
FIG. 10 is a circuit diagram illustrating an example of a limiter included in the service controller of FIG. 3.
11 is a timing diagram illustrating an operation of the limiter of FIG. 10.
FIG. 12 is a circuit diagram illustrating another example of a limiter included in the service controller of FIG. 3.
FIG. 13 is a timing diagram illustrating an operation of the restrictor of FIG. 12.
14 is a diagram illustrating a method for controlling a system on a chip according to an embodiment of the present invention.
15 is a diagram illustrating a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
FIG. 16 illustrates an example of an operation of the monitor of FIG. 5 according to the method of FIG. 15.
17 is a block diagram illustrating a system according to embodiments of the present invention.
18 is a block diagram illustrating an example of a service controller included in the system of FIG. 17.
19 is a diagram illustrating a method of controlling a request flow based on a credit value according to an embodiment of the present invention.
20 is a diagram illustrating a method for generating an emergency signal according to an embodiment of the present invention.
FIG. 21 is a block diagram illustrating an example of a service controller included in the system of FIG. 17.
FIG. 22 is a diagram illustrating an example of slave intelligent elements included in the system of FIG. 17.
FIG. 23 is a diagram illustrating an example of a request structure and an emergency signal stored in the slave intelligent device of FIG. 22.
24 is a block diagram illustrating an example in which a system on chip according to embodiments of the present invention is applied to an electronic device.
FIG. 25 is a block diagram illustrating an example of an interface used in the electronic device of FIG. 24.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a system in accordance with embodiments of the present invention. The system referred to below may include a system on chip (SOC) in which various semiconductor components are integrated on one chip.

Referring to FIG. 1, the system 1000 may include slave intelligent elements (IP) SLV1 and SLV2 (301 and 302) and master intelligent elements (MST1, MST2 and MST3) ( 101, 102, 103, service controllers QC1, QC2, QC3 501, 502, 503, and interconnect device 10. According to an embodiment, the system 1000 may further include a global controller 30.

Master intelligent elements 101, 102, 103 and slave intelligent elements 301, 302 may be referred to as devices, respectively, and may be referred to as IP cores or IP blocks. According to an embodiment, each of the master intelligent elements 101, 102, 103 and slave intelligent elements 301, 302 may be part of a logic unit, cell, or chip.

The plurality of master intelligent elements 101, 102, 103 respectively generate requests for requesting service from at least one slave intelligent element 301, 302. The at least one intelligent element 301, 302 may be used as a common resource of the plurality of master intelligent elements 101, 102, 103.

The interconnect device 10 is connected to the slave intelligent devices 301, 302 and the master intelligent devices 101, 102, 103 via respective channels. One channel may be implemented between one intelligent element and the interconnect device 10, and a plurality of channels may be implemented. For example, when the slave intelligent devices 301 and 302 include a memory controller, a read channel and a write channel may be implemented between one intelligent device and the interconnect device 10, respectively. Interconnect device 10 performs an arbitration operation of requests from master intelligent elements 101, 102, 103. The interconnect device 10 may include at least one arbiter for the arbitration operation.

The plurality of service controllers 501, 502, 503 adaptively control the request flows of the master intelligent elements 101, 102, 103 according to a change in the operating environment of the system 1000.

The change in the operating environment may be provided using one or more status signals ST1, ST2, ST3. For example, the second slave intelligent element 302 may be a memory controller, the second master intelligent element 102 may be a modem, and the third master intelligent element 103 may be a display controller.

The memory controller 302 may generate the first status signal ST1 that is activated when the operating temperature is greater than the reference temperature. The memory controller 302 may include a temperature sensor for detecting an operating temperature. In general, the memory controller 302 is designed to reduce the operation speed in order to ensure the reliability of the operation when the operating temperature rises above a certain level. When the operation speed of the memory controller 302 is reduced, a scenario that can guarantee the bandwidth of the real-time intelligent device while totally suppressing the request flows of the master intelligent devices using the memory controller 302 as a shared resource is required. do.

The modem 102 may generate a second status signal ST2 that is activated when no service is received from the slave intelligent device 102 for a reference time or more. In general, if the modem 102 is not provided with the service within a certain time due to the limitation of the communication protocol with the external device, the already issued request is invalidated. If the operating environment changes so that service to the modem 102 is severely delayed, a scenario is required that suppresses the request flow of other master intelligent elements so that the modem 102 can be guaranteed a constant latency.

The display controller 103 may generate the third status signal ST3 that is activated when the storage rate of the data stored in the internal data buffer is smaller than the reference rate. The display controller 103 corresponds to a real-time intelligent device that regularly requests display data. If the display data is not served properly (in time), the user will directly recognize it as underperforming the product. In this case, a scenario is required in which the display controller 103 suppresses the request flow of other master intelligent elements so as to guarantee a constant bandwidth.

The above-mentioned scenarios may be variously determined according to an operating characteristic of the system 1000, a user's selection, and the like. Examples of scenarios based on the transformation of the operating environment according to embodiments of the present invention are described below with reference to FIG. 14.

In one embodiment, as shown in FIG. 1, the system 1000 generates a global control signal GCON that represents a change in the operating environment based on one or more status signals ST1, ST2, ST3. It may further include a controller (30). In this case, the service controllers 501, 502, and 503 may control respective request flows based on the global control signal GCON.

In another embodiment, global controller 30 may be omitted and status signals ST1, ST2, ST3 may be provided directly to service controllers 501, 502, 503. In this case, the service controllers 501, 502, and 503 may control the respective request flows based on the respective status signals ST1, ST2, ST3, or a combination thereof.

The number of master intelligent elements and slave intelligent elements shown in FIG. 1 may be variously changed. Depending on the operating characteristics of the master intelligent device, the service controllers may have different configurations, and some service controllers may be omitted.

2 is a flowchart illustrating a system control method according to embodiments of the present invention.

FIG. 2 illustrates a control method of a system in which at least one slave intelligent device and a plurality of master intelligent devices each generating requests for requesting service from the slave intelligent device are connected to the interconnect device.

1 and 2, at least one of the slave intelligent elements 301, 302 and the master intelligent elements 101, 102, 103 are one or more state signals ST1, ST2, ST3 indicating their state. (Step S100). The global controller 30 generates a global control signal GCON indicating a change in the operating environment of the system 1000 based on the state signals ST1, ST2, ST3 (step S300). The service controllers 501, 502, 503 adaptively control the request flows of the master intelligent elements 101, 102, 103 based on the global control signal GCON (step S500).

Hereinafter, various embodiments of the control method of the system of FIG. 1 and the system of FIG. 2 will be described with reference to FIGS. 3 to 23. Only components necessary for the description of the embodiments may be illustrated in FIGS. 3 to 23, and redundant descriptions may be omitted.

3 is a block diagram illustrating a service controller according to embodiments of the present invention.

3 shows one service controller 500a corresponding to one master intelligent element 100. Each of the plurality of service controllers 501, 502, and 503 of FIG. 1 may have a configuration as illustrated in FIG. 3. As shown in FIG. 3, the service controller 500a may be coupled to a channel between the corresponding master intelligent element 100 and the interconnect device 10. In another embodiment, the service controller 500a may be included inside the master intelligence element 100 as part of the master intelligence element 100.

Referring to FIG. 3, the service controller 500a may include a limiter 510, a monitor 520, and a control block 530.

The monitor 520 detects the service requirement level of the corresponding master intelligent element 100 in real time and outputs a credit value CRD indicating the service requirement level.

The service demand level may be detected by bandwidth, outstanding count value, and / or average latency. Bandwidth represents the amount of data transmitted or serviced at a given time. As described below, the credit value CRD corresponds to the bandwidth. The outstand count value is the number of requests that have already been issued from the master intelligent device but have not yet completed. The latency represents a time interval from when the master intelligent device requests a service to the slave intelligent device to when the requested service is completed. The monitor of FIG. 3 may be implemented to further provide at least one of bandwidth, outstand count value and average latency as well as the credit value CRD.

The control block 530 generates a local control signal LCON for controlling the monitor 520 based on the change in the operating environment of the system. The change in the operating environment may be provided as the global control signal GCON as described with reference to FIG. 1 or may be provided as the status signals ST1, ST2, ST3. The control block 530 may also generate priority information (PRT) for the request from the corresponding master intelligent element 100 based on the credit value CRD. Priority information (PRT) may be provided to the interconnect device 10 and used as the basis of the arbitration operation. At least a portion of the control block 530 may be implemented as a special function register having a configuration that performs a predetermined process sequence in response to stored values and input values.

The limiter 510 blocks the request flow between the corresponding master intelligent element 100 and the interconnect device 10 in response to the limit signal LMT from the control block 530. The limiter 510 may be omitted depending on the operating characteristics of the corresponding master intelligent element 100.

4 is a view for explaining an example of a method for detecting a service request level of a master intelligent element.

Depending on the operation characteristics of the master intelligent device, the service requirement level of the master intelligent device may be expressed as a bandwidth. Bandwidth represents the amount of data transmitted or serviced at a given time. For example, a master intelligent device such as a display controller may receive data from a slave intelligent device such as a memory controller connected through an interconnect device, store data in a data buffer, and consume the stored data to perform its own functions. Can be.

In FIG. 4, the data occupancy state of the line buffer included in the master intelligent element is shown by hatching. The occupancy state of the data may be represented by a line buffer pointer LBP. When data is serviced from the slave intelligent device (DATA IN), the line buffer pointer LBP increases in the full direction, and when the master intelligent device consumes data (DATA OUT), the line buffer pointer LBP is empty. Decrease in the direction of.

As the line buffer pointer LBP increases, a low priority may be given, and as the line buffer pointer LBP decreases, a high priority may be given. That is, the higher the priority, the higher the bandwidth required. The relationship between the line buffer pointer LBP and the priority may be set according to the overall scenario of the system. For example, an area between the full and the empty areas of the line buffer pointer LBP may be divided into a plurality of areas to sequentially assign the priority to each area.

FIG. 5 is a block diagram illustrating an embodiment of a monitor included in the service controller of FIG. 3.

Referring to FIG. 5, the monitor 520a may be implemented to include a first counter (CNT1) 521, a second counter (CNT2) 523, and a service detector (SDET) 525.

The first counter 521 generates a first event signal CEV that is activated at a period corresponding to the overflow value OV. For example, the first counter 521 counts a cycle of the clock signal CLK, and the first event signal CEV is a pulse signal that is activated whenever the counted value reaches the overflow value OV. Can be. The clock signal CLK may be an operating clock signal of the corresponding master intelligent device 100.

The service detector 525 is a second activated whenever a service is provided to the corresponding master intelligent element 100 based on the channel signal CHN between the corresponding master intelligent element 100 and the interconnect device 10. Generates an event signal SEV.

The second counter 523 increases the credit value CRD by the unit increment value INC every time the first event signal CEV is activated, and decreases the unit value each time the second event signal SEV is activated. Decreases the credit value (CRD) by (DEC). The second counter 523 may also decrease the credit value CRD by the still value STL provided from the control block 530. The control block 530 may provide the still value STL only once when the change in the operating environment occurs to decrease the credit value CRD once.

As such, the current bandwidth requirement level of the corresponding master intelligent element 100 may be represented by a credit value CRD. As the credit value CRD increases, a relatively large bandwidth is required, and as the credit value CRD decreases, a relatively small bandwidth may be required.

The overflow value OV, unit increase value INC, unit decrease value DEC, and still value STL may be included in the local control signal LCON from the control block 530. The overflow value OV, unit increment value INC, unit decrease value DEC, and still value STL may be determined according to the overall scenario of the system. The control block 530 may change the overflow value OV, the unit increase value INC, the unit decrease value DEC, and the still value STL according to the change of the operating environment. For example, an overflow value (OV), a unit increase value (INC), a unit decrease value (DEC), and a still value (STL) according to a change in an operating environment are provided during an initialization process of the system 1000 to provide a control block ( 530 may be stored. Considering the operating characteristics of the master intelligent elements 101, 102, 103, the user may determine values for each master intelligent element. Through such a distributed control scheme for each master intelligent device, complex scenarios of the system 1000 may be easily and efficiently implemented.

6 is a view for explaining a method of controlling a request flow based on a credit value according to an embodiment of the present invention, and FIG. 7 is a view for explaining an example of an operation of the monitor of FIG. 5.

6 and 7, each time the first event signal CEV is activated, the credit value CRD increases in the direction of the maximum value MAX, and each time the second event signal SEV is activated, the credit value ( CRD) decreases in the direction of the minimum value MIN. The activation period of the first event signal CEV corresponds to the target bandwidth and the average activation period of the second event signal SEV corresponds to the real-time bandwidth currently being serviced. As shown in FIG. 7, when the real time bandwidth is smaller than the target bandwidth, the credit value CRD gradually increases, and when the real time bandwidth is larger than the target bandwidth, the credit value CRD gradually decreases.

The control block 530 illustrated in FIG. 3 may give a higher priority as the credit value CRD is larger and give a lower priority as the credit value CRD is smaller. In general, the interconnect device 10 is designed to promote the request flow as the master intelligent element with a higher priority and to suppress the request flow as the master intelligent element with a lower priority.

The control block 530 may change the corresponding master intelligent element (i) by changing at least one of the overflow value OV, the unit increment value INC, and the unit decrease value DEC based on a change in the operating environment of the system 1000. 100 can control the request flow. For example, the control block 530 may control the request flow of the corresponding master intelligent element 100 by decreasing the overflow value OV, increasing the unit increasing value INC, or decreasing the unit decreasing value DEC. It can be promoted. The control block 530 also suppresses the request flow of the corresponding master intelligent element 100 by increasing the overflow value OV, decreasing the unit increasing value INC, or increasing the unit decreasing value DEC. can do.

As described above with reference to FIG. 3, the at least one service controller 500a is configured between the corresponding master intelligent element 100 and the interconnect device 10 in response to a limit signal LMT from the control block 530. It may further include a limiter 510 to block the request flow of. Embodiments of the limiter 510 are described below with reference to FIGS. 9 to 13.

If the service controller 500a includes a limiter 510, the control block 530 may generate a limit signal LMT that is activated when the credit value CRD is less than the grant value GRN. The control block 530 may control the request flow of the corresponding master intelligent element 100 by changing the grant value GRN based on a change in the operating environment of the system. That is, the larger the grant value GRN is set to suppress the request flow of the corresponding master intelligent element 100, and the lower the grant value GRN is set to further promote the request flow of the corresponding master intelligent element 100. Can be.

8 is a diagram illustrating an example of a transaction performed by a system according to embodiments of the present invention.

8 illustrates an example of a read transaction according to an advanced extensible interface (AXI) protocol for convenience of description. The AXI protocol employs a handshake mechanism that uses valid signals (ARVALID, RVALID) and ready signals (ARREADY, RREADY).

According to the handshake method, one side of the master interface and the slave interface activates the valid signal during signal transmission, and the other side activates the ready signal when ready for reception. Sampling of the transmission signal is performed in synchronization with the rising edge of the global clock signal ACLK at both the master interface and the slave interface. Thus, valid signal transmission occurs only when both the valid signal and the corresponding ready signal are activated on the rising edge of the global clock signal ACLK.

As shown in FIG. 8, when the master intelligent element 100 corresponding to the master interface activates the request valid signal ARVALID during signal transmission, and the interconnect device 10 corresponding to the slave interface is ready for reception. Activates the request ready signal ARREADY. Similarly, the interconnect device 10 activates the service valid signal RVALID upon signal transmission, and the master intelligent element 100 activates the service ready signal RREADY when ready for reception.

In FIG. 8, time points representing the rising edges of the global clock signal ACLK are represented by T0 to T13. The master interface, for example, the master intelligent element 100 transmits a read request signal (ARADDR) to a slave interface, for example, the interconnect device 10, together with a read valid signal (corresponding to the request request signal). ARVALID). At time T2 both the valid signal ARVALID and the ready signal RREADY are activated so that the transmission of the read request signal ARADDR is actually performed. However, from the viewpoint of the master interface, the time T1 may be determined as the service request time regardless of whether the ready signal RREADY of the slave interface is activated, that is, whether the actual signal transmission is successful.

Data (D (A0), D (A1), D (A2), D (A3)) is transmitted from the interconnect device 10 to the master intelligent element 100 by a burst transmission method as a response to the read request. do. The interconnect device 10 activates the RLAST signal corresponding to the service completion signal with the transmission of the last data D (A3), and time T13 is determined as the service completion time.

As such, the service controller 500a of FIG. 3 is a request signal between the master intelligent element 100 and the interconnect device 10 among the channel signals CHN between the master intelligent element 100 and the interconnect device 10. The service completion time may be determined based on the service request time, that is, the request issuance time and the service signals RVALID, RREADY, and RLAST based on the ARVALID and ARREADY.

Latency (LAT) represents the time interval from the time when the master intelligent device requests the service to the slave intelligent device to the completion of the requested service, for example, the latency (LAT) is expressed as the number of cycles of the clock signal, etc. Can be.

9 is a block diagram illustrating a limiter included in the service controller of FIG. 3.

Referring to FIG. 9, a limiter 510 may include a synchronizer (SYNC) 512 and a mask unit (MASK) 515.

The synchronizer 512 generates a synchronized limit signal SMSK based on the limit signal LMT from the control block 530. The mask unit 515 blocks a request from the corresponding master intelligent element 100 in response to the synchronization limit signal SMSK.

The synchronizer 512 serves to control the transition time of the limit signal LMT in order to prevent an error in the handshake signal transmission between the master intelligent element 100 and the interconnect device 10.

FIG. 10 is a circuit diagram illustrating an example of a limiter included in the service controller of FIG. 3.

Referring to FIG. 10, the limiter 510a may include a flip-flop (FF) 512a and a mask unit 515a corresponding to a synchronizer.

The flip-flop 512a generates the sync limit signal SMSK based on the limit signal LMT and the inverted global clock signal ACLKb from the control block 530. The flip-flop 512a samples the limit signal LMT in response to the rising edge of the inverted global clock signal ACLKb to generate the sync limit signal SMSK. The rising edge of the inverted global clock signal ACLKb corresponds to the falling edge of the global clock signal ACLK. As a result, the transition time of the synchronization limit signal SMSK is synchronized to the falling edge of the global clock signal ACLK.

The mask unit 515a blocks a request from the corresponding master intelligent element 10 in response to the synchronization limit signal SMSK. The mask unit 515a may include a first logic gate 516 and a second logic gate 517. The first logic gate 516 may perform a logic operation on the synchronization limit signal SMSK and the valid signal VALID from the corresponding master intelligent element 100 to output a masked valid signal MVALID. The second logic gate 517 logically operates the sync limit signal SMSK and the ready signal READY from the interconnect device 10 to output a masked ready signal MREADY.

For example, when the synchronization limit signal SMSK is deactivated to a logic low level, the mask unit 515a may have a mask valid signal MVALID of the same logic level as the valid signal VALID and the ready signal READY, respectively. And a mask ready signal MREADY. When the sync limit signal SMSK is activated at a logic high level, the mask unit 515a is a mask valid signal deactivated at a logic low level regardless of the logic levels of the valid signal VALID and the ready signal READY. MVALID) and a mask ready signal (MREADY) are output.

11 is a timing diagram illustrating an operation of the limiter of FIG. 10.

As described with reference to FIG. 8, the master intelligent element 100 activates the valid signal VALID upon transmission of the request signal, and the interconnect device 10 corresponding to the slave is ready for reception when the ready signal READ is received. ) Is activated. By the mask unit 515a of FIG. 10, the interconnect device 10 receives the mask valid signal MVALID and the master intelligent element 100 receives the mask ready signal MREADY. In other words, the master intelligent device 100 determines that valid signal transmission has been made when both the valid signal VALID and the mask ready signal MREADY are activated on the rising edge of the global clock signal ACLK, and the interconnection device 10 determines that valid signal transmission is performed when both the mask valid signal MVALID and the ready signal READY are activated on the rising edge of the global clock signal ACLK.

Due to the discrepancy of the criterion, even though the effective signal transmission is not actually performed, only one of the master intelligent element 100 and the interconnection device 10 may determine that the effective signal transmission is performed, and thus an interface error may occur.

In order to prevent such an error, the limiter 510a of FIG. 10 performs a function of synchronizing the start time and the end time of the masked interval tMSK with the falling edge of the global clock signal ACLK. That is, regardless of the transition time of the limit signal LMT, the transition time of the synchronization limit signal SMSK is synchronized with the falling edge of the global clock signal ACLK. Thus, the start and end times of masking can be clearly separated from the sampling point of the master intelligent element 100 and the interconnect device 10, that is, the rising edge of the global clock signal ACLK.

At sampling points SP1 and SP3 that do not belong to the mask period, the mask valid signal MVALID and the mask ready signal MREADY have the same logic level as the valid signal VALID and the ready signal READY, respectively. The handshake is performed and valid signal transmission is made at sampling points SP1 and SP3. On the other hand, at the sampling point SP2 belonging to the mask period, even though both the valid signal VALID and the ready signal READY are activated, the master intelligent device 100 and the interconnection device 10 are respectively disabled mask ready signals. Based on the MREADY and the mask valid signal MVALID, it is determined that no valid signal transmission is performed.

FIG. 12 is a circuit diagram illustrating another example of a limiter included in the service controller of FIG. 3.

Referring to FIG. 12, the limiter 510b may include a synchronizer 512b and a mask unit 515b.

The synchronizer 512b generates the synchronization limit signal SMSKb based on the limit signal LMT, the global clock signal ACLK, the valid signal VALID, and the mask ready signal MREADY from the control block 530. do. In contrast to the embodiment of FIG. 10, the logic low level of the sync limit signal SMSKb may correspond to an activation level. The operation of the synchronizer 512b will be described later with reference to FIG. 13.

The mask unit 515b blocks a request from the corresponding master intelligent element 100 in response to the synchronization limit signal SMSKb. The mask unit 515b may include a first logic gate 518 and a second logic gate 519. The first logic gate 518 logically operates the validity limit signal SMSKb and a valid signal VALID from the corresponding master intelligent element 100, and outputs a masked valid signal MVALID. The second logic gate 519 performs a logic operation on the synchronization limit signal SMSKb and the ready signal READY from the interconnect device 10 to output a masked ready signal MREADY.

For example, when the synchronization limit signal SMSKb is deactivated to a logic high level, the mask unit 515b may have a mask valid signal MVALID of the same logic level as the valid signal VALID and the ready signal READY, respectively. And a mask ready signal MREADY. When the sync limit signal SMSKb is activated at a logic low level, the mask unit 515b may be configured to be a mask valid signal deactivated at a logic low level regardless of the logic levels of the valid signal VALID and the ready signal READY. MVALID) and a mask ready signal (MREADY) are output.

FIG. 13 is a timing diagram illustrating an operation of the restrictor of FIG. 12.

As described with reference to FIG. 8, the master intelligent element 100 activates the valid signal VALID upon transmission of the request signal, and the interconnect device 10 corresponding to the slave is ready for reception when the ready signal READ is received. ) Is activated. By the mask unit 515b of FIG. 12, the interconnect device 10 receives the mask valid signal MVALID and the master intelligent element 100 receives the mask ready signal MREADY. In other words, the master intelligent device 100 determines that valid signal transmission has been made when both the valid signal VALID and the mask ready signal MREADY are activated on the rising edge of the global clock signal ACLK, and the interconnection device 10 determines that valid signal transmission is performed when both the mask valid signal MVALID and the ready signal READY are activated on the rising edge of the global clock signal ACLK.

Due to the discrepancy of the criterion, even though the effective signal transmission is not actually performed, only one of the master intelligent element 100 and the interconnection device 10 may determine that the effective signal transmission is performed, and thus an interface error may occur.

In order to prevent such an error, the synchronizer 512b of FIG. 12 performs a function of synchronizing a start time of a masked interval tMSK immediately after one valid transmission is made. That is, the synchronization limit signal SMSKb is activated to a logic low level immediately after the sampling point SP1 in which the limit signal LMT is activated and valid transmission is performed. Meanwhile, the synchronizer 512b synchronizes the end time of the mask period tMSK with the deactivation timing of the limit signal LMT.

At sampling points SP1 and SP5 not belonging to the mask section, the mask valid signal MVALID and the mask ready signal MREADY have the same logic level as the valid signal VALID and the ready signal READY, respectively. The shake is performed, and valid signal transmission is performed at the sampling points SP1 and SP5. On the other hand, at the sampling points SP2, SP3, and SP4 belonging to the mask period, even though both the valid signal VALID and the ready signal READY are activated, the master intelligent element 100 and the interconnection device 10 are deactivated, respectively. Based on the mask ready signal MREADY and the mask valid signal MVALID, it is determined that no effective signal transmission is performed.

14 is a diagram illustrating a method for controlling a system on a chip according to an embodiment of the present invention.

14 illustrates scenarios for controlling the request flow of the system for example cases. The system includes at least a processor, a modem, and a display controller as master intelligent elements, which can issue requests to a memory controller corresponding to slave intelligent elements of a common resource, respectively, requesting service. .

The master intelligent devices may be classified into hard realtime IP devices, soft realtime IP devices, and best effort IP devices according to their types.

Hard real-time intelligent devices, such as display intelligent devices, are intelligent devices that consistently use data of a constant bandwidth and underrun of the data buffer if the required bandwidth is not guaranteed. By ensuring a constant bandwidth, these intelligent devices can fill the data buffers sufficiently and control the request flow on their own, generating requests only as they consume data.

On the other hand, in order to reduce the manufacturing cost of the system, an external modem chip (external modem chip) may be used to share the memory of the system on chip. Such an external modem chip has an error when an average latency requirement is not satisfied. In the case of a modem chip, a request comes into the system on chip only when communication occurs, and there are various types of modem chips, so it is difficult to determine the bandwidth requirements of the modem chip.

Like a video codec, a soft real-time intelligent device has a frame rate (e.g., 30, 60 per sec) and has several frame buffers with slightly different bandwidth requirements depending on the characteristics of the frame. It is an intelligent device that guarantees an average decode / encode time. Such an intelligent device has a characteristic of passing the decode / encode to the next frame as soon as possible without controlling the request flow, but has a dependency between data so that many requests are not made at once. Thus, while the constant bandwidth and / or latency is guaranteed, the operation speed satisfies the frame rate, but if the latency exceeds the threshold, the decode / encode time increases rapidly, resulting in a decrease in the operation speed.

Best-effort intelligent devices are intelligent devices that generate requests continuously without controlling the request flow, such as a 2D, two-dimensional and / or three dimensional graphics engine, or a direct memory access controller (DMAC). These intelligent devices must do flow control. It is desirable to provide as much service as possible for slave intelligent devices, such as memory controllers, without restricting the request flow, unless high priority intelligent devices are in an emergency. However, if an urgent situation occurs in a high priority intelligent device, the request of the best effort intelligent device should be limited to a level that allows the slave intelligent device to relax so that the high priority intelligent device can be released from the emergency situation.

On the other hand, latency oriented IP devices such as CPUs do not have the required bandwidth and bandwidth requirements vary greatly depending on the situation, but performance is directly affected by the average latency. Since these intelligent devices are difficult to define bandwidth requirements, they should be given priority to service the system according to average latency.

The first case CASE1 of FIG. 14 shows a default case in which the system operates in a normal state. Processors are typical best-effort intelligent devices and display controllers are typical real-time intelligent devices. The above-described overflow value OV, acceptance value GRN, and unit reduction value DEC may be appropriately set according to operating characteristics of the master intelligent elements. The aforementioned unit increment value INC may be set to a value of 1 for all cases and all master intelligent elements. According to an embodiment, the unit increment value INC may also be set to a different value according to the scenario and the operation characteristics of the master intelligent device. The overflow value OV may correspond to the number of cycles of the operation clock, for example, the cycle period of the operation clock may be 1 ns (nano second). The first case CASE1 of FIG. 1 may correspond to a case in which the display controller operates at 640 MB / sec and the processor operates at 2560 MB / sec.

The second case CASE2 may correspond to a case in which the third state signal ST3 described with reference to FIG. 1 is activated. That is, the second case CASE2 may be a case in which an urgent service for the display controller is required because the storage rate of the data stored in the data buffer of the display controller is smaller than the reference rate. In this case, the overflow value of the processor may be set larger than the default case to suppress the request flow of the processor, and the overflow value of the display controller may be set smaller than the default case to facilitate the request flow of the display controller. In addition, when the operating environment changes from the first case (CASE1) to the second case (CASE2), the request flow of the processor can be quickly suppressed by reducing the credit value of the processor (STEAL) once. The second case (CASE2) may correspond to a case where the display controller operates at 1280 MB / sec and the processor operates at 1920 MB / sec.

The third case CASE3 may correspond to a case in which the first state signal ST1 described with reference to FIG. 1 is activated. That is, the third case CASE3 may be a case where the operating speed of the memory controller is reduced because the operating temperature of the memory controller is greater than the reference temperature. In this case, set the overflow value of the processor corresponding to the best effort intelligent element larger than the default case to suppress the request flow of the processor, and set the overflow value of the display controller corresponding to the real-time intelligent element smaller than the default case. Maintain the bandwidth of the display controller. On the other hand, the request flow can be suppressed as a whole by setting the unit reduction value DEC for all master intelligent devices to be larger than the default case. In addition, when the operating environment changes from the first case (CASE1) to the third case (CASE3), the request flow of the processor can be quickly suppressed by reducing the credit value of the processor once. The third case (CASE3) may correspond to a case in which the display controller operates at 640 MB / sec and the processor operates at 960 MB / sec.

The fourth case CASE4 may correspond to a case where the first state signal ST1 and the third state signal ST3 described with reference to FIG. 1 are activated together. That is, in the fourth case (CASE4), the storage rate of the data stored in the data buffer of the display controller is smaller than the reference rate, so that urgent service for the display controller is required, and the operation temperature of the memory controller is greater than the reference temperature, thereby operating the memory controller. It may be the case that the speed is reduced. In this case, set the overflow value of the processor corresponding to the best effort intelligent element larger than the default case to suppress the request flow of the processor, and set the overflow value of the display controller corresponding to the real-time intelligent element smaller than the default case. Maintain the bandwidth of the display controller. Meanwhile, the unit reduction value DEC may be set larger than the default value for the processor and the modem to suppress the request flow to ensure the bandwidth of the display controller. In addition, when the operating environment changes from the first case (CASE1), the second case (CASE2), or the third case (CASE3) to the fourth case (CASE4), the request of the processor is reduced once by reducing the credit value of the processor. The flow can be quickly suppressed. The fourth case (CASE4) may correspond to a case in which the display controller operates at 1280 MB / sec and the processor operates at 320 MB / sec.

The fifth case CASE5 may correspond to a case in which the second state signal ST2 described with reference to FIG. 1 is activated. That is, the fifth case (CASE5) may be a case in which the modem does not receive a service from the memory controller for more than a reference time. In this case, the request flow of the processor may be blocked by setting the overflow value of the processor corresponding to the best effort intelligent element to infinity. Setting the overflow value of the processor to infinity may be to activate the limit signal LMT regardless of the above-described credit value CRD. The request flow between the processor and the interconnect device can be blocked by activating the limit signal LMT in response to the global control signal GCON representing the fifth case CASE5. In addition, when the operating environment changes from the first case (CASE1) to the fifth case (CASE5), the credit value of the processor may be reduced once.

As such, the system on chip and the method for controlling the system on chip according to the embodiments of the present invention may improve the quality of service by adaptively controlling the request flows of the master intelligent elements according to a change in the operating environment. In addition, since a control condition of request flows can be independently set for each master intelligent element using a plurality of service controllers assigned to each master intelligent element, a complicated scenario according to a change in an operating environment can be easily implemented.

FIG. 15 is a diagram illustrating a method of controlling a request flow based on a credit value according to an embodiment of the present invention, and FIG. 16 is a diagram illustrating an example of an operation of the monitor of FIG. 5 according to the method of FIG. 15. to be.

As described above, each time the first event signal CEV is activated, the credit value CRD increases in the direction of the maximum value MAX, and each time the second event signal SEV is activated, the credit value CRD is increased. Decrease in the direction of the minimum value (MIN). The control block 530 may give a higher priority as the credit value CRD is larger and give a lower priority as the credit value CRD is smaller.

15 and 16, the control block 530 sets a plurality of operation modes by dividing a range of a credit value CRD, and values OV and INC of the local control signal LCON according to the operation modes. , DEC) can be set differently to control the request flow of the corresponding master intelligent element.

For example, the operation modes may include a capture mode, a default mode, and a demotion mode. Promotion mode corresponds to when the credit value (CRD) is greater than the upper boundary value (UPBN), and default mode corresponds to when the credit value (CRD) is less than the upper boundary value (UPBN) and greater than the lower boundary value (LWBN). The demotion mode corresponds to a case where the credit value CRD is smaller than the lower boundary value LWBN.

The control block 530 is configured to determine the values of the local control signal LCON such that a larger bandwidth is allowed in the promotion mode than the default mode for the corresponding master intelligent element, and a larger bandwidth is allowed in the default mode than the demotion mode. OV, INC, DEC) can be set. For example, the control block 530 sets the overflow value OV2 in the default mode to be smaller than the overflow value OV1 in the demotion mode, and sets the overflow value OV3 in the promotion mode to the default mode. It can be set smaller than the overflow value (OV2) in. In addition, the control block 530 sets the unit increment value INC in the default mode to be greater than the unit increment value INC in the demotion mode, and sets the unit increment value INC in the promotion mode to the unit in the default mode. It can be set larger than the increment value (INC). Although FIG. 16 illustrates a case in which the unit decrease value DEC is constant regardless of the operation mode, the unit decrease value DEC may be set differently according to the operation mode. That is, the request flow can be promoted by reducing the unit decrease value DEC, and the request flow can be suppressed by increasing the unit decrease value DEC.

17 is a block diagram illustrating a system according to embodiments of the present invention. Since the system 1000a illustrated in FIG. 17 is similar to the system 1000 illustrated in FIG. 1, redundant descriptions may be omitted.

Referring to FIG. 17, the system 1000a may include slave intelligent elements (IP) SLV1 and SLV2 (301 and 302) and master intelligent elements (MST1, MST2 and MST3) ( 101, 102, 103, service controllers QC1, QC2, QC3 501, 502, 503, and interconnect device 10. According to an embodiment, the system 1000a may further include a global controller 30.

The plurality of master intelligent elements 101, 102, 103 respectively generate requests for requesting service from at least one slave intelligent element 301, 302. The interconnect device 10 is connected to the slave intelligent devices 301, 302 and the master intelligent devices 101, 102, 103 via respective channels. Interconnect device 10 performs an arbitration operation of requests from master intelligent elements 101, 102, 103. The interconnect device 10 may include at least one arbiter for the arbitration operation. The plurality of service controllers 501, 502, 503 adaptively control the request flows of the master intelligent elements 101, 102, 103 according to a change in the operating environment of the system 1000.

The master intelligent elements 101, 102, 103 may include at least one real-time intelligent element. For example, the third master intelligent element 103 may be a real-time intelligent element such as a display controller. In addition, the second slave intelligent device 102 may be a memory controller that provides a service to the master intelligent devices 101, 102, and 103 in common. In this case, the service controller 503 corresponding to the real-time intelligent element 103 may generate an emergency signal UGNT indicating that an urgent service is required.

The system 1000a may further include a transmission line TL2 connected point-to-point between the service controller 503 corresponding to the real-time intelligent element 103 and the slave intelligent element 302. have. The emergency signal UGNT may be transmitted directly from the service controller 503 corresponding to the real-time intelligent device 103 to the slave intelligent device 302 via the transmission line TL2. The emergency signal UGNT may also be provided to the interconnect device 10, and the interconnect device 10 may adjust the priority in the arbitration operation based on the emergency signal UGNT.

The master intelligent elements 101, 102, 103 may include at least one best effort intelligent element. For example, the first master intelligent element 101 may be a best effort intelligent element such as a processor. In this case, the slave intelligent element 302 generates an external limit signal ELMT based on a change in the operating environment of the system, and the service controller 501 corresponding to the best effort intelligent element 101 receives an external limit signal ( In response to the ELMT, the request flow between the best effort intelligent element 101 and the interconnect device 10 may be blocked.

The system 1000a may further include a transmission line TL1 connected point-to-point between the service controller 501 corresponding to the best effort intelligent element 101 and the slave intelligent element 302. The external limit signal ELMT may be directly transmitted from the slave intelligent element 302 to the service controller 501 corresponding to the best effort intelligent element 101 through the transmission line TL1.

18 is a block diagram illustrating an example of a service controller included in the system of FIG. 17.

The service controller 503 shown in FIG. 18 may be a service controller for controlling the request flow of the real-time intelligent device 103 such as a display controller. Since the service controller 503 of FIG. 18 is similar to the service controller 500a of FIG. 3 except for the operation of the control block, overlapping description may be omitted.

The control block 540 generates a local control signal LCON for controlling the monitor 520 based on the change in the operating environment of the system. The change in the operating environment may be provided as the global control signal GCON as described with reference to FIG. 1 or may be provided as the status signals ST1, ST2, ST3. The control block 540 may also generate priority information (PRT) for the request from the corresponding master intelligent element 103 based on the credit value CRD. Priority information (PRT) may be provided to the interconnect device 10 and used as the basis of the arbitration operation.

The control block 540 may generate an urgent signal UGNT indicating that an urgent service is required for the real-time intelligent element 103 together with the priority information PRT. As described above, the emergency signal UGNT is provided to the slave intelligent element 302 in real time to be used to facilitate the service for the request of the real-time intelligent element 103 or to suppress the request flow of another master intelligent element. Can be.

At least a portion of the control block 540 may be implemented as a special function register having a configuration that performs a predetermined process sequence in response to stored values and input values.

19 is a diagram illustrating a method of controlling a request flow based on a credit value according to an embodiment of the present invention.

Referring to FIG. 19, the control block 540 illustrated in FIG. 18 sets a plurality of operation modes by dividing a range of a credit value CRD, and sets values of the local control signal LCON according to the operation modes. By setting (OV, INC, DEC) differently, the request flow of the corresponding master intelligent element can be controlled.

For example, the operation modes may include an emergency mode, a captive motion mode, a default mode, and a demotion mode. The emergency mode corresponds to the case where the credit value CRD is greater than the emergency level UGL, and the promotion mode corresponds to the case where the credit value CRD is greater than the upper boundary value UPBN. The emergency level UGL may be set to be equal to the upper boundary value UPBN or may be set to be larger than the upper boundary value UPBN. The default mode corresponds to when the credit value (CRD) is less than the upper boundary value (UPBN) and greater than the lower boundary value (LWBN), and the demotion mode is when the credit value (CRD) is less than the lower boundary value (LWBN). Corresponding.

The control block 540 may determine the values of the local control signal LCON such that a larger bandwidth is allowed in the promotion mode than the default mode for the corresponding master intelligent element, and a larger bandwidth is allowed in the default mode than the demotion mode. OV, INC, DEC) can be set.

In addition, the control block 540 may activate the emergency signal UGNT when the credit value CRD is greater than the emergency level UGL. When a very urgent service is required for the real-time intelligent device 103 as described above, the emergency signal UGNT is activated, and the service for the request of the real-time intelligent device 103 is promoted using the emergency signal UGNT. Request flow of other master intelligent elements can be suppressed.

20 is a diagram illustrating a method for generating an emergency signal according to an embodiment of the present invention.

Referring to FIG. 20, the emergency signal UGNT may be generated in a hysteresis manner by setting the activation condition and the deactivation condition of the emergency signal UGNT differently. The control block 540 of FIG. 18 activates the emergency signal UGNT at a time point t1 at which the credit value CRD is greater than the rising emergency level UGLR and the credit value CRD is smaller than the falling emergency level UGLF. At the point in time t3, the emergency signal UGNT can be deactivated. The falling emergency level UGLF may be set smaller than the rising emergency level UGLR.

In this case, at the time t2 when the credit value CRD becomes smaller than the rising emergency level UGLR, the activation state of the emergency signal UGNT is maintained as it is, and the credit value CRD is lowered to the falling emergency level UGLF. The emergency signal UGNT is deactivated at the time point t3. By generating the emergency signal UGNT in such a hysteresis scheme, it is possible to prevent the frequent operation mode change and to control the real-time intelligent device to stably solve the emergency state.

FIG. 21 is a block diagram illustrating an example of a service controller included in the system of FIG. 17.

The service controller 501 shown in FIG. 21 may be a service controller for controlling the request flow of the best effort intelligent element 101 such as a processor. Since the service controller 503 of FIG. 21 is similar to the service controller 500a of FIG. 3 except for the operating condition of the limiter 510, a redundant description may be omitted.

The limiter 510 of FIG. 21 may be enabled in response to the external limit signal ELMT as well as the limit signal LMT from the control block 530. To this end, the service controller 501 may further include an OR gate 550. The OR gate 550 may perform an OR operation on the limit signal LMT and the external limit signal ELMT, and the limiter 510 may be enabled in response to an output signal of the OR gate 550.

The limit signal LMT is activated when the corresponding best effort intelligent element 101 is sufficiently serviced and the external limit signal ELMT is activated when other master intelligent elements and / or slave intelligent elements are in an emergency state. Can be. As a result, the service controller 501 corresponding to the best effort intelligent element 101 may block the request flow of the best effort intelligent element 101 according to the change of the internal state and the external state.

FIG. 22 is a diagram illustrating an example of slave intelligent elements included in the system of FIG. 17.

Referring to FIG. 22, the slave intelligent element 302 may include a request queue 310 and a scheduler 320 to control the request flow of the system 1000a of FIG. 17.

Request queue 310 stores a plurality of requests delivered from master devices 101, 102, 103 via interconnect device 10. When a protocol that supports multiple outstanding transactions or multiple outstanding requests is employed, the slave intelligent element may include at least one request queue 310. Request queue 310 stores a plurality of requests that have already been issued from master intelligent elements but have not yet been completed.

The scheduler 320 may determine a service order for the stored requests based on the priorities of the requests stored in the request queue 310. Requests are sequentially sent to the internal circuit 340 according to the determined service order.

The scheduler 320 is generated from the real time intelligent element 103 among the requests stored in the request queue 310 in response to the emergency signal UGNT provided from the service controller 503 corresponding to the real time intelligent element 103. You can increase the priority of requests made. By increasing the priority, it is possible to facilitate the service to the real-time intelligent device 103 to solve the emergency state of the real-time intelligent device 103.

The scheduler 320 may activate the queue pool signal QF when more requests than the reference number are stored in the request queue 310 and are waiting for service. The AND gate 330 may generate an external limit signal ELMT by performing an OR operation on the emergency signal UGNT and the cue signal QF. As described above, the emergency signal UGNT may indicate that urgent service is required for the real-time intelligent device, and the external limit signal ELMT may be used to block the request flow of the best effort intelligent device.

In this manner, the emergency signal UGNT and the external limit signal ELMT can be used to promote the request flow of the real-time intelligent device and to suppress the request flow of the best effort intelligent device according to the change in the operating environment.

FIG. 23 is a diagram illustrating an example of a request structure and an emergency signal stored in the slave intelligent device of FIG. 22.

Referring to FIG. 23, the requests REQ stored in the request queue 310 may include a master identifier MID indicating a master intelligent element that generated the request REQ, a request identifier AxID for distinguishing a plurality of requests, It may include an address-command (ADD-COM) indicating the content of the request REQ and a priority AxQ of the request REQ.

The emergency signal UGNT may include a flag value FLG representing an emergency state of the master intelligent device and a master identifier MID representing the master intelligent device that generated the emergency signal UGNT. According to an embodiment, the emergency signal UGNT may include only the flag value FLG, and a master identifier MID representing the master intelligent element that generated the emergency signal UGNT may be provided as a separate signal.

The scheduler 320 of FIG. 22 compares the urgent signal UGNT and the master identifier MID of the requests stored in the request queue 310 from the master intelligent element in the emergency state when the flag FLG value indicates the emergency state. You can increase the priority of issued requests. Services for requests with increased priority can be facilitated and the emergency state of the master intelligent device can be resolved.

24 is a block diagram illustrating an example in which a system on chip according to embodiments of the present invention is applied to an electronic device.

Referring to FIG. 24, the electronic device 2000 includes a system on chip 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and an image sensor 1060. can do. Although not shown in FIG. 24, the electronic device 2000 may further include ports for communicating with a video card, a sound card, a memory card, a USB device, or the like, or communicating with other electronic devices. .

The system on chip 1010 is an application processor system on chip (AP SOC) according to embodiments of the present invention described with reference to FIGS. 1 to 23, and the interconnect device INT and a plurality of intelligent elements connected thereto (or Functional blocks). For example, the intelligent devices may include a memory controller (MC), a central processing unit, a display controller (DIS), a file system block (FSYS), and a graphics processor. (GPU), an image signal processor (ISP), a multi-format codec block (MFC), and the like. The memory controller MC corresponds to one of the aforementioned slave intelligent devices, and a plurality of intelligent devices among the other intelligent devices correspond to master intelligent devices using the memory controller MC as a common resource. Although not shown in FIG. 23, as described above, the system on chip 1010 includes service controllers that adaptively control request flows of the master intelligent elements according to a change in an operating environment of the system on chip.

The system on chip 1010 may include a memory device 1020, a storage device 1030, an input / output device 1040, and an image sensor through an address bus, a control bus, and a data bus. 2060). In some embodiments, the system on chip 1010 may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1020 may store data and program codes necessary for the operation of the electronic device 2000. For example, the memory device 1020 may be embodied as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and / or MRAM. have. The storage device 1030 may include a solid state drive, a hard disk drive, a CD-ROM, and the like. The input / output device 1040 may include input means such as a keyboard, a keypad, a mouse, and the like, and output means such as a printer or a display. The power supply 1050 may supply an operating voltage necessary for the operation of the electronic device 2000.

The image sensor 1060 may be connected to the system on chip 1010 through the buses or other communication links to perform communication. The image sensor 1060 may be integrated on one chip together with the system on chip 1010, or may be integrated on different chips, respectively.

At least some of the components of the electronic device 2000 illustrated in FIG. 24 may be implemented as various types of packages. For example, at least some of the configurations may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) It can be implemented using packages such as).

Meanwhile, the electronic device 2000 should be interpreted as all devices and systems including at least one system on chip. For example, the electronic device 2000 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, or the like.

FIG. 25 is a block diagram illustrating an example of an interface used in the electronic device of FIG. 24.

Referring to FIG. 25, the electronic device 1100 may be embodied as a data processing device capable of using or supporting a MIPI interface, and includes an application processor chip (AP SOC) 1110 and an image sensor 1140. And a display 1150 and the like.

The CSI host 1112 of the system on chip 1110 may perform serial communication with the CSI device 1141 of the image sensor 1140 through a camera serial interface (CSI). In one embodiment, the CSI host 1112 may include a deserializer DES, and the CSI device 1141 may include a serializer SER. The DSI host 1111 of the system on chip 1110 may perform serial communication with the DSI device 1151 of the display 1150 through a display serial interface (DSI).

In one embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). In addition, the electronic device 1100 may further include a radio frequency (RF) chip 1160 that may communicate with the system on chip 1110. The PHY 1113 of the electronic device 1100 and the PHY 1161 of the RF chip 1160 may perform data transmission / reception in accordance with Mobile Industry Processor Interface (MIPI) DigRF. In addition, the system on chip 1110 may further include a DigRF MASTER 1114 for controlling data transmission and reception according to the MIPI DigRF of the PHY 1161.

The electronic device 1100 may include a Global Positioning System (GPS) 1120, a storage 1170, a microphone 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. Can be. In addition, the electronic device 1100 may use an ultra wideband (UWB) 1210, a wireless local area network (WLAN) 1220, a worldwide interoperability for microwave access (WIMAX) 1230, or the like. Communication can be performed. The structure and interface of the electronic device 1100 illustrated in FIG. 25 are merely examples and are not limited thereto.

The system and system control method according to embodiments of the present invention may be usefully used in any apparatus and system including a plurality of master intelligent elements and at least one slave element commonly accessed by the master intelligent elements. Can be. In particular, the present invention can be usefully used in a system-on-chip in which a variety of semiconductor components are integrated in one chip, and digital cameras, mobile phones, PDAs, and PMPs that require miniaturization, high performance, and high-speed operation are required. ), And may be more usefully used for portable devices such as smartphones.

While the invention has been described above with reference to preferred embodiments, those skilled in the art will be able to make various modifications and changes to the invention without departing from the spirit and scope of the invention as set forth in the claims below. I will understand.

100, 101, 102, 103: master intelligent device
10: interconnect device
301 and 302: slave intelligent elements
500, 501, 502: service controller
PRT: Priority Information
UGNT: emergency signal
LMT: limit signal
ELMT: external limit signal

Claims (20)

At least one slave intelligent device;
A plurality of master intelligent elements each generating requests for requesting a service from the slave intelligent element;
An interconnection device connected to the slave intelligent element and the master intelligent elements via respective channels, the interconnection device performing an arbitration operation of the requests; And
A plurality of service controllers for adaptively controlling request flows of the master intelligent elements according to a change in an operating environment of a system on chip;
Each of the service controllers,
A monitor for detecting a service requirement level of the corresponding master intelligent element in real time and outputting a credit value indicating the service requirement level; And
A control block for generating a local control signal for controlling the monitor based on a change in the operating environment and for generating priority information for a request from the corresponding master intelligent element based on the credit value. On chip. According to claim 1,
A global controller for generating a global control signal indicative of a change in the operating environment based on at least one status signal,
And the service controllers control respective request flows based on the global control signal. The method of claim 2,
The slave intelligent device includes a memory controller,
The master intelligent elements include a modem and a display controller,
The state signal is,
A first status signal activated when the operating temperature of the memory controller is greater than a reference temperature;
A second status signal activated when the modem has not received service from the slave intelligent device for more than a reference time; And
And at least one of a third state signal activated when a storage rate of data stored in a data buffer of the display controller is less than a reference rate. delete According to claim 1,
The local control signal includes an overflow value, a unit increase value, and a unit decrease value determined according to a change in the operating environment,
The monitor,
A first counter for generating a first event signal activated at a period corresponding to the overflow value;
A service detector for generating a second event signal that is activated whenever a service is provided to the corresponding master intelligent element based on a channel signal between the corresponding master intelligent element and the interconnect device; And
And a second counter that increases the credit value by the unit increase value each time the first event signal is activated, and decreases the credit value by the unit decrease value each time the second event signal is activated. System-on-chip. The method of claim 5, wherein the control block,
And control a request flow of the corresponding master intelligent element by changing at least one of the overflow value, the unit increase value, and the unit decrease value based on a change in the operating environment. The method of claim 5,
The local control signal further includes a still value provided when the operating environment changes,
And the second counter decreases the credit value by the still value. The method of claim 1, wherein at least one of the service controllers is:
And a limiter that blocks a request flow between the corresponding master intelligent element and the interconnect device in response to a limit signal from the control block. The method of claim 8, wherein the control block,
And control the request flow of the corresponding master intelligent element by activating the limit signal when the credit value is less than the grant value and changing the grant value based on a change in the operating environment. The method of claim 8, wherein the limiter,
A synchronizer for generating a synchronization limit signal in response to the limit signal;
A first logic gate for logic operation of the sync limit signal and the valid signal from the corresponding master intelligent element to output a mask valid signal; And
And a second logic gate for logic operation of the sync limit signal and the ready signal from the interconnect device to output a mask ready signal. The method of claim 1, wherein the control block,
The plurality of operating modes are set by dividing the range of credit values, and the values of the local control signal are set differently according to the operating modes to control the request flow of the corresponding master intelligent element. On chip. The method of claim 1, wherein the slave intelligent device,
A request queue for storing a plurality of requests delivered from the master intelligent elements via the interconnect device; And
And a scheduler that determines a service order for the stored requests based on priorities of the stored requests. The method of claim 12,
The master intelligent elements include at least one real-time intelligent element,
And the service controller corresponding to the real-time intelligent device generates an emergency signal indicating that an urgent service is required. The method of claim 13,
And the scheduler of the slave intelligent device increases the priority of requests generated from the real-time intelligent device among the requests stored in the request queue in response to the emergency signal. The method of claim 12,
The master intelligent elements include at least one best effort intelligent element,
The slave intelligent device generates an external limit signal based on the change of the operating environment,
And the service controller corresponding to the best effort intelligent element interrupts a request flow between the best effort intelligent element and the interconnect device in response to the external limit signal. The method of claim 15,
And the slave intelligent device activates the external limit signal when more than a reference number of requests are stored in the request queue and are waiting for service. The method of claim 15,
The master intelligent elements further comprise at least one real-time intelligent element,
And the slave intelligent device activates the external limit signal in response to an emergency signal indicating that an urgent service is required for the real-time intelligent device. The method of claim 17,
The real-time intelligent device includes a display controller,
And the best effort intelligent device comprises a processor. A control method of a system on a chip in which at least one slave intelligent device and a plurality of master intelligent devices each generating requests for requesting service from the slave intelligent device are connected to an interconnect device,
Generating at least one state signal indicative of a state of at least one of the slave intelligent element and the master intelligent element;
Generating a global control signal indicating a change in an operating environment of the system on chip based on the status signal; And
Adaptively controlling request flows of the master intelligent elements based on the global control signal,
Controlling request flows of the master intelligent elements,
Detecting a service demand level of the corresponding master intelligent element in real time and outputting a credit value indicating the service demand level; And
Generating a local control signal for controlling the monitor based on a change in the operating environment, and generating priority information for a request from the corresponding master intelligent element based on the credit value; Chip control method. A service controller for controlling a request flow of a master intelligent device that generates a request for requesting a service from a slave intelligent device,
A monitor for detecting a service requirement level of the master intelligent element in real time and outputting a credit value representing the service request level; And
And a control block for generating a local control signal for controlling the monitor based on a change in operating environment and for generating priority information for a request from the master intelligent element based on the credit value.

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