JP5874143B2 - Display control unit - Google Patents

Description

  The present invention relates to a display control unit that controls a display unit such as an LCD.

  Patent Document 1 describes a technique that enables efficient memory access arbitration processing. Therefore, Patent Document 1 includes a memory access arbitration circuit for arbitrating a plurality of memory accesses, and the display control unit notifies the memory access arbitration circuit of an output priority mask signal that prioritizes display processing for a predetermined period. During the period when the output priority mask signal is valid, the memory access arbitration circuit waits for execution of a memory transfer request other than display and gives priority to display processing. The memory access arbitration circuit notifies the memory access arbitration circuit in advance of the transfer amount that the display control unit should transfer in one horizontal period. The memory access arbitration circuit opens the memory bus for other memory transfers based on the comparison between the memory access transfer amount and the threshold value.

Japanese Patent Laid-Open No. 2004-62333

  As described above, in an apparatus using an LCD as a user interface, the display control unit gives priority to the display output to the LCD, and always sends the synchronization signal and data. This is because if data transmission to the LCD is interrupted, it will immediately appear as image distortion.

  On the other hand, the printer requires real-time control for printing. If the frequency of access to the memory by the CPU and other hardware increases, there is a possibility of causing a delay in print control or failure in the worst case. Increasing the frequency of access to the memory causes a delay in touch screen processing and a decrease in the transfer rate of the interface circuit. Therefore, it is important to reduce the access frequency to the memory without reducing the quality of processing as much as possible.

  One embodiment of the present invention is a display control unit that supplies display data for displaying an image on a screen of a display unit. The display control unit includes an input unit that reads display data from the memory via an access control unit that controls access from a plurality of control units to a memory that stores a plurality of types of data including image data, and the input unit reads A buffer for temporarily storing the display data, and an output unit for outputting the display data stored in the buffer to the display unit. The input unit has a function for maintaining the access waiting time history for the memory, and when it is determined that access to the memory is concentrated based on the access waiting time history, the data of a plurality of pixels included in the display data is thinned out. The output unit includes a function of generating the thinned pixel data from the pixel data read from the memory and not thinned.

  This display control unit is included in the display data instead of acquiring all of the display data for outputting an image to the display unit such as the LCD with the highest priority when the input unit concentrates access to the memory. Display data is obtained by thinning out a plurality of pixel data. As a result, the display control unit contributes to alleviating access concentration to the memory and enables display data to be acquired within a predetermined timing range, thereby suppressing the access concentration from greatly affecting image display. In addition, since the data read by the display control unit is display data, it is highly related to adjacent pixels. For this reason, the output unit suppresses the display data from being significantly deteriorated by generating the thinned pixel data from the pixel data that has not been thinned, such as the top and bottom or the left and right of the pixel.

  The display data is preferably a part of frame data for refreshing the screen of the display unit at a predetermined refresh rate in units of frames. Even if the data of some pixels in the display data is deteriorated with respect to the actual pixel data, the image displayed on the screen of the display unit is significantly deteriorated by periodically refreshing. Can be suppressed.

  Therefore, in the system (apparatus) including the display control unit, when access to the memory is concentrated, the access frequency to the memory of the display control unit is reduced without significantly degrading the image quality in the display unit. Can improve the performance.

  The pixel data (pixel data) included in the display data may be acquired at appropriate timing or randomly thinned out. One method of thinning out and acquiring pixel data is to intermittently abandon periodic reading from the memory for reading display data. Therefore, it is preferable that the reading control function of the display control unit includes a function of intermittently abandoning and skipping periodic reading with respect to the memory for reading display data.

  The display skipping function of the display control unit preferably includes a function of abandoning periodic reading so that the positions of a plurality of pixels thinned out from previous display data do not overlap. By preventing the skipped pixels from overlapping or regularly appearing on the screen of the display unit, deterioration of the image displayed on the screen can be further suppressed.

  Further, the skipping function preferably includes a function of abandoning periodic reading so that a plurality of thinned pixels on the screen of the display unit do not continue vertically and horizontally. If a plurality of thinned pixels are continuous vertically and horizontally, it becomes difficult to generate (complement) the data of the thinned pixels in the output unit from the data of surrounding pixels.

  The skipping function includes a function of abandoning periodic reading within a predetermined time at a predetermined ratio when the average of the first time in the latest access waiting time exceeds the first value. Is preferred. It is possible to alleviate the concentration of access to the memory due to unexpected factors or non-periodic factors.

  When there is a periodic increase in the access waiting time, the skip-reading function predicts the timing of the periodic increase in the waiting time thereafter, and periodically reads the display control unit according to the timing. It may include the ability to give up at a rate. The concentration of access to the memory due to periodic factors can be predicted and mitigated.

  It is preferable that the read control function of the display control unit includes a function of setting data indicating that the pixel data is thinned out to the thinned pixel data. The thinned pixel data may be indefinite, but for example, low value or high value data indicating that the pixel data at the position where the periodic readout of the display data was abandoned was thinned. By setting, the thinned data can be determined by referring to the display data stored in the buffer by the input unit.

  One of the different aspects of the present invention includes the display control unit, the access control unit, and a print control unit that accesses the memory via the access control unit and supplies printing data to the printing mechanism. Device. When access to the memory by the display control unit and the print control unit is concentrated, the access frequency of the display control unit can be relaxed, deterioration of print quality due to delay in print control can be suppressed, and printing failure can be prevented. it can. An example of this apparatus is a controller such as an LSI or ASIC equipped with a display control unit and a print control unit.

  The apparatus further includes an apparatus having a memory, a display unit that receives display data from the display control unit, and a printing mechanism that receives printing data from the print control unit, such as a printer, a printing apparatus, and a multifunction peripheral. It may be.

One of the different aspects of the present invention is that a display unit, a display control unit that supplies display data for displaying an image on a screen of the display unit to the display unit, and a memory that stores a plurality of types of data including display data And an access control unit that controls access to a memory from a plurality of control units including a display control unit. This control method includes the following steps.
1. The display control unit reads the display from the memory via the access control unit.
2. The read display data is temporarily stored in a buffer.
3. Output the display data stored in the buffer to the display unit.

  The step of reading the display data includes acquiring the display data by thinning out the data of a plurality of pixels included in the display data when it is determined that access to the memory is concentrated due to the access waiting time for the memory. The outputting step includes generating the thinned pixel data from the non-thinned pixel data read from the memory.

  By this method, it is possible to suppress a decrease in the performance of the entire apparatus due to concentration of access, and to suppress a significant deterioration in display quality. The step of reading further includes intermittently abandoning and skipping periodic reading of the memory for reading display data when it is determined that access to the memory is concentrated due to the access waiting time. It is preferable.

FIG. 2 is a diagram illustrating an overview of a printer including an LCD. The block diagram which shows the outline | summary of a LCD control circuit. FIGS. 3A and 3B are diagrams illustrating an example in which display data is acquired at a reading skip condition (read skip rate) of ½, FIG. 3A shows a previous frame, and FIG. 3B shows a current frame. FIGS. 4A and 4B are diagrams illustrating an example in which display data is acquired at a reading skip condition (read skipping rate) of 1/3, FIG. 4A shows a previous frame, and FIG. 4B shows a current frame. It is a figure which shows a mode that the data of the pixel skipped from the data of the pixel which was not skipped are shown, FIG.5 (a) is interpolated from the data of the upper and lower, right and left pixel, FIG.5 (b) is the upper and lower pixel. FIG. 5C shows a state of interpolation from the data of the left and right pixels. The figure which shows an example of the smoothing filter for correct | amending an image. The flowchart which shows the process of a LCD control circuit. The timing chart which shows the example which sets a skipping condition. The timing chart which shows the example which sets a different skipping condition. 4 is a timing chart illustrating an example of setting different skipping conditions. An example of display data. 12A is an example of display data obtained by skipping some pixel data, FIG. 12B is an example of interpolating skipped pixel data, and FIG. 12C is a skipped pixel. Example of correcting the data. 13A is an example displayed using the display data of FIG. 12B, and FIG. 13B is an example displayed using the display data of FIG. 12C.

  FIG. 1 shows an outline of an apparatus (printer, multifunction device) using an LCD and a touch screen as a user interface. The apparatus (printer) 1 includes a printing mechanism (printer mechanism) 2 for printing information such as images and characters on recording paper (recording medium), and a printer controller (system controller) 5 including a function for controlling the printing mechanism 2. And an external memory 6 for temporarily storing data to be printed (print data, print data) 61. The printer controller 5 is realized by an integrated circuit device such as an LSI or an ASIC, but may be provided by one chip or a plurality of chips (chip sets). Moreover, you may provide with the printed circuit board carrying a some chip | tip. The external memory 6 may be included in the integrated circuit. The printer 1 may provide a function as a printer alone, or may be a multifunction machine including functions such as a scanner, or may be combined with another system such as a POS. It may be.

  The printer 1 further includes an LCD (display unit) 3 and a touch screen (touch panel) 7 that are user interfaces, and a USB interface 4 that transmits / receives information such as print data 61 to / from an external device. The printer 1 may further include an interface for transmitting / receiving information to / from an external device, for example, a LAN interface, a UART interface, an IEEE 1284 interface, or the like. The printer controller 5 includes a print control circuit (print control unit) 11 that controls the printing mechanism 2, an LCD control circuit (display control unit) 10 that controls the LCD (display unit) 3, and a touch screen that controls the touch screen 7. A controller 17 and a USB interface control circuit 14 that controls the USB interface 4 are included. The print control circuit 11 includes a motor control circuit 12 that controls the motor 21 of the printer mechanism 2 and a print head control circuit 13 that controls the print head 22. The printer controller 5 further includes a CPU 9 that controls the entire printer controller 5, a memory control circuit (memory control unit) 16 that controls input / output (writing and reading) to the memory 6, the CPU 9, and a plurality of control circuits. 10 includes a memory access arbitration circuit (access control unit) 15 that controls access between the memory 11 and the memory 6.

  In the memory 6, in addition to the print data 61, a program and data (CPU instruction code / data) 62 for controlling the CPU 9, data (frame data) 63 for displaying an image on the LCD 3, and motor control Data (motor phase data) 64 is stored. The memory 6 is also used as a transmission data buffer 65 and a reception data buffer 66 when data is transmitted / received by the USB interface 4.

  Therefore, the memory access arbitration circuit 15 controls the timing so that many accesses to the memory 6 are performed as appropriate. For accessing the memory 6, CPU instruction code / data 62 and other data are input / output by the CPU 9, the frame data 63 is read by the LCD control circuit 10, the motor phase data 64 is read by the motor control circuit 12, and the print head control circuit 13, reading of print data 61 by 13, and input / output to / from the transmission buffer 65 and reception buffer 66 by the USB interface control circuit 14 are included.

  FIG. 2 is a block diagram showing the configuration of the LCD control circuit (display control unit) 10. The LCD control circuit 10 uses the frame data 63 stored in the memory 6 to periodically display the screen of the LCD 3 as a display unit in units of frames, for example, at a refresh rate of about 50 to 100 Hz, preferably about 70 to 75 Hz. The image on the LCD 3 is updated to maintain the latest state. Specifically, the LCD control circuit 10 reads a part of the frame data 63, for example, data (display data) 63a of one or a plurality of scanning lines from the memory 6 at any time, and outputs to the LCD 3 for rewriting.

  Therefore, the LCD control circuit 10 periodically accesses the memory 6 via the memory access arbitration circuit 15 and reads the display data 63a as a plurality of pixel data, and the display data read by the input unit 30. A buffer 50 for temporarily storing 63a, and an output unit 40 for outputting the display data 63a stored in the buffer 50 to the LCD 3 in a state (unit) that is easy to display on the LCD 3, such as a scanning line unit (line unit). And have.

  The input unit 30 outputs a predetermined address of a frame buffer area in which the frame data 63 of the memory 6 is stored, and a memory access circuit 32 that periodically reads the display data 63a in units of several pixels, for example, in units of 4 pixels. A function (waiting time history holding circuit) 33 for holding a history of the access waiting time TW when the memory access circuit 32 acquires the display data 63a. In the printer controller 5, the access waiting time TW for the memory 6 is controlled by the access arbitration circuit 15. Therefore, the access waiting time TW for the memory 6 varies depending on the concentration of access to the memory 6.

  The input unit 30 includes a read control unit (read control function) 31 that controls the function of the memory access circuit 32 from the history of the waiting time TW. The read control unit 31 determines that access to the memory 6 is concentrated based on the history of the waiting time TW, and when it is determined that access to the memory 6 is concentrated, it is included in the display data 63a. Display data 63a is obtained by thinning out a plurality of pixel data. Therefore, the read control function 31 intermittently abandons periodic reading of the memory access circuit 32 and skips the display data 63a (frame buffer read control circuit) 35, and the waiting time history holding circuit 33 It includes a skip determination function (read skip determination circuit) 34 for setting a condition 34f for analyzing and skipping the history data 33d of the access waiting time TW, and a function (result holding circuit) 36 for holding the result of the skip determination. .

  Further, the output unit 40 generates an interpolation correction function for generating the data of the thinned pixels (pixels skipped) from the data of the pixels read from the memory 6, that is, the data of the pixels not skipped. Interpolation correction circuit) 41.

  In the printer 1 using a display unit such as the LCD 3 as a user interface (UI), the LCD control circuit 10 must continue to send a synchronization signal and data (frame data) 63 to the LCD 3. If the data transmission is interrupted, it becomes a big problem because it appears immediately as a disturbance of the image. Therefore, normally, when a plurality of hardware (control circuits) including the LCD control circuit 10 and the CPU 9 share the memory 6, normally, arbitration is performed with the highest priority given to the access to the memory 6 of the LCD control circuit 10. This prevents data transfer from being interrupted. However, in the control of the printer 1, the real time property of the print control is high, and there is a possibility that the print control may be delayed or broken due to the lower priority of memory access of the CPU 9 or other hardware. In addition, the processing of the touch screen 7 may be delayed or the transfer band of the USB interface control circuit 14 may be reduced.

  Also in the printer controller 5, the CPU 9 and a large number of hardware including the LCD control circuit 10, for example, the motor control circuit 12, the print head control circuit 13, and the USB interface control circuit 14 share the memory 6. The LCD control circuit 10 reduces the peak memory bandwidth of the printer controller 5 without greatly reducing the quality of the image displayed on the LCD 3 by skipping a part of the display data 63a when the access is concentrated on the memory 6. Can do.

  That is, the LCD control circuit 10 reads all the frame data 63 or display data 63a from the memory 6 and transfers it to the LCD 3 when the necessary memory bandwidth of the entire system of the printer controller 5 is small. However, when the required memory bandwidth is large during printing control or the like, reading from the memory 6 is thinned out, and pixels that have not been read are generated by interpolation. If the LCD control circuit 10 skips reading when the memory access frequency is high, the image quality of the image displayed on the LCD 3 may be temporarily deteriorated. However, the frequency of memory access at the time of print control is not constant, and the number of memory accesses is repeatedly increased and decreased at regular intervals according to the motor control cycle, so that the image quality does not continuously deteriorate. Therefore, the peak bandwidth of the memory can be reduced without significantly degrading the quality of the image displayed on the LCD 3.

  Therefore, the printer controller 5 can reduce the delay in print control due to the concentration of memory access, and can avoid the failure of printing. In addition, the delay of the touch screen process can be reduced, and the transfer bandwidth of the interface circuit can be improved. Furthermore, since the LCD control circuit 10 can acquire the display data 63a at a predetermined timing, it is possible to continue sending the synchronization signal and the display data 63a to the LCD 3. Therefore, the data transmission in the LCD 3 is not interrupted, and it is possible to prevent the image from being disturbed.

  The required memory bandwidth of the system (printer controller) 5 at a certain point in time can be estimated by holding the history data 33d of the waiting time TW during memory access. That is, by analyzing the history data 33d of the waiting time TW, the frequency of memory access of other circuits can be estimated. For this reason, the history holding circuit 33 holds the history data 33d.

  One of the methods for determining the memory bandwidth is that when a certain length of waiting time TW occurs at a certain frequency, it is determined that the memory access frequency of other circuits is high and the required memory bandwidth of the system is large. That is. For this reason, when the average of the read access waiting time TW executed within the latest first time of the history data 33d exceeds the first value, the skip-reading determination circuit 34 within the predetermined time thereafter Includes a function (first function) 34a for setting a skip condition 34f so as to abandon the periodic reading at a predetermined ratio.

  Further, when the change in the waiting time TW has periodicity, it is possible to predict the memory bandwidth in accordance with the cycle. For this reason, when there is a periodic increase in the history data 33d of the access waiting time TW, the skipping determination circuit 34 abandons the periodic reading at a predetermined ratio in accordance with the subsequent periodic increase timing. A function (second function) 34b for setting the skipping condition 34f is included.

  The pixels to be skipped may be selected at random, but if the same pixel of the image displayed on the LCD 3 or the pixels of the same X coordinate or Y coordinate are skipped, the complemented pixels are concentrated after skipping. However, it becomes a factor that the image quality deteriorates. Therefore, the skipping determination circuit 34 refers to the skipping result held in the result holding circuit 36, and the position of the pixel to be skipped is the position of the pixel skipped by the previous frame data 63 or the previous display data 63a as much as possible. And a function (third function) 34c for controlling so as not to overlap. Thereby, the interpolation correction circuit 41 of the output unit 40 complements the skipped pixels at a pixel position different from the previous frame data 63 or the previous display data 63a, and can suppress the deterioration of the display image quality.

  The third function 34c adds the skipped pixel position in the previous frame held in the result holding circuit 36 to the skipping condition 34f when determining skipping of pixels. When skipping, the first function 34a and the second function 34b reduce the number of memory accesses to 1/2, 2/3, and the like. If the read ratio is 1/2, the read control circuit 35 alternately reads and skips reading. If the read ratio is 2/3, the read control circuit 35 controls the memory access circuit 32 so as to skip the next reading after two consecutive readings. When performing this skipping operation, the third function 34c starts skipping from the beginning of the position read in the previous frame in order to avoid skipping pixels at the same position for two consecutive frames. As a result, if the skip ratio is 50% or less, it is always read once every two frames.

  FIG. 3 shows an example in which the display data 63a is read at a reading skip rate of 50% (reading rate ½). In the figure, the whitened ones indicate the pixels (actual pixels) 63r that are actually read, and the blacked ones are the pixels that are skipped and complemented later (complementary pixels) 63c. Complementary pixels overlap by changing the timing of skipping between the immediately preceding frame data 63 (n−1) shown in FIG. 3A and the current frame data 63 (n) shown in FIG. Can be prevented.

  FIG. 4 shows an example in which the display data 63a is read at a reading skip rate of 33% (a reading rate of two thirds). Also in this case, the complementary pixel is changed by changing the timing of skipping between the immediately preceding frame data 63 (n−1) shown in FIG. 4A and the current frame data 63 (n) shown in FIG. It can prevent duplication.

  When the period for reducing the number of memory accesses by skipping is very short or when the skip frequency is low, the skip condition by the third function 34c may be ignored. For example, if the period during which memory accesses are concentrated is short and the skip period ends in a time shorter than one line data transfer of LCD 3 (one line transfer is about 35 us with a 480 line LCD), the third function 34c You may cancel the prohibition on skipping duplicate reading. The same applies to the case where the frequency of skipping is low and it occurs only at intervals of about three lines at most (transfer of three lines is about 100 us with a 480-line LCD). Furthermore, skipping over 50% may occur when conditions such as a slight deterioration in the image quality of the LCD 3 are set by the user or when the frame rate of the LCD 3 is high (such as close to 100 Hz). Even when the ratio is requested, the prohibition of duplicate skipping may be canceled by the third function 34c.

  Further, the skip skip determination circuit 34 refers to the skip skip result held in the result hold circuit 36 and periodically reads out the plurality of thinned pixels on the screen of the LCD 3 so as not to be continuous vertically and horizontally. A function (fourth function) 34d for setting the abandoning condition to the skipping condition 34f is included. This is because in the interpolation correction circuit 41 of the output unit 40, it is possible to interpolate and / or correct the pixel data skipped by the pixel data that has not been skipped above and below or right and left of the pixel.

  When a read skip condition is set by the read determination circuit 34, the read control circuit 35 sends a signal S for controlling the read skip timing to the memory access circuit 32 to control the read skip timing (read timing).

  The position of the skipped pixel is stored in the result holding circuit 36. Therefore, the interpolation correction circuit 41 of the output unit 40 may generate (restore) the pixel data skipped by referring to the skip result (read skip history) held in the result holding circuit 36. On the other hand, a predetermined value is put in the data of the skipped pixel in the display data 63a, and the display data 63a is read from the buffer 50 so that it can be determined whether the pixel is skipped. Good. For this reason, the read control circuit 35 includes a function 35 a that sets specific data indicating that the data is not read from the memory 6 in the thinned pixel data. If the pixel data is an 8-bit × 3 data set indicating the gradation of each RGB color in 8 bits, examples of data set in the skipped pixel data are (7F / 7F / 7F) and (FF / FF / FF).

  The buffer 50 of the LCD control circuit 10 temporarily stores display data 63a read by the input unit 30 in units of pixels, for example, in units of four pixels, and the output unit 40 outputs to the LCD 3 in units of one line or a plurality of lines. To refresh the image. The buffer 50 of this example is a single port memory having a capacity capable of storing display data 63a for four lines. The pixel data generated by the interpolation correction circuit 41 of the output unit 40 is skipped by the input unit 30 with the data of a certain line of the display data 63a, and fed back to the buffer 50, and the pixel of the next line skipped is read. Used to generate data.

  If there is a skipped pixel in the display data 63a, the interpolation correction circuit 41 of the output unit 40 generates (complements) that data using surrounding pixel data. Accordingly, the fourth function 34d of the skipping determination circuit 34 controls to perform skipping only when data of surrounding pixels exist without skipping in order to enable interpolation of pixels. As described above, the history of the result holding circuit 36 may be referred to as to whether or not it is a skipped pixel to be interpolated and corrected, and it is determined by data (high value or the like) indicating that the skip is performed. You may judge.

  The interpolation correction circuit 41 refers to two adjacent pixels to generate (complement) pixel data, and a pixel complemented by a smoothing filter (complement pixel) and a read pixel (actual pixel). And an image correction circuit 43 for improving the image quality by making the difference from the above inconspicuous. The pixel interpolation circuit 42 may generate complementary pixel data with reference to adjacent four pixels.

  FIG. 5 shows some examples of the relationship between the interpolation method and pixel skipping. When reading is skipped so as not to be continuous left and right and up and down like the black dots 63c in FIG. 5A, the data of the skipped pixel 63c is white dots 63r that are not skipped from top to bottom and left and right. Can be interpolated by the data. When reading is skipped so as not to be continuous up and down as shown in FIG. 5B, the data of the skipped pixel 63c can be interpolated from the data of the pixel 63r that has not been skipped. When skipping left and right as shown in FIG. 5C, the data of the skipped pixel 63c can be interpolated from the data of the left and right pixel 63r.

  For example, when an image including characters is displayed on the LCD 3, if the pixel interpolation circuit 42 complements the image by referring to two adjacent upper and lower pixels, the line of one pixel in the horizontal direction disappears, and the pixel value of the complementary pixel and the actual pixel is lost. There may be significant differences in Since the LCD display is an overlay display of the actual pixel and the complementary pixel, the difference between the complementary pixel and the actual pixel can be made inconspicuous by reducing the luminance difference between the complementary pixel, the actual pixel, and the surrounding pixels. it can. For this reason, in the image correction circuit 43, the complementary pixels are less noticeable by performing a smoothing process on the complementary pixels using a smoothing filter. FIG. 6 shows an example of the smoothing filter 49.

  The pixel interpolation circuit 42 of the interpolation correction circuit 41 of this example generates each value of R, G, and B of the pixel data included in the display data 63a by an average value of the values of the surrounding two pixels or four pixels. The image correction circuit 43 converts the pixel data from the RGB format to the YCbCr format to smooth the Y value, and then inversely converts the luminance difference from the surrounding pixels.

An example of the conversion formula from the RGB format to the YCbCr format is as follows.
Y = 0.256835938 × R + 0.50390625 × G + 0.098144531 × B + 16
Cb = −0.147949219 × R−0.291015625 × G + 0.438964844 × B + 128
Cr = 0.438964844 × R−0.368164063 × G−0.070800781 × B + 128 (1)
An example of a conversion formula from the YCbCr format to the RGB format is as follows.
R = 1.1640625 × (Y−16) + 1.596191406 × (Cr−128)
G = 1.1640625 × (Y−16) −0.392089844 × (Cb−128) −0.812988281 × (Cr−128)
B = 1.1640625 × (Y−16) + 2.017089844 × (Cb−128) (2)

  FIG. 7 is a flowchart showing an outline of the process of the LCD control circuit 10. In the following, the frequency of the memory bus and CPU of the printer controller 5 is 100 MHz (0.01 μs cycle), and the memory access circuit 32 of the input unit 30 reads 4 pixels (4 clocks, 1 pixel 1 clock) in one data read. Display data 63a is acquired from the memory 6. Actually, since the waiting time TW is included, 4 clocks + the waiting time TW is consumed in one data read.

  In step 71, when it is time to determine whether or not there is access concentration, the skip skip determination circuit 34 of the input unit 30 determines whether it is necessary to set skip skip. The read skip determination circuit 34 determines whether or not there is access concentration during the first time T1 (1 μs in this example) and between the average waiting time TWA1 of reading and the second time T2 (2 μs in this example). Judgment is made in two stages of the average waiting time TWA2 of the read that has been executed. Therefore, the skip-reading determination circuit 34 determines whether there is access concentration every 1 μs in step 71. In step 72, the first function 34a calculates the average waiting time TWA1 of the most recent first time T1 (1 μs). If the first value, in this example, 8 clocks or more, sudden access concentration occurs. In step 74, the skip condition 34f is set at a relatively large ratio, for example, a ratio of 50%, for the same period as the subsequent first time T1, that is, for 1 μs. At this time, the third function 34c and the fourth function 34d cooperate to set a skipping condition 34f that satisfies the above-described condition.

  In step 73, the second function 34b calculates an average waiting time TWA2 for each second time (2 μs), and the average waiting time TWA2 is equal to the second value, which is 8 clocks in the present example, the same as the first value. If it is above, it is determined that there is an access concentration of a degree that is preferably eliminated. Further, when the second function 34b has periodicity in the increase / decrease of the average waiting time TWA2, in step 74, the skip function 34f is set so that the skip is performed at the timing corresponding to the periodic access concentration. To do. Also in this case, the third function 34c and the fourth function 34d cooperate to set the skipping condition 34f that satisfies the above-described condition.

  On the other hand, if it is not found in step 72 and 73 that the concentration of access that is preferable to be eliminated is found, the skipping determination circuit 34 resets the skipping condition 34f in step 75.

  In step 76, when it is time to read the display data 63a, the read control circuit 35 of the input unit reads the pixel data included in the display data 63a from the memory 6 via the arbitration circuit 15 using the memory access circuit 32. Store in buffer 50. Although depending on the presence or absence of the waiting time TW, the memory access circuit 32 periodically accesses the memory 6 and acquires pixel data about 5 to 10 times within 1 μs. At this time, if the skip condition is set in step 77, the read control circuit 35 determines whether or not skip is necessary. If the skipping condition 34f is set and skipping is necessary, the read control circuit 35 performs periodic memory access of the memory access circuit 32 at a frequency of 1/2 or 1/3 in step 81. Mask and write “FF” data for four pixels in the buffer 50. If it is not necessary to skip reading, the read control circuit 35 causes the memory access circuit 32 to perform periodic reading in step 78 and stores the pixel data read in step 79 in the buffer 50. In step 80, the waiting time history holding circuit 33 records the access waiting time TW.

  In step 82, when it is time to output the display data 63a, the output unit 40 reads it from the buffer 50 and supplies it to the LCD 3. For example, when the display data 63a for one line is stored in the buffer 50, the output unit 40 supplies the display data 63a for one line from the buffer 50 to the LCD 3 in step 86. At this time, if there is a pixel skipped in step 83, the pixel interpolation circuit 42 of the interpolation correction circuit 41 interpolates the skipped pixel data in step 84, and in step 85, the image correction circuit 43 further The correction is performed including the data around the complemented pixels.

  FIG. 8 shows a state in which the skipping condition 34 f is set by the first function 34 a of the skipping determination circuit 34. In the first function 34a, the average waiting time TWA1 of the most recent first time T1 (1 μs in this example) stored in the history data 33d is equal to or greater than the first value (8 clocks in this example) (in the figure). If H), the skip condition 34f is set to 1/2 for the first time T1. The first function 34a sets the skip condition 34f if the average waiting time TWA1 of the most recent first time T1 stored in the history data 33d is less than the first value (L in the figure). Reset (0 in the figure). Therefore, the first function 34a sets the skipping condition 34f to “1/2” when the average waiting time TWA1 becomes “H” at time t1.

  When the average waiting time TWA1 becomes “L” at time t2, the first function 34a resets the skipping condition 34f to “0”. If the average waiting time TWA1 becomes “H” again at time t3, the first function 34a sets the skip condition 34f to “1/2”, and maintains the skip condition 34f at times t4 to t6. When the average waiting time TWA1 becomes “L” at time t7, the first function 34a resets the skipping condition 34f to “0”.

  In this example, the LCD control circuit 10 accesses at half the normal rate for 4 μs from time t3 to time t7. Normally, when pixel data is periodically read out with an interval of about 8 clocks, access occurs about 33 times (400 clocks / (4 + 8) clocks). By setting the read skip condition 34f to “1/2”, a 12-clock mask signal (WAIT signal) S is output from the read control circuit 35, and the number of accesses in 4 μs is reduced to about 16. Therefore, the concentration of access to the memory 6 can be reduced. On the other hand, the LCD control circuit 10 skips part of the pixel data, but as a whole, the display data 63a can be read from the memory 6 at a predetermined timing. The pixel data skipped can be supplemented in the output unit 40.

  FIG. 9 shows a state in which the skipping condition 34 f is set by the second function 34 b of the skipping determination circuit 34. In the second function 34b, the average waiting time TWA2 is equal to or more than the first value (8 clocks in this example) in the latest third time T3 (1000 μs in this example) stored in the history data 33d ( It is determined whether or not the state M) in the figure occurs periodically. When the second function 34b analyzes the history data 33d of the third time T3 at the time t19, until the time t11, the time t12 to t13, the time t14 to t15, the time t16 to t17, and the time t18 to t19. During each 200 μs, the average waiting time TWA2 of the second time T2 (2 μs in this example) is 3 to 7 clocks, from time t11 to t12, time t13 to t14, time t15 to t16, and time t17 to t18. During each 10 μs, the average waiting time TWA2 was 8-15 clocks. Therefore, in the history data 33d, the period in which the average waiting time TWA2 is equal to or greater than the first value occurs four times at intervals of 10 μs every 200 μs, and the second function 34b performs a period based on the analysis result. Therefore, it is determined that a period in which memory access is concentrated occurs.

  Therefore, the second function 34b relaxes the concentration of memory access by setting the read skip condition 34f to “1/2” from the time t19 when the next access concentration starts to the time t20 after 10 μs. Also at the time t21, during the most recent third time T3, a period in which the average waiting time TWA2 is equal to or greater than the first value occurs four times at intervals of 10 μs every 200 μs. Therefore, the second function 34b reduces the concentration of memory access by setting the read skip condition 34f to “1/2” again from time t21 when the next access concentration starts to time t22 after 10 μs. To do.

  FIG. 10 shows a state in which the skipping condition 34f is set by the first function 34a and the second function 34b of the skipping determination circuit 34, respectively. In addition to the conditions shown in FIG. 9, between time t31 and time t33 between times t16 and t17 (for example, 20 μs), when the average waiting time TWA1 every 1 μs becomes 8 clocks or more, the first function 34a Accordingly, the skip condition 34f is set to “1/2” at time t32 1 μs after time t31. Further, the first function 34a resets the skip condition 34f to “0” at time t34 after 1 μs from time t33.

  FIG. 11 shows an example of the display data 63a stored in the memory 6, and FIG. 12 shows how interpolation and correction are performed after skipping some pixel data of the display data 63a. In these figures, only Y values obtained by converting pixel data into YCbCr data are schematically shown.

  FIG. 12A shows a state in which the pixel indicated by (FF) is skipped in the display data 63a shown in FIG. FIG. 12B shows that pixel data skipped by the pixel interpolation circuit 42 of the interpolation correction circuit 41 of the output unit 40 is not skipped by the pixel interpolation circuit 42 of the output unit 40. The figure shows a state interpolated from data 63r of upper and lower pixels (actual pixels).

  FIG. 13A shows a state where the image of FIG. 12B and the image of FIG. 11 are superimposed. This state schematically shows a state where display data 63a including pixel data skipped on the LCD 3 is displayed. When an image is displayed on the LCD 3 using the display data 63a that has been partially skipped, a slight deterioration appears, but an image that can be sufficiently discriminated is displayed. Actually, since the images are rewritten one after another at a frame rate of several tens of Hz, the image is displayed with an image quality several levels higher than that in FIG.

  FIG. 12C further shows a state in which the complementary pixel data 63c is corrected from the data of surrounding pixels by the image correction circuit 43 using the smoothing filter shown in FIG. FIG. 13B shows a state where the image of FIG. 12C and the image of FIG. 11 are superimposed. This state schematically shows a state where display data 63a including pixel data skipped on the LCD 3 is displayed. Compared with FIG. 13A, the image quality of the image displayed on the LCD 3 is considerably improved, and the characters are displayed sufficiently clearly.

  As described above, even if data of some pixels in the display data 63a is temporarily skipped, the pixel data 63c skipped can be complemented by using the pixel data 63r that has not been skipped. Further, since the image on the LCD 3 is refreshed at a predetermined frame rate, the deterioration of the image due to the skipped pixels is hardly noticeable, and the concentration of access to the memory 6 can be reduced while suppressing the deterioration of the image.

  Accordingly, in the printer controller 5 and the printer 1, when the access frequency between the printer control circuit 11 and the memory 6 increases when printing is performed by the printing mechanism 2, the access concentration of the LCD control circuit 10 is reduced. The frequency of peak access to the memory 6 can be reduced. For this reason, it is possible to execute printing without affecting the real-time print control. The same applies when the frequency of access to the memory 6 is increased by the processing of the touch screen 7 or the processing of the USB interface control circuit 14. Then, by complementing the skipped pixel data, image deterioration can be suppressed even if the access frequency to the memory 6 of the printer control circuit 11 is lowered.

  Therefore, in the printer controller 5, the hardware cost is increased by providing a dedicated built-in frame buffer inside the LCD control circuit 10 or preparing a dedicated external frame buffer memory outside the printer controller (LSI) 5. The frequency of memory access for data transmission to the LCD 3 can be reduced without using the inviting method. Further, the frequency at which accesses to the memory 6 are concentrated by the printer control circuit 11 and other control circuits is not so high, and the display data 63a can be acquired without being skipped by the LCD control circuit 10 for most of the time. For this reason, the time during which the quality of the image actually displayed on the LCD 3 is slightly deteriorated is very short, and hardly affects the performance as a user interface.

  The smoothing filter, the access concentration determination method, and the periodic access concentration determination method described above are examples. For example, the smoothing filter may be 4 × 4 pixels or more, and the time for obtaining the average waiting time is not limited to 1 μs or 2 μs. The occurrence of a periodic waiting time may be determined in a time shorter or longer than 1000 μs, and the presence or absence of periodicity may be determined three times or less or five times or more.

  Furthermore, in the present embodiment, the description has been given using the LCD as an example of the display unit. However, if the display unit requires refreshing, other display units such as an organic EL display and a plasma display may be used. May be. Further, the present invention can be applied not only to a printer but also to other systems having a display unit.

1 Printer system 3 LCD
6 Memory 10 LCD Control Unit 15 Memory Access Arbitration Circuit

Claims (12)

A display control unit for supplying display data for displaying an image on a screen of the display unit to the display unit;
An input unit that reads the display data from the memory via an access control unit that controls access from a plurality of control units including the display control unit to a memory that stores a plurality of types of data including the display data;
A buffer for temporarily storing the display data read by the input unit;
An output unit for outputting the display data stored in the buffer to the display unit;
The input unit has a function of holding a history of access latency to the memory;
When it is determined that access to the memory is concentrated according to the history of the access waiting time, a read control function for acquiring the display data by thinning out data of a plurality of pixels included in the display data,
The output unit includes a function of generating thinned pixel data from pixel data read from the memory.   The display control unit according to claim 1, wherein the read control function includes a function of intermittently abandoning and skipping periodic reading from the memory for reading the display data.   3. The display control unit according to claim 2, wherein the skipping function includes a function of abandoning the periodic reading so that positions of the plurality of thinned pixels of the previous display data do not overlap.   4. The display control according to claim 2, wherein the skipping function includes a function of abandoning the periodic reading so that the plurality of thinned pixels are not continuous vertically and horizontally on the screen of the display unit. unit.   5. The read skip function according to claim 2, wherein when the average of the most recent first time of the access waiting time exceeds a first value, the periodicity within a predetermined time thereafter Display control unit including a function of abandoning accurate reading at a predetermined rate.   6. The read skip function according to claim 2, wherein when the access waiting time has a periodic increase, the periodic read is predetermined in accordance with the subsequent periodic increase timing. Display control unit, including the function to abandon at a ratio of. In any one of Claims 1 thru | or 6.
The display control unit, wherein the readout control function includes a function of setting data indicating thinning in the thinned pixel data.   8. The display control unit according to claim 1, wherein the display data is a part of frame data for refreshing a screen of the display unit at a predetermined refresh rate in units of frames. A display control unit according to any one of claims 1 to 8,
The access control unit;
A printing control unit for supplying printing data from the memory to a printing mechanism via the access control unit. The claim 9, further comprising:
The memory;
The display unit for receiving the display data from the display control unit;
A printing mechanism for receiving printing data from the printing control unit. A display unit; a display control unit that supplies display data for displaying an image on a screen of the display unit to the display unit; a memory that stores a plurality of types of data including the display data; and the display control unit. An access control unit for controlling access to the memory of a plurality of control units, comprising:
The display control unit reads the display data from the memory via the access control unit;
Temporarily storing the read display data in a buffer;
Outputting the display data stored in the buffer to the display unit;
In the reading, when it is determined that access to the memory is concentrated due to an access waiting time for the memory, the display data is acquired by thinning out data of a plurality of pixels included in the display data. Including
The outputting includes generating the thinned pixel data from the pixel data read from the memory.   12. The reading is intermittently abandoned in periodic reading of the memory for reading the display data when it is determined that the access to the memory is concentrated due to the access waiting time. Control method including skipping.

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