JP3675349B2 - Access control method and access control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an access control method for arbitrating a plurality of access requests.
[0002]
[Prior art]
There are various types of access. Hereinafter, a DRAM (memory) will be described as an access target.
[0003]
FIG. 5 shows a conventional access control circuit. The refresh execution remaining number counter 1 counts up the number of refresh executions by counting up with a refresh clock and counting down with refresh execution. The refresh request generation circuit 2 outputs a refresh request when the value of the refresh execution remaining number counter 1 is other than 0, and when the value of the refresh execution remaining number counter 1 becomes equal to or greater than a threshold, the priority of the arbitration circuit 3 is refreshed. Outputs the highest priority switching signal for switching so that becomes the highest priority. The arbitration circuit 3 arbitrates the refresh request, syndrome operation access request, and input data write request, and the memory control signal generation circuit 4 generates a memory control signal to the memory 5 based on the arbitration result of the arbitration circuit 3.
[0004]
Since the memory 5 which is a DRAM needs to be refreshed 512 times within 8.2 msec, the refresh execution remaining number counter 1 is counted up with a clock of about 70 kHz, and the refresh execution remaining number is counted down by refresh execution. Count. When the count value of the refresh execution remaining number counter 1 becomes equal to or greater than the threshold value, the refresh cannot be done in time. Therefore, the priority order of the arbitration circuit 3 is changed by the highest priority switching signal so that the refresh priority order becomes the highest priority. By performing refresh, 512 refreshes are realized within 8.2 msec.
[0005]
6A and 6B are diagrams illustrating an arbitration method of the arbitration circuit 3 in FIG. 5, in which (A) is a refresh request, and (B) is a syndrome calculation access request.
[0006]
This syndrome calculation access request has a high access request frequency and uses the page mode, so that the access efficiency is improved by continuous access. (C) is an input data write request.
[0007]
Access priority is usually
Input data write request> syndrome operation access request> refresh request.
[0008]
(D) represents the count value of the remaining refresh execution counter 1 and (E) represents the arbitration result of the arbitration circuit 3.
[0009]
As shown in FIG. 6, in the conventional access control method, in order to satisfy the number of refreshes, when the value of the remaining refresh execution counter 1 in (D) exceeds a threshold value, the value of the remaining refresh execution counter 1 becomes 0. Until then, it was continuously refreshed with the highest priority.
[0010]
[Problems to be solved by the invention]
However, in the conventional access control method, since the syndrome calculation access request has a high access request frequency and has a higher priority than the refresh, there are few opportunities to perform the refresh. Since the refresh is continuously performed with the highest priority when the remaining number of refreshes is equal to or greater than the threshold value, the input data write is performed during the refresh as in the third input data write request in FIG. There was a problem that the request was awaited and input data writing was delayed while data was input at a constant rate, input data was lost, and the system broke down.
[0011]
Therefore, the access control method of the present invention does not continuously perform refresh execution with the highest priority, but distributes the refresh execution and permits high priority access such as input data write requests during refresh. By doing so, it is intended to prevent system failure due to missing input data.
[0012]
[Means for Solving the Problems]
In order to solve this problem, the access control method of the present invention is an access control method for arbitrating a plurality of access requests, and the priority of the refresh request is lower than the priority of the input data write request at any time. It is characterized by doing so.
[0013]
Furthermore, in the access control method for arbitrating a plurality of access requests, once the refresh operation is started, the priority of the refresh requests is a request other than the input data write request until the refresh execution remaining number counter falls below the threshold value. It is characterized by making it higher.
[0014]
Further, when the access target is a DRAM, the periodic refresh request acceptance timing is synchronized with the switching timing from the page mode to the normal mode.
[0015]
Next, the access control circuit according to the present invention counts up by a refresh clock signal input from the outside and decrements by a signal indicating that one refresh operation is completed, and a refresh request. An output refresh request generation circuit; an arbitration circuit that performs an arbitration operation between the refresh request and a plurality of other access requests; determines an access system to be accessed according to a predetermined priority; and an arbitration result of the arbitration circuit An access control signal generation circuit that generates an access signal according to the first access request, a first access request having a higher priority than the refresh request, and a priority higher than that of the first access request. A high second access request is included and the refresh execution When the value of the number counter is equal to the first threshold value or larger than the first threshold value, the value of the refresh execution remaining number counter is equal to the second threshold value lower than the first threshold value or the second threshold value. The refresh request is accepted until the threshold value becomes smaller than the threshold value, and when the second access request is generated while accepting the refresh request, the second execution request is made regardless of the value of the refresh execution remaining number counter. It is characterized by accepting access requests .
[0016]
Further, even if the first access request occurs until the value of the refresh execution remaining number counter becomes equal to the second threshold value or falls below the second threshold value, the first access request is changed. It is characterized by not accepting .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. There are various types of access. Hereinafter, a DRAM (memory) will be described as an example of an access target.
[0018]
FIG. 1 shows an access control circuit according to the first embodiment of the present invention, and FIG. 2 shows an access control method according to the first embodiment of the present invention.
[0019]
However, a description will be given using a refresh request as the first access request and a syndrome calculation access request as the second access request.
[0020]
In FIG. 1, 6 is a refresh request generating circuit that outputs a refresh request when the value of the refresh execution remaining counter 1 is other than 0, and 7 is the value of the refresh execution remaining counter 1 after the completion of the syndrome calculation access request. This is an arbitration circuit that has a function of making the priority of refresh requests higher than the priority of syndrome calculation access requests until the refresh request ends with 0, and arbitrates refresh requests, syndrome calculation access requests, and input data write requests. .
[0021]
Reference numeral 1 denotes a refresh execution remaining number counter, 4 denotes a memory control signal generation circuit, and 5 denotes a memory, which has the same configuration as the conventional example. The operation will be described below.
[0022]
Since DRAM needs to be refreshed 512 times within 8.2 msec, the refresh execution remaining number counter 1 is counted up with a clock of about 70 KHz, and the refresh execution remaining count is counted down to count the remaining number of refresh executions. When the count value is other than 0, refresh is requested from the refresh request generation circuit 6 to the arbitration circuit 7.
[0023]
Here, FIG. 2 shows an arbitration method of the arbitration circuit 7 of FIG. 1, wherein (A) is a refresh request and (B) is a syndrome calculation access request.
[0024]
This syndrome calculation access request increases access efficiency by continuously accessing the page mode. (C) is an input data write request. If the execution of this request is delayed too much, data writing will not be in time for data input, and the system will fail due to missing input data.
[0025]
Access priority is usually
Input data write request> syndrome operation access request> refresh request.
[0026]
(D) represents the count value of the remaining refresh execution counter 1 and (E) represents the arbitration result of the arbitration circuit 7.
[0027]
The refresh request has a lower priority than the syndrome calculation access request. In addition, since the syndrome operation access request is frequently accessed and is continuously accessed using the page mode, refreshing is not easily performed.
[0028]
Therefore, as shown in FIG. 2B, since the syndrome calculation process has a timing to return to the normal access from the page mode periodically due to the processing method or the DRAM configuration, the syndrome calculation access request is issued at this timing. Withdraw once. From the end of the syndrome calculation access request made in this way until the value of the refresh execution remaining number counter 1 becomes 0, the arbitration circuit 7 sets the priority of the refresh request higher than the syndrome calculation access request.
[0029]
By doing so, the page mode can be periodically refreshed without being interrupted unnecessarily, and the priority of refresh is lower than that of a high-priority input data write request. The input data writing is permitted even during the refresh as in the first request in), and the system failure due to the missing input data can be prevented.
[0030]
As described above, according to the present embodiment, it is possible to perform periodic refresh without causing unnecessary page mode interruption due to refresh execution, and the priority of refresh is a high-priority input data write request. Therefore, input data writing is permitted even during refresh, and system failure due to missing input data can be prevented.
[0031]
The memory access signal is generated by the memory control signal generation circuit 4 based on the arbitration result thus obtained, and the memory 5 is accessed.
[0032]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. There are various types of access. Hereinafter, a DRAM (memory) will be described as an access target.
[0033]
FIG. 3 shows an access control circuit according to the second embodiment of the present invention, and FIG. 4 shows an access control method according to the second embodiment of the present invention.
[0034]
In FIG. 3, reference numeral 8 has a function of successively raising the priority of refresh requests in response to an increase in the value of the remaining refresh execution counter 1, and includes an input data write request, a third access request, a syndrome calculation access request, It is an arbitration circuit that arbitrates refresh requests.
[0035]
The priority is usually
Input data write request> third access request> syndrome operation access request> refresh request.
[0036]
Note that 1 is a refresh execution remaining number counter, 4 is a memory control signal generation circuit, 5 is a memory, which is the same as the configuration of the conventional example, and 6 is a refresh request generation circuit, which is the same as the configuration of the first embodiment. is there. The operation will be described below.
[0037]
Since DRAM requires 512 refreshes within 8.2 msec, the refresh execution remaining counter 1 is counted up with a clock of about 70 kHz, and the refresh execution remaining counter 1 is counted down to count the remaining number of refresh executions. When the count value is other than 0, the refresh request generation circuit 6 requests the arbitration circuit 8 for refresh.
[0038]
Here, as shown in FIG. 4A, when the refresh request is not readily accepted and the value of the refresh execution remaining number counter 1 becomes equal to or greater than the second threshold value, the priority order of the refresh request is increased by one. (A) Refresh request> (B) Syndrome operation access request, prompting refresh execution. Thereafter, when the refresh execution results in a drop below a third threshold value that is smaller than the second threshold value, the priority of the refresh request is lowered.
[0039]
However, even if the priority of the refresh request increases by one, the value of the remaining refresh counter 1 continues to increase, and if the value exceeds the fourth threshold, the refresh priority is set as shown in FIG. Further, it is assumed that (A) refresh request> (F) third access request. Similarly, as long as the value of the refresh counter 1 increases, the priority of the refresh request is raised every time the threshold value determined in stages is exceeded.
[0040]
Then, as shown in FIG. 4C, priority is given when the value of the refresh execution remaining number counter 1 starts to decrease and becomes equal to or smaller than the second threshold or the third threshold set to a value smaller than the fourth threshold. Return the ranking.
[0041]
As described above, according to the present embodiment, the refresh priority is increased step by step in accordance with the increase in the refresh remaining number counter, so that the refresh can be executed according to the urgent level of the refresh request, and the refresh remaining number Since the priority of the refresh request is restored only after the counter value becomes small to some extent, the remaining number of refreshes can be surely reduced.
[0042]
By doing so, refresh can be executed without hindering access with high priority, such as an input data write request, and system failure due to missing write data can be prevented.
[0043]
In the first embodiment, the priority of the refresh request is made higher than the priority of the syndrome calculation access request until the value of the remaining refresh execution counter 1 becomes 0 and the refresh request is completed. However, a threshold is provided. The priority of the refresh request may be made higher than the priority of the syndrome calculation access request until the threshold is reached.
[0044]
In the first embodiment, the arbitration circuit 7 sets the priority of the refresh request to be higher than that of the syndrome calculation access request from the end of the syndrome calculation access request until the value of the refresh execution remaining number counter 1 becomes 0. Instead, the syndrome calculation access request may be terminated only at a predetermined interval.
[0045]
Further, in the first embodiment, after the syndrome calculation access request is completed, the priority of the refresh request is changed from the priority of the syndrome calculation access request until the value of the refresh execution remaining number counter 1 becomes 0 and the refresh request is completed. Alternatively, the syndrome calculation access request may not be reunited until the value of the refresh execution remaining number counter 1 reaches a predetermined threshold after the syndrome calculation access request ends.
[0046]
Although the above description has been made using a DRAM (memory) as an access target, it goes without saying that access control to other than the DRAM may be performed.
[0047]
【The invention's effect】
According to the present invention, refresh can be performed without hindering an access request having a high priority, such as an input data write request, and a system failure due to a lack of input data can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram of an access control circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing an access control method according to the first embodiment of the present invention. FIG. 4 is a diagram showing an access control method according to a second embodiment of the present invention. FIG. 5 is a diagram showing a conventional access control circuit. FIG. 6 is a diagram showing a conventional access control method. [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Refresh execution number counter 2 Refresh request generation circuit 3 Arbitration circuit 4 of conventional example Memory control signal generation circuit 5 Memory 6 Refresh request generation circuit 7 in the first embodiment of the present invention Arbitration in the first embodiment of the present invention Circuit 8 Arbitration circuit according to the second embodiment of the present invention

Claims (2)

A refresh remaining counter that is counted up by a refresh clock signal input from the outside and decremented by a signal indicating that one refresh operation is completed, a refresh request generation circuit that outputs a refresh request, and the refresh request And an arbitration circuit that performs an arbitration operation with a plurality of other access requests, determines an access system to be accessed according to a predetermined priority, and an access control signal generation circuit that generates an access signal according to the arbitration result of the arbitration circuit And the plurality of other access requests include a first access request having a higher priority than the refresh request and a second access request having a higher priority than the first access request. The value of the refresh execution remaining number counter is equal to the first threshold value. Alternatively, when the value is larger than the first threshold, the refresh request is accepted until the value of the remaining refresh execution counter becomes equal to a second threshold lower than the first threshold or smaller than the second threshold. during the refresh request receiving, when said second access request is generated, regardless of the value of the refresh execution remaining counter, along with receiving the second access request, said refresh execution remaining number Until the counter value becomes equal to or less than the second threshold value, even if the first access request is generated, the first access request is not accepted. An access control circuit. A refresh remaining counter that is counted up by a refresh clock signal input from the outside and decremented by a signal indicating that one refresh operation is completed, a refresh request generation circuit that outputs a refresh request, and the refresh request And an arbitration circuit that performs an arbitration operation with a plurality of other access requests, determines an access system to be accessed according to a predetermined priority, and an access control signal generation circuit that generates an access signal according to the arbitration result of the arbitration circuit And the plurality of other access requests include a first access request having a higher priority than the refresh request and a second access request having a higher priority than the first access request. The value of the refresh execution remaining number counter is equal to the first threshold value. Alternatively, when the value is larger than the first threshold, the priority of the refresh request is kept until the value of the remaining refresh execution counter becomes equal to a second threshold lower than the first threshold or smaller than the second threshold. If the second access request is generated while the highest priority is given and the refresh request is accepted, the priority of the second access request is set regardless of the value of the refresh execution remaining number counter. Even when the first access request is generated, the first access request is not increased until the value of the refresh execution remaining number counter becomes equal to the second threshold value or falls below the second threshold value. access control priority of access request characterized in that priority and operated to lower than the refresh request Road.

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